arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 simplefb_hdmi: framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  70                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  71                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  72                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 simplefb_lcd: framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  81                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  82                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  83                         status = "disabled";
  84                 };
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93                 clock-frequency = <24000000>;
  94                 arm,cpu-registers-not-fw-configured;
  95         };
  96
  97         cpus {
  98                 enable-method = "allwinner,sun6i-a31";
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 1008000 1200000
 111                                 864000  1200000
 112                                 720000  1100000
 113                                 480000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                 };
 117
 118                 cpu1: cpu@1 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         reg = <1>;
 122                         clocks = <&ccu CLK_CPU>;
 123                         clock-latency = <244144>; /* 8 32k periods */
 124                         operating-points = <
 125                                 /* kHz    uV */
 126                                 1008000 1200000
 127                                 864000  1200000
 128                                 720000  1100000
 129                                 480000  1000000
 130                                 >;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu2: cpu@2 {
 135                         compatible = "arm,cortex-a7";
 136                         device_type = "cpu";
 137                         reg = <2>;
 138                         clocks = <&ccu CLK_CPU>;
 139                         clock-latency = <244144>; /* 8 32k periods */
 140                         operating-points = <
 141                                 /* kHz    uV */
 142                                 1008000 1200000
 143                                 864000  1200000
 144                                 720000  1100000
 145                                 480000  1000000
 146                                 >;
 147                         #cooling-cells = <2>;
 148                 };
 149
 150                 cpu3: cpu@3 {
 151                         compatible = "arm,cortex-a7";
 152                         device_type = "cpu";
 153                         reg = <3>;
 154                         clocks = <&ccu CLK_CPU>;
 155                         clock-latency = <244144>; /* 8 32k periods */
 156                         operating-points = <
 157                                 /* kHz    uV */
 158                                 1008000 1200000
 159                                 864000  1200000
 160                                 720000  1100000
 161                                 480000  1000000
 162                                 >;
 163                         #cooling-cells = <2>;
 164                 };
 165         };
 166
 167         thermal-zones {
 168                 cpu-thermal {
 169                         /* milliseconds */
 170                         polling-delay-passive = <250>;
 171                         polling-delay = <1000>;
 172                         thermal-sensors = <&rtp>;
 173
 174                         cooling-maps {
 175                                 map0 {
 176                                         trip = <&cpu_alert0>;
 177                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 178                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 179                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182                         };
 183
 184                         trips {
 185                                 cpu_alert0: cpu_alert0 {
 186                                         /* milliCelsius */
 187                                         temperature = <70000>;
 188                                         hysteresis = <2000>;
 189                                         type = "passive";
 190                                 };
 191
 192                                 cpu_crit: cpu_crit {
 193                                         /* milliCelsius */
 194                                         temperature = <100000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200         };
 201
 202         pmu {
 203                 compatible = "arm,cortex-a7-pmu";
 204                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 208         };
 209
 210         clocks {
 211                 #address-cells = <1>;
 212                 #size-cells = <1>;
 213                 ranges;
 214
 215                 osc24M: clk-24M {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <24000000>;
 219                         clock-accuracy = <50000>;
 220                         clock-output-names = "osc24M";
 221                 };
 222
 223                 osc32k: clk-32k {
 224                         #clock-cells = <0>;
 225                         compatible = "fixed-clock";
 226                         clock-frequency = <32768>;
 227                         clock-accuracy = <50000>;
 228                         clock-output-names = "ext_osc32k";
 229                 };
 230
 231                 /*
 232                  * The following two are dummy clocks, placeholders
 233                  * used in the gmac_tx clock. The gmac driver will
 234                  * choose one parent depending on the PHY interface
 235                  * mode, using clk_set_rate auto-reparenting.
 236                  *
 237                  * The actual TX clock rate is not controlled by the
 238                  * gmac_tx clock.
 239                  */
 240                 mii_phy_tx_clk: clk-mii-phy-tx {
 241                         #clock-cells = <0>;
 242                         compatible = "fixed-clock";
 243                         clock-frequency = <25000000>;
 244                         clock-output-names = "mii_phy_tx";
 245                 };
 246
 247                 gmac_int_tx_clk: clk-gmac-int-tx {
 248                         #clock-cells = <0>;
 249                         compatible = "fixed-clock";
 250                         clock-frequency = <125000000>;
 251                         clock-output-names = "gmac_int_tx";
 252                 };
 253
 254                 gmac_tx_clk: clk@1c200d0 {
 255                         #clock-cells = <0>;
 256                         compatible = "allwinner,sun7i-a20-gmac-clk";
 257                         reg = <0x01c200d0 0x4>;
 258                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 259                         clock-output-names = "gmac_tx";
 260                 };
 261         };
 262
 263         de: display-engine {
 264                 compatible = "allwinner,sun6i-a31-display-engine";
 265                 allwinner,pipelines = <&fe0>, <&fe1>;
 266                 status = "disabled";
 267         };
 268
 269         soc {
 270                 compatible = "simple-bus";
 271                 #address-cells = <1>;
 272                 #size-cells = <1>;
 273                 ranges;
 274
 275                 dma: dma-controller@1c02000 {
 276                         compatible = "allwinner,sun6i-a31-dma";
 277                         reg = <0x01c02000 0x1000>;
 278                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&ccu CLK_AHB1_DMA>;
 280                         resets = <&ccu RST_AHB1_DMA>;
 281                         #dma-cells = <1>;
 282                 };
 283
 284                 tcon0: lcd-controller@1c0c000 {
 285                         compatible = "allwinner,sun6i-a31-tcon";
 286                         reg = <0x01c0c000 0x1000>;
 287                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 288                         dmas = <&dma 11>;
 289                         resets = <&ccu RST_AHB1_LCD0>,
 290                                  <&ccu RST_AHB1_LVDS>;
 291                         reset-names = "lcd",
 292                                       "lvds";
 293                         clocks = <&ccu CLK_AHB1_LCD0>,
 294                                  <&ccu CLK_LCD0_CH0>,
 295                                  <&ccu CLK_LCD0_CH1>,
 296                                  <&ccu 15>;
 297                         clock-names = "ahb",
 298                                       "tcon-ch0",
 299                                       "tcon-ch1",
 300                                       "lvds-alt";
 301                         clock-output-names = "tcon0-pixel-clock";
 302                         #clock-cells = <0>;
 303
 304                         ports {
 305                                 #address-cells = <1>;
 306                                 #size-cells = <0>;
 307
 308                                 tcon0_in: port@0 {
 309                                         #address-cells = <1>;
 310                                         #size-cells = <0>;
 311                                         reg = <0>;
 312
 313                                         tcon0_in_drc0: endpoint@0 {
 314                                                 reg = <0>;
 315                                                 remote-endpoint = <&drc0_out_tcon0>;
 316                                         };
 317
 318                                         tcon0_in_drc1: endpoint@1 {
 319                                                 reg = <1>;
 320                                                 remote-endpoint = <&drc1_out_tcon0>;
 321                                         };
 322                                 };
 323
 324                                 tcon0_out: port@1 {
 325                                         #address-cells = <1>;
 326                                         #size-cells = <0>;
 327                                         reg = <1>;
 328
 329                                         tcon0_out_hdmi: endpoint@1 {
 330                                                 reg = <1>;
 331                                                 remote-endpoint = <&hdmi_in_tcon0>;
 332                                                 allwinner,tcon-channel = <1>;
 333                                         };
 334                                 };
 335                         };
 336                 };
 337
 338                 tcon1: lcd-controller@1c0d000 {
 339                         compatible = "allwinner,sun6i-a31-tcon";
 340                         reg = <0x01c0d000 0x1000>;
 341                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 342                         dmas = <&dma 12>;
 343                         resets = <&ccu RST_AHB1_LCD1>,
 344                                  <&ccu RST_AHB1_LVDS>;
 345                         reset-names = "lcd", "lvds";
 346                         clocks = <&ccu CLK_AHB1_LCD1>,
 347                                  <&ccu CLK_LCD1_CH0>,
 348                                  <&ccu CLK_LCD1_CH1>,
 349                                  <&ccu 15>;
 350                         clock-names = "ahb",
 351                                       "tcon-ch0",
 352                                       "tcon-ch1",
 353                                       "lvds-alt";
 354                         clock-output-names = "tcon1-pixel-clock";
 355                         #clock-cells = <0>;
 356
 357                         ports {
 358                                 #address-cells = <1>;
 359                                 #size-cells = <0>;
 360
 361                                 tcon1_in: port@0 {
 362                                         #address-cells = <1>;
 363                                         #size-cells = <0>;
 364                                         reg = <0>;
 365
 366                                         tcon1_in_drc0: endpoint@0 {
 367                                                 reg = <0>;
 368                                                 remote-endpoint = <&drc0_out_tcon1>;
 369                                         };
 370
 371                                         tcon1_in_drc1: endpoint@1 {
 372                                                 reg = <1>;
 373                                                 remote-endpoint = <&drc1_out_tcon1>;
 374                                         };
 375                                 };
 376
 377                                 tcon1_out: port@1 {
 378                                         #address-cells = <1>;
 379                                         #size-cells = <0>;
 380                                         reg = <1>;
 381
 382                                         tcon1_out_hdmi: endpoint@1 {
 383                                                 reg = <1>;
 384                                                 remote-endpoint = <&hdmi_in_tcon1>;
 385                                                 allwinner,tcon-channel = <1>;
 386                                         };
 387                                 };
 388                         };
 389                 };
 390
 391                 mmc0: mmc@1c0f000 {
 392                         compatible = "allwinner,sun7i-a20-mmc";
 393                         reg = <0x01c0f000 0x1000>;
 394                         clocks = <&ccu CLK_AHB1_MMC0>,
 395                                  <&ccu CLK_MMC0>,
 396                                  <&ccu CLK_MMC0_OUTPUT>,
 397                                  <&ccu CLK_MMC0_SAMPLE>;
 398                         clock-names = "ahb",
 399                                       "mmc",
 400                                       "output",
 401                                       "sample";
 402                         resets = <&ccu RST_AHB1_MMC0>;
 403                         reset-names = "ahb";
 404                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 405                         pinctrl-names = "default";
 406                         pinctrl-0 = <&mmc0_pins>;
 407                         status = "disabled";
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                 };
 411
 412                 mmc1: mmc@1c10000 {
 413                         compatible = "allwinner,sun7i-a20-mmc";
 414                         reg = <0x01c10000 0x1000>;
 415                         clocks = <&ccu CLK_AHB1_MMC1>,
 416                                  <&ccu CLK_MMC1>,
 417                                  <&ccu CLK_MMC1_OUTPUT>,
 418                                  <&ccu CLK_MMC1_SAMPLE>;
 419                         clock-names = "ahb",
 420                                       "mmc",
 421                                       "output",
 422                                       "sample";
 423                         resets = <&ccu RST_AHB1_MMC1>;
 424                         reset-names = "ahb";
 425                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&mmc1_pins>;
 428                         status = "disabled";
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                 };
 432
 433                 mmc2: mmc@1c11000 {
 434                         compatible = "allwinner,sun7i-a20-mmc";
 435                         reg = <0x01c11000 0x1000>;
 436                         clocks = <&ccu CLK_AHB1_MMC2>,
 437                                  <&ccu CLK_MMC2>,
 438                                  <&ccu CLK_MMC2_OUTPUT>,
 439                                  <&ccu CLK_MMC2_SAMPLE>;
 440                         clock-names = "ahb",
 441                                       "mmc",
 442                                       "output",
 443                                       "sample";
 444                         resets = <&ccu RST_AHB1_MMC2>;
 445                         reset-names = "ahb";
 446                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 447                         status = "disabled";
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                 };
 451
 452                 mmc3: mmc@1c12000 {
 453                         compatible = "allwinner,sun7i-a20-mmc";
 454                         reg = <0x01c12000 0x1000>;
 455                         clocks = <&ccu CLK_AHB1_MMC3>,
 456                                  <&ccu CLK_MMC3>,
 457                                  <&ccu CLK_MMC3_OUTPUT>,
 458                                  <&ccu CLK_MMC3_SAMPLE>;
 459                         clock-names = "ahb",
 460                                       "mmc",
 461                                       "output",
 462                                       "sample";
 463                         resets = <&ccu RST_AHB1_MMC3>;
 464                         reset-names = "ahb";
 465                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 466                         status = "disabled";
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                 };
 470
 471                 hdmi: hdmi@1c16000 {
 472                         compatible = "allwinner,sun6i-a31-hdmi";
 473                         reg = <0x01c16000 0x1000>;
 474                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 475                         clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
 476                                  <&ccu CLK_HDMI_DDC>,
 477                                  <&ccu CLK_PLL_VIDEO0_2X>,
 478                                  <&ccu CLK_PLL_VIDEO1_2X>;
 479                         clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
 480                         resets = <&ccu RST_AHB1_HDMI>;
 481                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 482                         dmas = <&dma 13>, <&dma 13>, <&dma 14>;
 483                         status = "disabled";
 484
 485                         ports {
 486                                 #address-cells = <1>;
 487                                 #size-cells = <0>;
 488
 489                                 hdmi_in: port@0 {
 490                                         #address-cells = <1>;
 491                                         #size-cells = <0>;
 492                                         reg = <0>;
 493
 494                                         hdmi_in_tcon0: endpoint@0 {
 495                                                 reg = <0>;
 496                                                 remote-endpoint = <&tcon0_out_hdmi>;
 497                                         };
 498
 499                                         hdmi_in_tcon1: endpoint@1 {
 500                                                 reg = <1>;
 501                                                 remote-endpoint = <&tcon1_out_hdmi>;
 502                                         };
 503                                 };
 504
 505                                 hdmi_out: port@1 {
 506                                         reg = <1>;
 507                                 };
 508                         };
 509                 };
 510
 511                 usb_otg: usb@1c19000 {
 512                         compatible = "allwinner,sun6i-a31-musb";
 513                         reg = <0x01c19000 0x0400>;
 514                         clocks = <&ccu CLK_AHB1_OTG>;
 515                         resets = <&ccu RST_AHB1_OTG>;
 516                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 517                         interrupt-names = "mc";
 518                         phys = <&usbphy 0>;
 519                         phy-names = "usb";
 520                         extcon = <&usbphy 0>;
 521                         dr_mode = "otg";
 522                         status = "disabled";
 523                 };
 524
 525                 usbphy: phy@1c19400 {
 526                         compatible = "allwinner,sun6i-a31-usb-phy";
 527                         reg = <0x01c19400 0x10>,
 528                               <0x01c1a800 0x4>,
 529                               <0x01c1b800 0x4>;
 530                         reg-names = "phy_ctrl",
 531                                     "pmu1",
 532                                     "pmu2";
 533                         clocks = <&ccu CLK_USB_PHY0>,
 534                                  <&ccu CLK_USB_PHY1>,
 535                                  <&ccu CLK_USB_PHY2>;
 536                         clock-names = "usb0_phy",
 537                                       "usb1_phy",
 538                                       "usb2_phy";
 539                         resets = <&ccu RST_USB_PHY0>,
 540                                  <&ccu RST_USB_PHY1>,
 541                                  <&ccu RST_USB_PHY2>;
 542                         reset-names = "usb0_reset",
 543                                       "usb1_reset",
 544                                       "usb2_reset";
 545                         status = "disabled";
 546                         #phy-cells = <1>;
 547                 };
 548
 549                 ehci0: usb@1c1a000 {
 550                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 551                         reg = <0x01c1a000 0x100>;
 552                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 553                         clocks = <&ccu CLK_AHB1_EHCI0>;
 554                         resets = <&ccu RST_AHB1_EHCI0>;
 555                         phys = <&usbphy 1>;
 556                         phy-names = "usb";
 557                         status = "disabled";
 558                 };
 559
 560                 ohci0: usb@1c1a400 {
 561                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 562                         reg = <0x01c1a400 0x100>;
 563                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 565                         resets = <&ccu RST_AHB1_OHCI0>;
 566                         phys = <&usbphy 1>;
 567                         phy-names = "usb";
 568                         status = "disabled";
 569                 };
 570
 571                 ehci1: usb@1c1b000 {
 572                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 573                         reg = <0x01c1b000 0x100>;
 574                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&ccu CLK_AHB1_EHCI1>;
 576                         resets = <&ccu RST_AHB1_EHCI1>;
 577                         phys = <&usbphy 2>;
 578                         phy-names = "usb";
 579                         status = "disabled";
 580                 };
 581
 582                 ohci1: usb@1c1b400 {
 583                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 584                         reg = <0x01c1b400 0x100>;
 585                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 587                         resets = <&ccu RST_AHB1_OHCI1>;
 588                         phys = <&usbphy 2>;
 589                         phy-names = "usb";
 590                         status = "disabled";
 591                 };
 592
 593                 ohci2: usb@1c1c400 {
 594                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 595                         reg = <0x01c1c400 0x100>;
 596                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 597                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 598                         resets = <&ccu RST_AHB1_OHCI2>;
 599                         status = "disabled";
 600                 };
 601
 602                 ccu: clock@1c20000 {
 603                         compatible = "allwinner,sun6i-a31-ccu";
 604                         reg = <0x01c20000 0x400>;
 605                         clocks = <&osc24M>, <&rtc 0>;
 606                         clock-names = "hosc", "losc";
 607                         #clock-cells = <1>;
 608                         #reset-cells = <1>;
 609                 };
 610
 611                 pio: pinctrl@1c20800 {
 612                         compatible = "allwinner,sun6i-a31-pinctrl";
 613                         reg = <0x01c20800 0x400>;
 614                         interrupt-parent = <&r_intc>;
 615                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 618                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
 620                         clock-names = "apb", "hosc", "losc";
 621                         gpio-controller;
 622                         interrupt-controller;
 623                         #interrupt-cells = <3>;
 624                         #gpio-cells = <3>;
 625
 626                         gmac_gmii_pins: gmac-gmii-pins {
 627                                 pins = "PA0", "PA1", "PA2", "PA3",
 628                                                 "PA4", "PA5", "PA6", "PA7",
 629                                                 "PA8", "PA9", "PA10", "PA11",
 630                                                 "PA12", "PA13", "PA14", "PA15",
 631                                                 "PA16", "PA17", "PA18", "PA19",
 632                                                 "PA20", "PA21", "PA22", "PA23",
 633                                                 "PA24", "PA25", "PA26", "PA27";
 634                                 function = "gmac";
 635                                 /*
 636                                  * data lines in GMII mode run at 125MHz and
 637                                  * might need a higher signal drive strength
 638                                  */
 639                                 drive-strength = <30>;
 640                         };
 641
 642                         gmac_mii_pins: gmac-mii-pins {
 643                                 pins = "PA0", "PA1", "PA2", "PA3",
 644                                                 "PA8", "PA9", "PA11",
 645                                                 "PA12", "PA13", "PA14", "PA19",
 646                                                 "PA20", "PA21", "PA22", "PA23",
 647                                                 "PA24", "PA26", "PA27";
 648                                 function = "gmac";
 649                         };
 650
 651                         gmac_rgmii_pins: gmac-rgmii-pins {
 652                                 pins = "PA0", "PA1", "PA2", "PA3",
 653                                                 "PA9", "PA10", "PA11",
 654                                                 "PA12", "PA13", "PA14", "PA19",
 655                                                 "PA20", "PA25", "PA26", "PA27";
 656                                 function = "gmac";
 657                                 /*
 658                                  * data lines in RGMII mode use DDR mode
 659                                  * and need a higher signal drive strength
 660                                  */
 661                                 drive-strength = <40>;
 662                         };
 663
 664                         i2c0_pins: i2c0-pins {
 665                                 pins = "PH14", "PH15";
 666                                 function = "i2c0";
 667                         };
 668
 669                         i2c1_pins: i2c1-pins {
 670                                 pins = "PH16", "PH17";
 671                                 function = "i2c1";
 672                         };
 673
 674                         i2c2_pins: i2c2-pins {
 675                                 pins = "PH18", "PH19";
 676                                 function = "i2c2";
 677                         };
 678
 679                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 680                                 pins = "PD0", "PD1", "PD2", "PD3",
 681                                                  "PD4", "PD5", "PD6", "PD7",
 682                                                  "PD8", "PD9", "PD10", "PD11",
 683                                                  "PD12", "PD13", "PD14", "PD15",
 684                                                  "PD16", "PD17", "PD18", "PD19",
 685                                                  "PD20", "PD21", "PD22", "PD23",
 686                                                  "PD24", "PD25", "PD26", "PD27";
 687                                 function = "lcd0";
 688                         };
 689
 690                         mmc0_pins: mmc0-pins {
 691                                 pins = "PF0", "PF1", "PF2",
 692                                                  "PF3", "PF4", "PF5";
 693                                 function = "mmc0";
 694                                 drive-strength = <30>;
 695                                 bias-pull-up;
 696                         };
 697
 698                         mmc1_pins: mmc1-pins {
 699                                 pins = "PG0", "PG1", "PG2", "PG3",
 700                                                  "PG4", "PG5";
 701                                 function = "mmc1";
 702                                 drive-strength = <30>;
 703                                 bias-pull-up;
 704                         };
 705
 706                         mmc2_4bit_pins: mmc2-4bit-pins {
 707                                 pins = "PC6", "PC7", "PC8", "PC9",
 708                                                  "PC10", "PC11";
 709                                 function = "mmc2";
 710                                 drive-strength = <30>;
 711                                 bias-pull-up;
 712                         };
 713
 714                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 715                                 pins = "PC6", "PC7", "PC8", "PC9",
 716                                                  "PC10", "PC11", "PC12",
 717                                                  "PC13", "PC14", "PC15",
 718                                                  "PC24";
 719                                 function = "mmc2";
 720                                 drive-strength = <30>;
 721                                 bias-pull-up;
 722                         };
 723
 724                         mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
 725                                 pins = "PC6", "PC7", "PC8", "PC9",
 726                                                  "PC10", "PC11", "PC12",
 727                                                  "PC13", "PC14", "PC15",
 728                                                  "PC24";
 729                                 function = "mmc3";
 730                                 drive-strength = <40>;
 731                                 bias-pull-up;
 732                         };
 733
 734                         spdif_tx_pin: spdif-tx-pin {
 735                                 pins = "PH28";
 736                                 function = "spdif";
 737                         };
 738
 739                         uart0_ph_pins: uart0-ph-pins {
 740                                 pins = "PH20", "PH21";
 741                                 function = "uart0";
 742                         };
 743                 };
 744
 745                 timer@1c20c00 {
 746                         compatible = "allwinner,sun4i-a10-timer";
 747                         reg = <0x01c20c00 0xa0>;
 748                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 754                         clocks = <&osc24M>;
 755                 };
 756
 757                 wdt1: watchdog@1c20ca0 {
 758                         compatible = "allwinner,sun6i-a31-wdt";
 759                         reg = <0x01c20ca0 0x20>;
 760                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&osc24M>;
 762                 };
 763
 764                 spdif: spdif@1c21000 {
 765                         #sound-dai-cells = <0>;
 766                         compatible = "allwinner,sun6i-a31-spdif";
 767                         reg = <0x01c21000 0x400>;
 768                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 769                         clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
 770                         resets = <&ccu RST_APB1_SPDIF>;
 771                         clock-names = "apb", "spdif";
 772                         dmas = <&dma 2>, <&dma 2>;
 773                         dma-names = "rx", "tx";
 774                         status = "disabled";
 775                 };
 776
 777                 i2s0: i2s@1c22000 {
 778                         #sound-dai-cells = <0>;
 779                         compatible = "allwinner,sun6i-a31-i2s";
 780                         reg = <0x01c22000 0x400>;
 781                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 782                         clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
 783                         resets = <&ccu RST_APB1_DAUDIO0>;
 784                         clock-names = "apb", "mod";
 785                         dmas = <&dma 3>, <&dma 3>;
 786                         dma-names = "rx", "tx";
 787                         status = "disabled";
 788                 };
 789
 790                 i2s1: i2s@1c22400 {
 791                         #sound-dai-cells = <0>;
 792                         compatible = "allwinner,sun6i-a31-i2s";
 793                         reg = <0x01c22400 0x400>;
 794                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
 796                         resets = <&ccu RST_APB1_DAUDIO1>;
 797                         clock-names = "apb", "mod";
 798                         dmas = <&dma 4>, <&dma 4>;
 799                         dma-names = "rx", "tx";
 800                         status = "disabled";
 801                 };
 802
 803                 lradc: lradc@1c22800 {
 804                         compatible = "allwinner,sun4i-a10-lradc-keys";
 805                         reg = <0x01c22800 0x100>;
 806                         interrupt-parent = <&r_intc>;
 807                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 808                         status = "disabled";
 809                 };
 810
 811                 rtp: rtp@1c25000 {
 812                         compatible = "allwinner,sun6i-a31-ts";
 813                         reg = <0x01c25000 0x100>;
 814                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 815                         #thermal-sensor-cells = <0>;
 816                 };
 817
 818                 uart0: serial@1c28000 {
 819                         compatible = "snps,dw-apb-uart";
 820                         reg = <0x01c28000 0x400>;
 821                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 822                         reg-shift = <2>;
 823                         reg-io-width = <4>;
 824                         clocks = <&ccu CLK_APB2_UART0>;
 825                         resets = <&ccu RST_APB2_UART0>;
 826                         dmas = <&dma 6>, <&dma 6>;
 827                         dma-names = "rx", "tx";
 828                         status = "disabled";
 829                 };
 830
 831                 uart1: serial@1c28400 {
 832                         compatible = "snps,dw-apb-uart";
 833                         reg = <0x01c28400 0x400>;
 834                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 835                         reg-shift = <2>;
 836                         reg-io-width = <4>;
 837                         clocks = <&ccu CLK_APB2_UART1>;
 838                         resets = <&ccu RST_APB2_UART1>;
 839                         dmas = <&dma 7>, <&dma 7>;
 840                         dma-names = "rx", "tx";
 841                         status = "disabled";
 842                 };
 843
 844                 uart2: serial@1c28800 {
 845                         compatible = "snps,dw-apb-uart";
 846                         reg = <0x01c28800 0x400>;
 847                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 848                         reg-shift = <2>;
 849                         reg-io-width = <4>;
 850                         clocks = <&ccu CLK_APB2_UART2>;
 851                         resets = <&ccu RST_APB2_UART2>;
 852                         dmas = <&dma 8>, <&dma 8>;
 853                         dma-names = "rx", "tx";
 854                         status = "disabled";
 855                 };
 856
 857                 uart3: serial@1c28c00 {
 858                         compatible = "snps,dw-apb-uart";
 859                         reg = <0x01c28c00 0x400>;
 860                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 861                         reg-shift = <2>;
 862                         reg-io-width = <4>;
 863                         clocks = <&ccu CLK_APB2_UART3>;
 864                         resets = <&ccu RST_APB2_UART3>;
 865                         dmas = <&dma 9>, <&dma 9>;
 866                         dma-names = "rx", "tx";
 867                         status = "disabled";
 868                 };
 869
 870                 uart4: serial@1c29000 {
 871                         compatible = "snps,dw-apb-uart";
 872                         reg = <0x01c29000 0x400>;
 873                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 874                         reg-shift = <2>;
 875                         reg-io-width = <4>;
 876                         clocks = <&ccu CLK_APB2_UART4>;
 877                         resets = <&ccu RST_APB2_UART4>;
 878                         dmas = <&dma 10>, <&dma 10>;
 879                         dma-names = "rx", "tx";
 880                         status = "disabled";
 881                 };
 882
 883                 uart5: serial@1c29400 {
 884                         compatible = "snps,dw-apb-uart";
 885                         reg = <0x01c29400 0x400>;
 886                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 887                         reg-shift = <2>;
 888                         reg-io-width = <4>;
 889                         clocks = <&ccu CLK_APB2_UART5>;
 890                         resets = <&ccu RST_APB2_UART5>;
 891                         dmas = <&dma 22>, <&dma 22>;
 892                         dma-names = "rx", "tx";
 893                         status = "disabled";
 894                 };
 895
 896                 i2c0: i2c@1c2ac00 {
 897                         compatible = "allwinner,sun6i-a31-i2c";
 898                         reg = <0x01c2ac00 0x400>;
 899                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 900                         clocks = <&ccu CLK_APB2_I2C0>;
 901                         resets = <&ccu RST_APB2_I2C0>;
 902                         pinctrl-names = "default";
 903                         pinctrl-0 = <&i2c0_pins>;
 904                         status = "disabled";
 905                         #address-cells = <1>;
 906                         #size-cells = <0>;
 907                 };
 908
 909                 i2c1: i2c@1c2b000 {
 910                         compatible = "allwinner,sun6i-a31-i2c";
 911                         reg = <0x01c2b000 0x400>;
 912                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 913                         clocks = <&ccu CLK_APB2_I2C1>;
 914                         resets = <&ccu RST_APB2_I2C1>;
 915                         pinctrl-names = "default";
 916                         pinctrl-0 = <&i2c1_pins>;
 917                         status = "disabled";
 918                         #address-cells = <1>;
 919                         #size-cells = <0>;
 920                 };
 921
 922                 i2c2: i2c@1c2b400 {
 923                         compatible = "allwinner,sun6i-a31-i2c";
 924                         reg = <0x01c2b400 0x400>;
 925                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 926                         clocks = <&ccu CLK_APB2_I2C2>;
 927                         resets = <&ccu RST_APB2_I2C2>;
 928                         pinctrl-names = "default";
 929                         pinctrl-0 = <&i2c2_pins>;
 930                         status = "disabled";
 931                         #address-cells = <1>;
 932                         #size-cells = <0>;
 933                 };
 934
 935                 i2c3: i2c@1c2b800 {
 936                         compatible = "allwinner,sun6i-a31-i2c";
 937                         reg = <0x01c2b800 0x400>;
 938                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 939                         clocks = <&ccu CLK_APB2_I2C3>;
 940                         resets = <&ccu RST_APB2_I2C3>;
 941                         status = "disabled";
 942                         #address-cells = <1>;
 943                         #size-cells = <0>;
 944                 };
 945
 946                 gmac: ethernet@1c30000 {
 947                         compatible = "allwinner,sun7i-a20-gmac";
 948                         reg = <0x01c30000 0x1054>;
 949                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 950                         interrupt-names = "macirq";
 951                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 952                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 953                         resets = <&ccu RST_AHB1_EMAC>;
 954                         reset-names = "stmmaceth";
 955                         snps,pbl = <2>;
 956                         snps,fixed-burst;
 957                         snps,force_sf_dma_mode;
 958                         status = "disabled";
 959
 960                         mdio: mdio {
 961                                 compatible = "snps,dwmac-mdio";
 962                                 #address-cells = <1>;
 963                                 #size-cells = <0>;
 964                         };
 965                 };
 966
 967                 crypto: crypto-engine@1c15000 {
 968                         compatible = "allwinner,sun6i-a31-crypto",
 969                                      "allwinner,sun4i-a10-crypto";
 970                         reg = <0x01c15000 0x1000>;
 971                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 973                         clock-names = "ahb", "mod";
 974                         resets = <&ccu RST_AHB1_SS>;
 975                         reset-names = "ahb";
 976                 };
 977
 978                 codec: codec@1c22c00 {
 979                         #sound-dai-cells = <0>;
 980                         compatible = "allwinner,sun6i-a31-codec";
 981                         reg = <0x01c22c00 0x400>;
 982                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 983                         clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
 984                         clock-names = "apb", "codec";
 985                         resets = <&ccu RST_APB1_CODEC>;
 986                         dmas = <&dma 15>, <&dma 15>;
 987                         dma-names = "rx", "tx";
 988                         status = "disabled";
 989                 };
 990
 991                 timer@1c60000 {
 992                         compatible = "allwinner,sun6i-a31-hstimer",
 993                                      "allwinner,sun7i-a20-hstimer";
 994                         reg = <0x01c60000 0x1000>;
 995                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 997                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 998                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 999                         clocks = <&ccu CLK_AHB1_HSTIMER>;
1000                         resets = <&ccu RST_AHB1_HSTIMER>;
1001                 };
1002
1003                 spi0: spi@1c68000 {
1004                         compatible = "allwinner,sun6i-a31-spi";
1005                         reg = <0x01c68000 0x1000>;
1006                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1007                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1008                         clock-names = "ahb", "mod";
1009                         dmas = <&dma 23>, <&dma 23>;
1010                         dma-names = "rx", "tx";
1011                         resets = <&ccu RST_AHB1_SPI0>;
1012                         status = "disabled";
1013                         #address-cells = <1>;
1014                         #size-cells = <0>;
1015                 };
1016
1017                 spi1: spi@1c69000 {
1018                         compatible = "allwinner,sun6i-a31-spi";
1019                         reg = <0x01c69000 0x1000>;
1020                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1021                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1022                         clock-names = "ahb", "mod";
1023                         dmas = <&dma 24>, <&dma 24>;
1024                         dma-names = "rx", "tx";
1025                         resets = <&ccu RST_AHB1_SPI1>;
1026                         status = "disabled";
1027                         #address-cells = <1>;
1028                         #size-cells = <0>;
1029                 };
1030
1031                 spi2: spi@1c6a000 {
1032                         compatible = "allwinner,sun6i-a31-spi";
1033                         reg = <0x01c6a000 0x1000>;
1034                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1035                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1036                         clock-names = "ahb", "mod";
1037                         dmas = <&dma 25>, <&dma 25>;
1038                         dma-names = "rx", "tx";
1039                         resets = <&ccu RST_AHB1_SPI2>;
1040                         status = "disabled";
1041                         #address-cells = <1>;
1042                         #size-cells = <0>;
1043                 };
1044
1045                 spi3: spi@1c6b000 {
1046                         compatible = "allwinner,sun6i-a31-spi";
1047                         reg = <0x01c6b000 0x1000>;
1048                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1049                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1050                         clock-names = "ahb", "mod";
1051                         dmas = <&dma 26>, <&dma 26>;
1052                         dma-names = "rx", "tx";
1053                         resets = <&ccu RST_AHB1_SPI3>;
1054                         status = "disabled";
1055                         #address-cells = <1>;
1056                         #size-cells = <0>;
1057                 };
1058
1059                 gic: interrupt-controller@1c81000 {
1060                         compatible = "arm,gic-400";
1061                         reg = <0x01c81000 0x1000>,
1062                               <0x01c82000 0x2000>,
1063                               <0x01c84000 0x2000>,
1064                               <0x01c86000 0x2000>;
1065                         interrupt-controller;
1066                         #interrupt-cells = <3>;
1067                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1068                 };
1069
1070                 fe0: display-frontend@1e00000 {
1071                         compatible = "allwinner,sun6i-a31-display-frontend";
1072                         reg = <0x01e00000 0x20000>;
1073                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1074                         clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1075                                  <&ccu CLK_DRAM_FE0>;
1076                         clock-names = "ahb", "mod",
1077                                       "ram";
1078                         resets = <&ccu RST_AHB1_FE0>;
1079
1080                         ports {
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083
1084                                 fe0_out: port@1 {
1085                                         #address-cells = <1>;
1086                                         #size-cells = <0>;
1087                                         reg = <1>;
1088
1089                                         fe0_out_be0: endpoint@0 {
1090                                                 reg = <0>;
1091                                                 remote-endpoint = <&be0_in_fe0>;
1092                                         };
1093
1094                                         fe0_out_be1: endpoint@1 {
1095                                                 reg = <1>;
1096                                                 remote-endpoint = <&be1_in_fe0>;
1097                                         };
1098                                 };
1099                         };
1100                 };
1101
1102                 fe1: display-frontend@1e20000 {
1103                         compatible = "allwinner,sun6i-a31-display-frontend";
1104                         reg = <0x01e20000 0x20000>;
1105                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1106                         clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1107                                  <&ccu CLK_DRAM_FE1>;
1108                         clock-names = "ahb", "mod",
1109                                       "ram";
1110                         resets = <&ccu RST_AHB1_FE1>;
1111
1112                         ports {
1113                                 #address-cells = <1>;
1114                                 #size-cells = <0>;
1115
1116                                 fe1_out: port@1 {
1117                                         #address-cells = <1>;
1118                                         #size-cells = <0>;
1119                                         reg = <1>;
1120
1121                                         fe1_out_be0: endpoint@0 {
1122                                                 reg = <0>;
1123                                                 remote-endpoint = <&be0_in_fe1>;
1124                                         };
1125
1126                                         fe1_out_be1: endpoint@1 {
1127                                                 reg = <1>;
1128                                                 remote-endpoint = <&be1_in_fe1>;
1129                                         };
1130                                 };
1131                         };
1132                 };
1133
1134                 be1: display-backend@1e40000 {
1135                         compatible = "allwinner,sun6i-a31-display-backend";
1136                         reg = <0x01e40000 0x10000>;
1137                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1138                         clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1139                                  <&ccu CLK_DRAM_BE1>;
1140                         clock-names = "ahb", "mod",
1141                                       "ram";
1142                         resets = <&ccu RST_AHB1_BE1>;
1143
1144                         ports {
1145                                 #address-cells = <1>;
1146                                 #size-cells = <0>;
1147
1148                                 be1_in: port@0 {
1149                                         #address-cells = <1>;
1150                                         #size-cells = <0>;
1151                                         reg = <0>;
1152
1153                                         be1_in_fe0: endpoint@0 {
1154                                                 reg = <0>;
1155                                                 remote-endpoint = <&fe0_out_be1>;
1156                                         };
1157
1158                                         be1_in_fe1: endpoint@1 {
1159                                                 reg = <1>;
1160                                                 remote-endpoint = <&fe1_out_be1>;
1161                                         };
1162                                 };
1163
1164                                 be1_out: port@1 {
1165                                         #address-cells = <1>;
1166                                         #size-cells = <0>;
1167                                         reg = <1>;
1168
1169                                         be1_out_drc1: endpoint@1 {
1170                                                 reg = <1>;
1171                                                 remote-endpoint = <&drc1_in_be1>;
1172                                         };
1173                                 };
1174                         };
1175                 };
1176
1177                 drc1: drc@1e50000 {
1178                         compatible = "allwinner,sun6i-a31-drc";
1179                         reg = <0x01e50000 0x10000>;
1180                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1181                         clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1182                                  <&ccu CLK_DRAM_DRC1>;
1183                         clock-names = "ahb", "mod",
1184                                       "ram";
1185                         resets = <&ccu RST_AHB1_DRC1>;
1186
1187                         ports {
1188                                 #address-cells = <1>;
1189                                 #size-cells = <0>;
1190
1191                                 drc1_in: port@0 {
1192                                         #address-cells = <1>;
1193                                         #size-cells = <0>;
1194                                         reg = <0>;
1195
1196                                         drc1_in_be1: endpoint@1 {
1197                                                 reg = <1>;
1198                                                 remote-endpoint = <&be1_out_drc1>;
1199                                         };
1200                                 };
1201
1202                                 drc1_out: port@1 {
1203                                         #address-cells = <1>;
1204                                         #size-cells = <0>;
1205                                         reg = <1>;
1206
1207                                         drc1_out_tcon0: endpoint@0 {
1208                                                 reg = <0>;
1209                                                 remote-endpoint = <&tcon0_in_drc1>;
1210                                         };
1211
1212                                         drc1_out_tcon1: endpoint@1 {
1213                                                 reg = <1>;
1214                                                 remote-endpoint = <&tcon1_in_drc1>;
1215                                         };
1216                                 };
1217                         };
1218                 };
1219
1220                 be0: display-backend@1e60000 {
1221                         compatible = "allwinner,sun6i-a31-display-backend";
1222                         reg = <0x01e60000 0x10000>;
1223                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1224                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1225                                  <&ccu CLK_DRAM_BE0>;
1226                         clock-names = "ahb", "mod",
1227                                       "ram";
1228                         resets = <&ccu RST_AHB1_BE0>;
1229
1230                         ports {
1231                                 #address-cells = <1>;
1232                                 #size-cells = <0>;
1233
1234                                 be0_in: port@0 {
1235                                         #address-cells = <1>;
1236                                         #size-cells = <0>;
1237                                         reg = <0>;
1238
1239                                         be0_in_fe0: endpoint@0 {
1240                                                 reg = <0>;
1241                                                 remote-endpoint = <&fe0_out_be0>;
1242                                         };
1243
1244                                         be0_in_fe1: endpoint@1 {
1245                                                 reg = <1>;
1246                                                 remote-endpoint = <&fe1_out_be0>;
1247                                         };
1248                                 };
1249
1250                                 be0_out: port@1 {
1251                                         reg = <1>;
1252
1253                                         be0_out_drc0: endpoint {
1254                                                 remote-endpoint = <&drc0_in_be0>;
1255                                         };
1256                                 };
1257                         };
1258                 };
1259
1260                 drc0: drc@1e70000 {
1261                         compatible = "allwinner,sun6i-a31-drc";
1262                         reg = <0x01e70000 0x10000>;
1263                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1264                         clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1265                                  <&ccu CLK_DRAM_DRC0>;
1266                         clock-names = "ahb", "mod",
1267                                       "ram";
1268                         resets = <&ccu RST_AHB1_DRC0>;
1269
1270                         ports {
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273
1274                                 drc0_in: port@0 {
1275                                         reg = <0>;
1276
1277                                         drc0_in_be0: endpoint {
1278                                                 remote-endpoint = <&be0_out_drc0>;
1279                                         };
1280                                 };
1281
1282                                 drc0_out: port@1 {
1283                                         #address-cells = <1>;
1284                                         #size-cells = <0>;
1285                                         reg = <1>;
1286
1287                                         drc0_out_tcon0: endpoint@0 {
1288                                                 reg = <0>;
1289                                                 remote-endpoint = <&tcon0_in_drc0>;
1290                                         };
1291
1292                                         drc0_out_tcon1: endpoint@1 {
1293                                                 reg = <1>;
1294                                                 remote-endpoint = <&tcon1_in_drc0>;
1295                                         };
1296                                 };
1297                         };
1298                 };
1299
1300                 rtc: rtc@1f00000 {
1301                         #clock-cells = <1>;
1302                         compatible = "allwinner,sun6i-a31-rtc";
1303                         reg = <0x01f00000 0x54>;
1304                         interrupt-parent = <&r_intc>;
1305                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1306                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1307                         clocks = <&osc32k>;
1308                         clock-output-names = "osc32k";
1309                 };
1310
1311                 r_intc: interrupt-controller@1f00c00 {
1312                         compatible = "allwinner,sun6i-a31-r-intc";
1313                         interrupt-controller;
1314                         #interrupt-cells = <3>;
1315                         reg = <0x01f00c00 0x400>;
1316                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1317                 };
1318
1319                 prcm@1f01400 {
1320                         compatible = "allwinner,sun6i-a31-prcm";
1321                         reg = <0x01f01400 0x200>;
1322
1323                         ar100: ar100_clk {
1324                                 compatible = "allwinner,sun6i-a31-ar100-clk";
1325                                 #clock-cells = <0>;
1326                                 clocks = <&rtc 0>, <&osc24M>,
1327                                          <&ccu CLK_PLL_PERIPH>,
1328                                          <&ccu CLK_PLL_PERIPH>;
1329                                 clock-output-names = "ar100";
1330                         };
1331
1332                         ahb0: ahb0_clk {
1333                                 compatible = "fixed-factor-clock";
1334                                 #clock-cells = <0>;
1335                                 clock-div = <1>;
1336                                 clock-mult = <1>;
1337                                 clocks = <&ar100>;
1338                                 clock-output-names = "ahb0";
1339                         };
1340
1341                         apb0: apb0_clk {
1342                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1343                                 #clock-cells = <0>;
1344                                 clocks = <&ahb0>;
1345                                 clock-output-names = "apb0";
1346                         };
1347
1348                         apb0_gates: apb0_gates_clk {
1349                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1350                                 #clock-cells = <1>;
1351                                 clocks = <&apb0>;
1352                                 clock-output-names = "apb0_pio", "apb0_ir",
1353                                                 "apb0_timer", "apb0_p2wi",
1354                                                 "apb0_uart", "apb0_1wire",
1355                                                 "apb0_i2c";
1356                         };
1357
1358                         ir_clk: ir_clk {
1359                                 #clock-cells = <0>;
1360                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1361                                 clocks = <&rtc 0>, <&osc24M>;
1362                                 clock-output-names = "ir";
1363                         };
1364
1365                         apb0_rst: apb0_rst {
1366                                 compatible = "allwinner,sun6i-a31-clock-reset";
1367                                 #reset-cells = <1>;
1368                         };
1369                 };
1370
1371                 cpucfg@1f01c00 {
1372                         compatible = "allwinner,sun6i-a31-cpuconfig";
1373                         reg = <0x01f01c00 0x300>;
1374                 };
1375
1376                 ir: ir@1f02000 {
1377                         compatible = "allwinner,sun6i-a31-ir";
1378                         clocks = <&apb0_gates 1>, <&ir_clk>;
1379                         clock-names = "apb", "ir";
1380                         resets = <&apb0_rst 1>;
1381                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1382                         reg = <0x01f02000 0x40>;
1383                         status = "disabled";
1384                 };
1385
1386                 r_pio: pinctrl@1f02c00 {
1387                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1388                         reg = <0x01f02c00 0x400>;
1389                         interrupt-parent = <&r_intc>;
1390                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1391                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1392                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
1393                         clock-names = "apb", "hosc", "losc";
1394                         resets = <&apb0_rst 0>;
1395                         gpio-controller;
1396                         interrupt-controller;
1397                         #interrupt-cells = <3>;
1398                         #gpio-cells = <3>;
1399
1400                         s_ir_rx_pin: s-ir-rx-pin {
1401                                 pins = "PL4";
1402                                 function = "s_ir";
1403                         };
1404
1405                         s_p2wi_pins: s-p2wi-pins {
1406                                 pins = "PL0", "PL1";
1407                                 function = "s_p2wi";
1408                         };
1409                 };
1410
1411                 p2wi: i2c@1f03400 {
1412                         compatible = "allwinner,sun6i-a31-p2wi";
1413                         reg = <0x01f03400 0x400>;
1414                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415                         clocks = <&apb0_gates 3>;
1416                         clock-frequency = <100000>;
1417                         resets = <&apb0_rst 3>;
1418                         pinctrl-names = "default";
1419                         pinctrl-0 = <&s_p2wi_pins>;
1420                         status = "disabled";
1421                         #address-cells = <1>;
1422                         #size-cells = <0>;
1423                 };
1424         };
1425 };