arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 /include/ "skeleton.dtsi"
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 serial0 = &uart0;
  57                 serial1 = &uart1;
  58                 serial2 = &uart2;
  59                 serial3 = &uart3;
  60                 serial4 = &uart4;
  61                 serial5 = &uart5;
  62                 ethernet0 = &gmac;
  63         };
  64
  65         chosen {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 ranges;
  69
  70                 framebuffer@0 {
  71                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  72                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  73                         clocks = <&pll6 0>;
  74                         status = "disabled";
  75                 };
  76         };
  77
  78         cpus {
  79                 enable-method = "allwinner,sun6i-a31";
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu@0 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0>;
  87                 };
  88
  89                 cpu@1 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <1>;
  93                 };
  94
  95                 cpu@2 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <2>;
  99                 };
 100
 101                 cpu@3 {
 102                         compatible = "arm,cortex-a7";
 103                         device_type = "cpu";
 104                         reg = <3>;
 105                 };
 106         };
 107
 108         memory {
 109                 reg = <0x40000000 0x80000000>;
 110         };
 111
 112         pmu {
 113                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 114                 interrupts = <0 120 4>,
 115                              <0 121 4>,
 116                              <0 122 4>,
 117                              <0 123 4>;
 118         };
 119
 120         clocks {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges;
 124
 125                 osc24M: osc24M {
 126                         #clock-cells = <0>;
 127                         compatible = "fixed-clock";
 128                         clock-frequency = <24000000>;
 129                 };
 130
 131                 osc32k: clk@0 {
 132                         #clock-cells = <0>;
 133                         compatible = "fixed-clock";
 134                         clock-frequency = <32768>;
 135                         clock-output-names = "osc32k";
 136                 };
 137
 138                 pll1: clk@01c20000 {
 139                         #clock-cells = <0>;
 140                         compatible = "allwinner,sun6i-a31-pll1-clk";
 141                         reg = <0x01c20000 0x4>;
 142                         clocks = <&osc24M>;
 143                         clock-output-names = "pll1";
 144                 };
 145
 146                 pll6: clk@01c20028 {
 147                         #clock-cells = <1>;
 148                         compatible = "allwinner,sun6i-a31-pll6-clk";
 149                         reg = <0x01c20028 0x4>;
 150                         clocks = <&osc24M>;
 151                         clock-output-names = "pll6", "pll6x2";
 152                 };
 153
 154                 cpu: cpu@01c20050 {
 155                         #clock-cells = <0>;
 156                         compatible = "allwinner,sun4i-a10-cpu-clk";
 157                         reg = <0x01c20050 0x4>;
 158
 159                         /*
 160                          * PLL1 is listed twice here.
 161                          * While it looks suspicious, it's actually documented
 162                          * that way both in the datasheet and in the code from
 163                          * Allwinner.
 164                          */
 165                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 166                         clock-output-names = "cpu";
 167                 };
 168
 169                 axi: axi@01c20050 {
 170                         #clock-cells = <0>;
 171                         compatible = "allwinner,sun4i-a10-axi-clk";
 172                         reg = <0x01c20050 0x4>;
 173                         clocks = <&cpu>;
 174                         clock-output-names = "axi";
 175                 };
 176
 177                 ahb1: ahb1@01c20054 {
 178                         #clock-cells = <0>;
 179                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 180                         reg = <0x01c20054 0x4>;
 181                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 182                         clock-output-names = "ahb1";
 183                 };
 184
 185                 ahb1_gates: clk@01c20060 {
 186                         #clock-cells = <1>;
 187                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 188                         reg = <0x01c20060 0x8>;
 189                         clocks = <&ahb1>;
 190                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 191                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 192                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 193                                         "ahb1_nand0", "ahb1_sdram",
 194                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 195                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 196                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 197                                         "ahb1_ehci1", "ahb1_ohci0",
 198                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 199                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 200                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 201                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 202                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 203                                         "ahb1_drc0", "ahb1_drc1";
 204                 };
 205
 206                 apb1: apb1@01c20054 {
 207                         #clock-cells = <0>;
 208                         compatible = "allwinner,sun4i-a10-apb0-clk";
 209                         reg = <0x01c20054 0x4>;
 210                         clocks = <&ahb1>;
 211                         clock-output-names = "apb1";
 212                 };
 213
 214                 apb1_gates: clk@01c20068 {
 215                         #clock-cells = <1>;
 216                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 217                         reg = <0x01c20068 0x4>;
 218                         clocks = <&apb1>;
 219                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 220                                         "apb1_pio", "apb1_daudio0",
 221                                         "apb1_daudio1";
 222                 };
 223
 224                 apb2: clk@01c20058 {
 225                         #clock-cells = <0>;
 226                         compatible = "allwinner,sun4i-a10-apb1-clk";
 227                         reg = <0x01c20058 0x4>;
 228                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 229                         clock-output-names = "apb2";
 230                 };
 231
 232                 apb2_gates: clk@01c2006c {
 233                         #clock-cells = <1>;
 234                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 235                         reg = <0x01c2006c 0x4>;
 236                         clocks = <&apb2>;
 237                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 238                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 239                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 240                                         "apb2_uart4", "apb2_uart5";
 241                 };
 242
 243                 mmc0_clk: clk@01c20088 {
 244                         #clock-cells = <1>;
 245                         compatible = "allwinner,sun4i-a10-mmc-clk";
 246                         reg = <0x01c20088 0x4>;
 247                         clocks = <&osc24M>, <&pll6 0>;
 248                         clock-output-names = "mmc0",
 249                                              "mmc0_output",
 250                                              "mmc0_sample";
 251                 };
 252
 253                 mmc1_clk: clk@01c2008c {
 254                         #clock-cells = <1>;
 255                         compatible = "allwinner,sun4i-a10-mmc-clk";
 256                         reg = <0x01c2008c 0x4>;
 257                         clocks = <&osc24M>, <&pll6 0>;
 258                         clock-output-names = "mmc1",
 259                                              "mmc1_output",
 260                                              "mmc1_sample";
 261                 };
 262
 263                 mmc2_clk: clk@01c20090 {
 264                         #clock-cells = <1>;
 265                         compatible = "allwinner,sun4i-a10-mmc-clk";
 266                         reg = <0x01c20090 0x4>;
 267                         clocks = <&osc24M>, <&pll6 0>;
 268                         clock-output-names = "mmc2",
 269                                              "mmc2_output",
 270                                              "mmc2_sample";
 271                 };
 272
 273                 mmc3_clk: clk@01c20094 {
 274                         #clock-cells = <1>;
 275                         compatible = "allwinner,sun4i-a10-mmc-clk";
 276                         reg = <0x01c20094 0x4>;
 277                         clocks = <&osc24M>, <&pll6 0>;
 278                         clock-output-names = "mmc3",
 279                                              "mmc3_output",
 280                                              "mmc3_sample";
 281                 };
 282
 283                 spi0_clk: clk@01c200a0 {
 284                         #clock-cells = <0>;
 285                         compatible = "allwinner,sun4i-a10-mod0-clk";
 286                         reg = <0x01c200a0 0x4>;
 287                         clocks = <&osc24M>, <&pll6 0>;
 288                         clock-output-names = "spi0";
 289                 };
 290
 291                 spi1_clk: clk@01c200a4 {
 292                         #clock-cells = <0>;
 293                         compatible = "allwinner,sun4i-a10-mod0-clk";
 294                         reg = <0x01c200a4 0x4>;
 295                         clocks = <&osc24M>, <&pll6 0>;
 296                         clock-output-names = "spi1";
 297                 };
 298
 299                 spi2_clk: clk@01c200a8 {
 300                         #clock-cells = <0>;
 301                         compatible = "allwinner,sun4i-a10-mod0-clk";
 302                         reg = <0x01c200a8 0x4>;
 303                         clocks = <&osc24M>, <&pll6 0>;
 304                         clock-output-names = "spi2";
 305                 };
 306
 307                 spi3_clk: clk@01c200ac {
 308                         #clock-cells = <0>;
 309                         compatible = "allwinner,sun4i-a10-mod0-clk";
 310                         reg = <0x01c200ac 0x4>;
 311                         clocks = <&osc24M>, <&pll6 0>;
 312                         clock-output-names = "spi3";
 313                 };
 314
 315                 usb_clk: clk@01c200cc {
 316                         #clock-cells = <1>;
 317                         #reset-cells = <1>;
 318                         compatible = "allwinner,sun6i-a31-usb-clk";
 319                         reg = <0x01c200cc 0x4>;
 320                         clocks = <&osc24M>;
 321                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 322                                              "usb_ohci0", "usb_ohci1",
 323                                              "usb_ohci2";
 324                 };
 325
 326                 /*
 327                  * The following two are dummy clocks, placeholders used in the gmac_tx
 328                  * clock. The gmac driver will choose one parent depending on the PHY
 329                  * interface mode, using clk_set_rate auto-reparenting.
 330                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 331                  */
 332                 mii_phy_tx_clk: clk@1 {
 333                         #clock-cells = <0>;
 334                         compatible = "fixed-clock";
 335                         clock-frequency = <25000000>;
 336                         clock-output-names = "mii_phy_tx";
 337                 };
 338
 339                 gmac_int_tx_clk: clk@2 {
 340                         #clock-cells = <0>;
 341                         compatible = "fixed-clock";
 342                         clock-frequency = <125000000>;
 343                         clock-output-names = "gmac_int_tx";
 344                 };
 345
 346                 gmac_tx_clk: clk@01c200d0 {
 347                         #clock-cells = <0>;
 348                         compatible = "allwinner,sun7i-a20-gmac-clk";
 349                         reg = <0x01c200d0 0x4>;
 350                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 351                         clock-output-names = "gmac_tx";
 352                 };
 353         };
 354
 355         soc@01c00000 {
 356                 compatible = "simple-bus";
 357                 #address-cells = <1>;
 358                 #size-cells = <1>;
 359                 ranges;
 360
 361                 dma: dma-controller@01c02000 {
 362                         compatible = "allwinner,sun6i-a31-dma";
 363                         reg = <0x01c02000 0x1000>;
 364                         interrupts = <0 50 4>;
 365                         clocks = <&ahb1_gates 6>;
 366                         resets = <&ahb1_rst 6>;
 367                         #dma-cells = <1>;
 368
 369                         /* DMA controller requires AHB1 clocked from PLL6 */
 370                         assigned-clocks = <&ahb1>;
 371                         assigned-clock-parents = <&pll6 0>;
 372                 };
 373
 374                 mmc0: mmc@01c0f000 {
 375                         compatible = "allwinner,sun5i-a13-mmc";
 376                         reg = <0x01c0f000 0x1000>;
 377                         clocks = <&ahb1_gates 8>,
 378                                  <&mmc0_clk 0>,
 379                                  <&mmc0_clk 1>,
 380                                  <&mmc0_clk 2>;
 381                         clock-names = "ahb",
 382                                       "mmc",
 383                                       "output",
 384                                       "sample";
 385                         resets = <&ahb1_rst 8>;
 386                         reset-names = "ahb";
 387                         interrupts = <0 60 4>;
 388                         status = "disabled";
 389                 };
 390
 391                 mmc1: mmc@01c10000 {
 392                         compatible = "allwinner,sun5i-a13-mmc";
 393                         reg = <0x01c10000 0x1000>;
 394                         clocks = <&ahb1_gates 9>,
 395                                  <&mmc1_clk 0>,
 396                                  <&mmc1_clk 1>,
 397                                  <&mmc1_clk 2>;
 398                         clock-names = "ahb",
 399                                       "mmc",
 400                                       "output",
 401                                       "sample";
 402                         resets = <&ahb1_rst 9>;
 403                         reset-names = "ahb";
 404                         interrupts = <0 61 4>;
 405                         status = "disabled";
 406                 };
 407
 408                 mmc2: mmc@01c11000 {
 409                         compatible = "allwinner,sun5i-a13-mmc";
 410                         reg = <0x01c11000 0x1000>;
 411                         clocks = <&ahb1_gates 10>,
 412                                  <&mmc2_clk 0>,
 413                                  <&mmc2_clk 1>,
 414                                  <&mmc2_clk 2>;
 415                         clock-names = "ahb",
 416                                       "mmc",
 417                                       "output",
 418                                       "sample";
 419                         resets = <&ahb1_rst 10>;
 420                         reset-names = "ahb";
 421                         interrupts = <0 62 4>;
 422                         status = "disabled";
 423                 };
 424
 425                 mmc3: mmc@01c12000 {
 426                         compatible = "allwinner,sun5i-a13-mmc";
 427                         reg = <0x01c12000 0x1000>;
 428                         clocks = <&ahb1_gates 11>,
 429                                  <&mmc3_clk 0>,
 430                                  <&mmc3_clk 1>,
 431                                  <&mmc3_clk 2>;
 432                         clock-names = "ahb",
 433                                       "mmc",
 434                                       "output",
 435                                       "sample";
 436                         resets = <&ahb1_rst 11>;
 437                         reset-names = "ahb";
 438                         interrupts = <0 63 4>;
 439                         status = "disabled";
 440                 };
 441
 442                 usbphy: phy@01c19400 {
 443                         compatible = "allwinner,sun6i-a31-usb-phy";
 444                         reg = <0x01c19400 0x10>,
 445                               <0x01c1a800 0x4>,
 446                               <0x01c1b800 0x4>;
 447                         reg-names = "phy_ctrl",
 448                                     "pmu1",
 449                                     "pmu2";
 450                         clocks = <&usb_clk 8>,
 451                                  <&usb_clk 9>,
 452                                  <&usb_clk 10>;
 453                         clock-names = "usb0_phy",
 454                                       "usb1_phy",
 455                                       "usb2_phy";
 456                         resets = <&usb_clk 0>,
 457                                  <&usb_clk 1>,
 458                                  <&usb_clk 2>;
 459                         reset-names = "usb0_reset",
 460                                       "usb1_reset",
 461                                       "usb2_reset";
 462                         status = "disabled";
 463                         #phy-cells = <1>;
 464                 };
 465
 466                 ehci0: usb@01c1a000 {
 467                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 468                         reg = <0x01c1a000 0x100>;
 469                         interrupts = <0 72 4>;
 470                         clocks = <&ahb1_gates 26>;
 471                         resets = <&ahb1_rst 26>;
 472                         phys = <&usbphy 1>;
 473                         phy-names = "usb";
 474                         status = "disabled";
 475                 };
 476
 477                 ohci0: usb@01c1a400 {
 478                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 479                         reg = <0x01c1a400 0x100>;
 480                         interrupts = <0 73 4>;
 481                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 482                         resets = <&ahb1_rst 29>;
 483                         phys = <&usbphy 1>;
 484                         phy-names = "usb";
 485                         status = "disabled";
 486                 };
 487
 488                 ehci1: usb@01c1b000 {
 489                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 490                         reg = <0x01c1b000 0x100>;
 491                         interrupts = <0 74 4>;
 492                         clocks = <&ahb1_gates 27>;
 493                         resets = <&ahb1_rst 27>;
 494                         phys = <&usbphy 2>;
 495                         phy-names = "usb";
 496                         status = "disabled";
 497                 };
 498
 499                 ohci1: usb@01c1b400 {
 500                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 501                         reg = <0x01c1b400 0x100>;
 502                         interrupts = <0 75 4>;
 503                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 504                         resets = <&ahb1_rst 30>;
 505                         phys = <&usbphy 2>;
 506                         phy-names = "usb";
 507                         status = "disabled";
 508                 };
 509
 510                 ohci2: usb@01c1c400 {
 511                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 512                         reg = <0x01c1c400 0x100>;
 513                         interrupts = <0 77 4>;
 514                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 515                         resets = <&ahb1_rst 31>;
 516                         status = "disabled";
 517                 };
 518
 519                 pio: pinctrl@01c20800 {
 520                         compatible = "allwinner,sun6i-a31-pinctrl";
 521                         reg = <0x01c20800 0x400>;
 522                         interrupts = <0 11 4>,
 523                                      <0 15 4>,
 524                                      <0 16 4>,
 525                                      <0 17 4>;
 526                         clocks = <&apb1_gates 5>;
 527                         gpio-controller;
 528                         interrupt-controller;
 529                         #interrupt-cells = <2>;
 530                         #size-cells = <0>;
 531                         #gpio-cells = <3>;
 532
 533                         uart0_pins_a: uart0@0 {
 534                                 allwinner,pins = "PH20", "PH21";
 535                                 allwinner,function = "uart0";
 536                                 allwinner,drive = <0>;
 537                                 allwinner,pull = <0>;
 538                         };
 539
 540                         i2c0_pins_a: i2c0@0 {
 541                                 allwinner,pins = "PH14", "PH15";
 542                                 allwinner,function = "i2c0";
 543                                 allwinner,drive = <0>;
 544                                 allwinner,pull = <0>;
 545                         };
 546
 547                         i2c1_pins_a: i2c1@0 {
 548                                 allwinner,pins = "PH16", "PH17";
 549                                 allwinner,function = "i2c1";
 550                                 allwinner,drive = <0>;
 551                                 allwinner,pull = <0>;
 552                         };
 553
 554                         i2c2_pins_a: i2c2@0 {
 555                                 allwinner,pins = "PH18", "PH19";
 556                                 allwinner,function = "i2c2";
 557                                 allwinner,drive = <0>;
 558                                 allwinner,pull = <0>;
 559                         };
 560
 561                         mmc0_pins_a: mmc0@0 {
 562                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 563                                 allwinner,function = "mmc0";
 564                                 allwinner,drive = <2>;
 565                                 allwinner,pull = <0>;
 566                         };
 567
 568                         gmac_pins_mii_a: gmac_mii@0 {
 569                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 570                                                 "PA8", "PA9", "PA11",
 571                                                 "PA12", "PA13", "PA14", "PA19",
 572                                                 "PA20", "PA21", "PA22", "PA23",
 573                                                 "PA24", "PA26", "PA27";
 574                                 allwinner,function = "gmac";
 575                                 allwinner,drive = <0>;
 576                                 allwinner,pull = <0>;
 577                         };
 578
 579                         gmac_pins_gmii_a: gmac_gmii@0 {
 580                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 581                                                 "PA4", "PA5", "PA6", "PA7",
 582                                                 "PA8", "PA9", "PA10", "PA11",
 583                                                 "PA12", "PA13", "PA14", "PA15",
 584                                                 "PA16", "PA17", "PA18", "PA19",
 585                                                 "PA20", "PA21", "PA22", "PA23",
 586                                                 "PA24", "PA25", "PA26", "PA27";
 587                                 allwinner,function = "gmac";
 588                                 /*
 589                                  * data lines in GMII mode run at 125MHz and
 590                                  * might need a higher signal drive strength
 591                                  */
 592                                 allwinner,drive = <2>;
 593                                 allwinner,pull = <0>;
 594                         };
 595
 596                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 597                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 598                                                 "PA9", "PA10", "PA11",
 599                                                 "PA12", "PA13", "PA14", "PA19",
 600                                                 "PA20", "PA25", "PA26", "PA27";
 601                                 allwinner,function = "gmac";
 602                                 /*
 603                                  * data lines in RGMII mode use DDR mode
 604                                  * and need a higher signal drive strength
 605                                  */
 606                                 allwinner,drive = <3>;
 607                                 allwinner,pull = <0>;
 608                         };
 609                 };
 610
 611                 ahb1_rst: reset@01c202c0 {
 612                         #reset-cells = <1>;
 613                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 614                         reg = <0x01c202c0 0xc>;
 615                 };
 616
 617                 apb1_rst: reset@01c202d0 {
 618                         #reset-cells = <1>;
 619                         compatible = "allwinner,sun6i-a31-clock-reset";
 620                         reg = <0x01c202d0 0x4>;
 621                 };
 622
 623                 apb2_rst: reset@01c202d8 {
 624                         #reset-cells = <1>;
 625                         compatible = "allwinner,sun6i-a31-clock-reset";
 626                         reg = <0x01c202d8 0x4>;
 627                 };
 628
 629                 timer@01c20c00 {
 630                         compatible = "allwinner,sun4i-a10-timer";
 631                         reg = <0x01c20c00 0xa0>;
 632                         interrupts = <0 18 4>,
 633                                      <0 19 4>,
 634                                      <0 20 4>,
 635                                      <0 21 4>,
 636                                      <0 22 4>;
 637                         clocks = <&osc24M>;
 638                 };
 639
 640                 wdt1: watchdog@01c20ca0 {
 641                         compatible = "allwinner,sun6i-a31-wdt";
 642                         reg = <0x01c20ca0 0x20>;
 643                 };
 644
 645                 uart0: serial@01c28000 {
 646                         compatible = "snps,dw-apb-uart";
 647                         reg = <0x01c28000 0x400>;
 648                         interrupts = <0 0 4>;
 649                         reg-shift = <2>;
 650                         reg-io-width = <4>;
 651                         clocks = <&apb2_gates 16>;
 652                         resets = <&apb2_rst 16>;
 653                         dmas = <&dma 6>, <&dma 6>;
 654                         dma-names = "rx", "tx";
 655                         status = "disabled";
 656                 };
 657
 658                 uart1: serial@01c28400 {
 659                         compatible = "snps,dw-apb-uart";
 660                         reg = <0x01c28400 0x400>;
 661                         interrupts = <0 1 4>;
 662                         reg-shift = <2>;
 663                         reg-io-width = <4>;
 664                         clocks = <&apb2_gates 17>;
 665                         resets = <&apb2_rst 17>;
 666                         dmas = <&dma 7>, <&dma 7>;
 667                         dma-names = "rx", "tx";
 668                         status = "disabled";
 669                 };
 670
 671                 uart2: serial@01c28800 {
 672                         compatible = "snps,dw-apb-uart";
 673                         reg = <0x01c28800 0x400>;
 674                         interrupts = <0 2 4>;
 675                         reg-shift = <2>;
 676                         reg-io-width = <4>;
 677                         clocks = <&apb2_gates 18>;
 678                         resets = <&apb2_rst 18>;
 679                         dmas = <&dma 8>, <&dma 8>;
 680                         dma-names = "rx", "tx";
 681                         status = "disabled";
 682                 };
 683
 684                 uart3: serial@01c28c00 {
 685                         compatible = "snps,dw-apb-uart";
 686                         reg = <0x01c28c00 0x400>;
 687                         interrupts = <0 3 4>;
 688                         reg-shift = <2>;
 689                         reg-io-width = <4>;
 690                         clocks = <&apb2_gates 19>;
 691                         resets = <&apb2_rst 19>;
 692                         dmas = <&dma 9>, <&dma 9>;
 693                         dma-names = "rx", "tx";
 694                         status = "disabled";
 695                 };
 696
 697                 uart4: serial@01c29000 {
 698                         compatible = "snps,dw-apb-uart";
 699                         reg = <0x01c29000 0x400>;
 700                         interrupts = <0 4 4>;
 701                         reg-shift = <2>;
 702                         reg-io-width = <4>;
 703                         clocks = <&apb2_gates 20>;
 704                         resets = <&apb2_rst 20>;
 705                         dmas = <&dma 10>, <&dma 10>;
 706                         dma-names = "rx", "tx";
 707                         status = "disabled";
 708                 };
 709
 710                 uart5: serial@01c29400 {
 711                         compatible = "snps,dw-apb-uart";
 712                         reg = <0x01c29400 0x400>;
 713                         interrupts = <0 5 4>;
 714                         reg-shift = <2>;
 715                         reg-io-width = <4>;
 716                         clocks = <&apb2_gates 21>;
 717                         resets = <&apb2_rst 21>;
 718                         dmas = <&dma 22>, <&dma 22>;
 719                         dma-names = "rx", "tx";
 720                         status = "disabled";
 721                 };
 722
 723                 i2c0: i2c@01c2ac00 {
 724                         compatible = "allwinner,sun6i-a31-i2c";
 725                         reg = <0x01c2ac00 0x400>;
 726                         interrupts = <0 6 4>;
 727                         clocks = <&apb2_gates 0>;
 728                         resets = <&apb2_rst 0>;
 729                         status = "disabled";
 730                         #address-cells = <1>;
 731                         #size-cells = <0>;
 732                 };
 733
 734                 i2c1: i2c@01c2b000 {
 735                         compatible = "allwinner,sun6i-a31-i2c";
 736                         reg = <0x01c2b000 0x400>;
 737                         interrupts = <0 7 4>;
 738                         clocks = <&apb2_gates 1>;
 739                         resets = <&apb2_rst 1>;
 740                         status = "disabled";
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743                 };
 744
 745                 i2c2: i2c@01c2b400 {
 746                         compatible = "allwinner,sun6i-a31-i2c";
 747                         reg = <0x01c2b400 0x400>;
 748                         interrupts = <0 8 4>;
 749                         clocks = <&apb2_gates 2>;
 750                         resets = <&apb2_rst 2>;
 751                         status = "disabled";
 752                         #address-cells = <1>;
 753                         #size-cells = <0>;
 754                 };
 755
 756                 i2c3: i2c@01c2b800 {
 757                         compatible = "allwinner,sun6i-a31-i2c";
 758                         reg = <0x01c2b800 0x400>;
 759                         interrupts = <0 9 4>;
 760                         clocks = <&apb2_gates 3>;
 761                         resets = <&apb2_rst 3>;
 762                         status = "disabled";
 763                         #address-cells = <1>;
 764                         #size-cells = <0>;
 765                 };
 766
 767                 gmac: ethernet@01c30000 {
 768                         compatible = "allwinner,sun7i-a20-gmac";
 769                         reg = <0x01c30000 0x1054>;
 770                         interrupts = <0 82 4>;
 771                         interrupt-names = "macirq";
 772                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 773                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 774                         resets = <&ahb1_rst 17>;
 775                         reset-names = "stmmaceth";
 776                         snps,pbl = <2>;
 777                         snps,fixed-burst;
 778                         snps,force_sf_dma_mode;
 779                         status = "disabled";
 780                         #address-cells = <1>;
 781                         #size-cells = <0>;
 782                 };
 783
 784                 timer@01c60000 {
 785                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 786                         reg = <0x01c60000 0x1000>;
 787                         interrupts = <0 51 4>,
 788                                      <0 52 4>,
 789                                      <0 53 4>,
 790                                      <0 54 4>;
 791                         clocks = <&ahb1_gates 19>;
 792                         resets = <&ahb1_rst 19>;
 793                 };
 794
 795                 spi0: spi@01c68000 {
 796                         compatible = "allwinner,sun6i-a31-spi";
 797                         reg = <0x01c68000 0x1000>;
 798                         interrupts = <0 65 4>;
 799                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 800                         clock-names = "ahb", "mod";
 801                         dmas = <&dma 23>, <&dma 23>;
 802                         dma-names = "rx", "tx";
 803                         resets = <&ahb1_rst 20>;
 804                         status = "disabled";
 805                 };
 806
 807                 spi1: spi@01c69000 {
 808                         compatible = "allwinner,sun6i-a31-spi";
 809                         reg = <0x01c69000 0x1000>;
 810                         interrupts = <0 66 4>;
 811                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 812                         clock-names = "ahb", "mod";
 813                         dmas = <&dma 24>, <&dma 24>;
 814                         dma-names = "rx", "tx";
 815                         resets = <&ahb1_rst 21>;
 816                         status = "disabled";
 817                 };
 818
 819                 spi2: spi@01c6a000 {
 820                         compatible = "allwinner,sun6i-a31-spi";
 821                         reg = <0x01c6a000 0x1000>;
 822                         interrupts = <0 67 4>;
 823                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 824                         clock-names = "ahb", "mod";
 825                         dmas = <&dma 25>, <&dma 25>;
 826                         dma-names = "rx", "tx";
 827                         resets = <&ahb1_rst 22>;
 828                         status = "disabled";
 829                 };
 830
 831                 spi3: spi@01c6b000 {
 832                         compatible = "allwinner,sun6i-a31-spi";
 833                         reg = <0x01c6b000 0x1000>;
 834                         interrupts = <0 68 4>;
 835                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 836                         clock-names = "ahb", "mod";
 837                         dmas = <&dma 26>, <&dma 26>;
 838                         dma-names = "rx", "tx";
 839                         resets = <&ahb1_rst 23>;
 840                         status = "disabled";
 841                 };
 842
 843                 gic: interrupt-controller@01c81000 {
 844                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 845                         reg = <0x01c81000 0x1000>,
 846                               <0x01c82000 0x1000>,
 847                               <0x01c84000 0x2000>,
 848                               <0x01c86000 0x2000>;
 849                         interrupt-controller;
 850                         #interrupt-cells = <3>;
 851                         interrupts = <1 9 0xf04>;
 852                 };
 853
 854                 rtc: rtc@01f00000 {
 855                         compatible = "allwinner,sun6i-a31-rtc";
 856                         reg = <0x01f00000 0x54>;
 857                         interrupts = <0 40 4>, <0 41 4>;
 858                 };
 859
 860                 nmi_intc: interrupt-controller@01f00c0c {
 861                         compatible = "allwinner,sun6i-a31-sc-nmi";
 862                         interrupt-controller;
 863                         #interrupt-cells = <2>;
 864                         reg = <0x01f00c0c 0x38>;
 865                         interrupts = <0 32 4>;
 866                 };
 867
 868                 prcm@01f01400 {
 869                         compatible = "allwinner,sun6i-a31-prcm";
 870                         reg = <0x01f01400 0x200>;
 871
 872                         ar100: ar100_clk {
 873                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 874                                 #clock-cells = <0>;
 875                                 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 876                                 clock-output-names = "ar100";
 877                         };
 878
 879                         ahb0: ahb0_clk {
 880                                 compatible = "fixed-factor-clock";
 881                                 #clock-cells = <0>;
 882                                 clock-div = <1>;
 883                                 clock-mult = <1>;
 884                                 clocks = <&ar100>;
 885                                 clock-output-names = "ahb0";
 886                         };
 887
 888                         apb0: apb0_clk {
 889                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 890                                 #clock-cells = <0>;
 891                                 clocks = <&ahb0>;
 892                                 clock-output-names = "apb0";
 893                         };
 894
 895                         apb0_gates: apb0_gates_clk {
 896                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 897                                 #clock-cells = <1>;
 898                                 clocks = <&apb0>;
 899                                 clock-output-names = "apb0_pio", "apb0_ir",
 900                                                 "apb0_timer", "apb0_p2wi",
 901                                                 "apb0_uart", "apb0_1wire",
 902                                                 "apb0_i2c";
 903                         };
 904
 905                         apb0_rst: apb0_rst {
 906                                 compatible = "allwinner,sun6i-a31-clock-reset";
 907                                 #reset-cells = <1>;
 908                         };
 909                 };
 910
 911                 cpucfg@01f01c00 {
 912                         compatible = "allwinner,sun6i-a31-cpuconfig";
 913                         reg = <0x01f01c00 0x300>;
 914                 };
 915
 916                 r_pio: pinctrl@01f02c00 {
 917                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 918                         reg = <0x01f02c00 0x400>;
 919                         interrupts = <0 45 4>,
 920                                      <0 46 4>;
 921                         clocks = <&apb0_gates 0>;
 922                         resets = <&apb0_rst 0>;
 923                         gpio-controller;
 924                         interrupt-controller;
 925                         #interrupt-cells = <2>;
 926                         #size-cells = <0>;
 927                         #gpio-cells = <3>;
 928                 };
 929         };
 930 };