2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "de_be0-lcd0";
82 compatible = "arm,armv7-timer";
83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
87 clock-frequency = <24000000>;
88 arm,cpu-registers-not-fw-configured;
92 enable-method = "allwinner,sun6i-a31";
97 compatible = "arm,cortex-a7";
101 clock-latency = <244144>; /* 8 32k periods */
109 #cooling-cells = <2>;
110 cooling-min-level = <0>;
111 cooling-max-level = <3>;
115 compatible = "arm,cortex-a7";
121 compatible = "arm,cortex-a7";
127 compatible = "arm,cortex-a7";
136 polling-delay-passive = <250>;
137 polling-delay = <1000>;
138 thermal-sensors = <&rtp>;
142 trip = <&cpu_alert0>;
143 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
148 cpu_alert0: cpu_alert0 {
150 temperature = <70000>;
157 temperature = <100000>;
166 reg = <0x40000000 0x80000000>;
170 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
171 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>;
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
190 compatible = "fixed-clock";
191 clock-frequency = <32768>;
192 clock-output-names = "osc32k";
197 compatible = "allwinner,sun6i-a31-pll1-clk";
198 reg = <0x01c20000 0x4>;
200 clock-output-names = "pll1";
205 compatible = "allwinner,sun6i-a31-pll6-clk";
206 reg = <0x01c20028 0x4>;
208 clock-output-names = "pll6", "pll6x2";
213 compatible = "allwinner,sun4i-a10-cpu-clk";
214 reg = <0x01c20050 0x4>;
217 * PLL1 is listed twice here.
218 * While it looks suspicious, it's actually documented
219 * that way both in the datasheet and in the code from
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
223 clock-output-names = "cpu";
228 compatible = "allwinner,sun4i-a10-axi-clk";
229 reg = <0x01c20050 0x4>;
231 clock-output-names = "axi";
234 ahb1: ahb1@01c20054 {
236 compatible = "allwinner,sun6i-a31-ahb1-clk";
237 reg = <0x01c20054 0x4>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
239 clock-output-names = "ahb1";
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
243 * has rate changes due to cpufreq. Also the DMA
244 * controller requires AHB1 clocked from PLL6.
246 assigned-clocks = <&ahb1>;
247 assigned-clock-parents = <&pll6 0>;
250 ahb1_gates: clk@01c20060 {
252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
253 reg = <0x01c20060 0x8>;
255 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
256 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
257 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
258 "ahb1_nand0", "ahb1_sdram",
259 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
260 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
261 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
262 "ahb1_ehci1", "ahb1_ohci0",
263 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
264 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
265 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
266 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
267 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
268 "ahb1_drc0", "ahb1_drc1";
271 apb1: apb1@01c20054 {
273 compatible = "allwinner,sun4i-a10-apb0-clk";
274 reg = <0x01c20054 0x4>;
276 clock-output-names = "apb1";
279 apb1_gates: clk@01c20068 {
281 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
282 reg = <0x01c20068 0x4>;
284 clock-output-names = "apb1_codec", "apb1_digital_mic",
285 "apb1_pio", "apb1_daudio0",
291 compatible = "allwinner,sun4i-a10-apb1-clk";
292 reg = <0x01c20058 0x4>;
293 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
294 clock-output-names = "apb2";
297 apb2_gates: clk@01c2006c {
299 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
300 reg = <0x01c2006c 0x4>;
302 clock-output-names = "apb2_i2c0", "apb2_i2c1",
303 "apb2_i2c2", "apb2_i2c3",
304 "apb2_uart0", "apb2_uart1",
305 "apb2_uart2", "apb2_uart3",
306 "apb2_uart4", "apb2_uart5";
309 mmc0_clk: clk@01c20088 {
311 compatible = "allwinner,sun4i-a10-mmc-clk";
312 reg = <0x01c20088 0x4>;
313 clocks = <&osc24M>, <&pll6 0>;
314 clock-output-names = "mmc0",
319 mmc1_clk: clk@01c2008c {
321 compatible = "allwinner,sun4i-a10-mmc-clk";
322 reg = <0x01c2008c 0x4>;
323 clocks = <&osc24M>, <&pll6 0>;
324 clock-output-names = "mmc1",
329 mmc2_clk: clk@01c20090 {
331 compatible = "allwinner,sun4i-a10-mmc-clk";
332 reg = <0x01c20090 0x4>;
333 clocks = <&osc24M>, <&pll6 0>;
334 clock-output-names = "mmc2",
339 mmc3_clk: clk@01c20094 {
341 compatible = "allwinner,sun4i-a10-mmc-clk";
342 reg = <0x01c20094 0x4>;
343 clocks = <&osc24M>, <&pll6 0>;
344 clock-output-names = "mmc3",
349 ss_clk: clk@01c2009c {
351 compatible = "allwinner,sun4i-a10-mod0-clk";
352 reg = <0x01c2009c 0x4>;
353 clocks = <&osc24M>, <&pll6 0>;
354 clock-output-names = "ss";
357 spi0_clk: clk@01c200a0 {
359 compatible = "allwinner,sun4i-a10-mod0-clk";
360 reg = <0x01c200a0 0x4>;
361 clocks = <&osc24M>, <&pll6 0>;
362 clock-output-names = "spi0";
365 spi1_clk: clk@01c200a4 {
367 compatible = "allwinner,sun4i-a10-mod0-clk";
368 reg = <0x01c200a4 0x4>;
369 clocks = <&osc24M>, <&pll6 0>;
370 clock-output-names = "spi1";
373 spi2_clk: clk@01c200a8 {
375 compatible = "allwinner,sun4i-a10-mod0-clk";
376 reg = <0x01c200a8 0x4>;
377 clocks = <&osc24M>, <&pll6 0>;
378 clock-output-names = "spi2";
381 spi3_clk: clk@01c200ac {
383 compatible = "allwinner,sun4i-a10-mod0-clk";
384 reg = <0x01c200ac 0x4>;
385 clocks = <&osc24M>, <&pll6 0>;
386 clock-output-names = "spi3";
389 usb_clk: clk@01c200cc {
392 compatible = "allwinner,sun6i-a31-usb-clk";
393 reg = <0x01c200cc 0x4>;
395 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
396 "usb_ohci0", "usb_ohci1",
401 * The following two are dummy clocks, placeholders
402 * used in the gmac_tx clock. The gmac driver will
403 * choose one parent depending on the PHY interface
404 * mode, using clk_set_rate auto-reparenting.
406 * The actual TX clock rate is not controlled by the
409 mii_phy_tx_clk: clk@1 {
411 compatible = "fixed-clock";
412 clock-frequency = <25000000>;
413 clock-output-names = "mii_phy_tx";
416 gmac_int_tx_clk: clk@2 {
418 compatible = "fixed-clock";
419 clock-frequency = <125000000>;
420 clock-output-names = "gmac_int_tx";
423 gmac_tx_clk: clk@01c200d0 {
425 compatible = "allwinner,sun7i-a20-gmac-clk";
426 reg = <0x01c200d0 0x4>;
427 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
428 clock-output-names = "gmac_tx";
433 compatible = "simple-bus";
434 #address-cells = <1>;
438 dma: dma-controller@01c02000 {
439 compatible = "allwinner,sun6i-a31-dma";
440 reg = <0x01c02000 0x1000>;
441 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&ahb1_gates 6>;
443 resets = <&ahb1_rst 6>;
448 compatible = "allwinner,sun5i-a13-mmc";
449 reg = <0x01c0f000 0x1000>;
450 clocks = <&ahb1_gates 8>,
458 resets = <&ahb1_rst 8>;
460 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
467 compatible = "allwinner,sun5i-a13-mmc";
468 reg = <0x01c10000 0x1000>;
469 clocks = <&ahb1_gates 9>,
477 resets = <&ahb1_rst 9>;
479 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
481 #address-cells = <1>;
486 compatible = "allwinner,sun5i-a13-mmc";
487 reg = <0x01c11000 0x1000>;
488 clocks = <&ahb1_gates 10>,
496 resets = <&ahb1_rst 10>;
498 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
505 compatible = "allwinner,sun5i-a13-mmc";
506 reg = <0x01c12000 0x1000>;
507 clocks = <&ahb1_gates 11>,
515 resets = <&ahb1_rst 11>;
517 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
519 #address-cells = <1>;
523 usbphy: phy@01c19400 {
524 compatible = "allwinner,sun6i-a31-usb-phy";
525 reg = <0x01c19400 0x10>,
528 reg-names = "phy_ctrl",
531 clocks = <&usb_clk 8>,
534 clock-names = "usb0_phy",
537 resets = <&usb_clk 0>,
540 reset-names = "usb0_reset",
547 ehci0: usb@01c1a000 {
548 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
549 reg = <0x01c1a000 0x100>;
550 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&ahb1_gates 26>;
552 resets = <&ahb1_rst 26>;
558 ohci0: usb@01c1a400 {
559 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
560 reg = <0x01c1a400 0x100>;
561 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
563 resets = <&ahb1_rst 29>;
569 ehci1: usb@01c1b000 {
570 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
571 reg = <0x01c1b000 0x100>;
572 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&ahb1_gates 27>;
574 resets = <&ahb1_rst 27>;
580 ohci1: usb@01c1b400 {
581 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
582 reg = <0x01c1b400 0x100>;
583 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
585 resets = <&ahb1_rst 30>;
591 ohci2: usb@01c1c400 {
592 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
593 reg = <0x01c1c400 0x100>;
594 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
596 resets = <&ahb1_rst 31>;
600 pio: pinctrl@01c20800 {
601 compatible = "allwinner,sun6i-a31-pinctrl";
602 reg = <0x01c20800 0x400>;
603 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&apb1_gates 5>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
614 uart0_pins_a: uart0@0 {
615 allwinner,pins = "PH20", "PH21";
616 allwinner,function = "uart0";
617 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
618 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
621 i2c0_pins_a: i2c0@0 {
622 allwinner,pins = "PH14", "PH15";
623 allwinner,function = "i2c0";
624 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
625 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
628 i2c1_pins_a: i2c1@0 {
629 allwinner,pins = "PH16", "PH17";
630 allwinner,function = "i2c1";
631 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
632 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
635 i2c2_pins_a: i2c2@0 {
636 allwinner,pins = "PH18", "PH19";
637 allwinner,function = "i2c2";
638 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
639 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
642 mmc0_pins_a: mmc0@0 {
643 allwinner,pins = "PF0", "PF1", "PF2",
645 allwinner,function = "mmc0";
646 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
647 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
650 mmc1_pins_a: mmc1@0 {
651 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
653 allwinner,function = "mmc1";
654 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
655 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
658 gmac_pins_mii_a: gmac_mii@0 {
659 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
660 "PA8", "PA9", "PA11",
661 "PA12", "PA13", "PA14", "PA19",
662 "PA20", "PA21", "PA22", "PA23",
663 "PA24", "PA26", "PA27";
664 allwinner,function = "gmac";
665 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
666 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
669 gmac_pins_gmii_a: gmac_gmii@0 {
670 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
671 "PA4", "PA5", "PA6", "PA7",
672 "PA8", "PA9", "PA10", "PA11",
673 "PA12", "PA13", "PA14", "PA15",
674 "PA16", "PA17", "PA18", "PA19",
675 "PA20", "PA21", "PA22", "PA23",
676 "PA24", "PA25", "PA26", "PA27";
677 allwinner,function = "gmac";
679 * data lines in GMII mode run at 125MHz and
680 * might need a higher signal drive strength
682 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
683 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
686 gmac_pins_rgmii_a: gmac_rgmii@0 {
687 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
688 "PA9", "PA10", "PA11",
689 "PA12", "PA13", "PA14", "PA19",
690 "PA20", "PA25", "PA26", "PA27";
691 allwinner,function = "gmac";
693 * data lines in RGMII mode use DDR mode
694 * and need a higher signal drive strength
696 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
697 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
701 ahb1_rst: reset@01c202c0 {
703 compatible = "allwinner,sun6i-a31-ahb1-reset";
704 reg = <0x01c202c0 0xc>;
707 apb1_rst: reset@01c202d0 {
709 compatible = "allwinner,sun6i-a31-clock-reset";
710 reg = <0x01c202d0 0x4>;
713 apb2_rst: reset@01c202d8 {
715 compatible = "allwinner,sun6i-a31-clock-reset";
716 reg = <0x01c202d8 0x4>;
720 compatible = "allwinner,sun4i-a10-timer";
721 reg = <0x01c20c00 0xa0>;
722 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
730 wdt1: watchdog@01c20ca0 {
731 compatible = "allwinner,sun6i-a31-wdt";
732 reg = <0x01c20ca0 0x20>;
736 compatible = "allwinner,sun6i-a31-ts";
737 reg = <0x01c25000 0x100>;
738 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
739 #thermal-sensor-cells = <0>;
742 uart0: serial@01c28000 {
743 compatible = "snps,dw-apb-uart";
744 reg = <0x01c28000 0x400>;
745 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&apb2_gates 16>;
749 resets = <&apb2_rst 16>;
750 dmas = <&dma 6>, <&dma 6>;
751 dma-names = "rx", "tx";
755 uart1: serial@01c28400 {
756 compatible = "snps,dw-apb-uart";
757 reg = <0x01c28400 0x400>;
758 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&apb2_gates 17>;
762 resets = <&apb2_rst 17>;
763 dmas = <&dma 7>, <&dma 7>;
764 dma-names = "rx", "tx";
768 uart2: serial@01c28800 {
769 compatible = "snps,dw-apb-uart";
770 reg = <0x01c28800 0x400>;
771 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&apb2_gates 18>;
775 resets = <&apb2_rst 18>;
776 dmas = <&dma 8>, <&dma 8>;
777 dma-names = "rx", "tx";
781 uart3: serial@01c28c00 {
782 compatible = "snps,dw-apb-uart";
783 reg = <0x01c28c00 0x400>;
784 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&apb2_gates 19>;
788 resets = <&apb2_rst 19>;
789 dmas = <&dma 9>, <&dma 9>;
790 dma-names = "rx", "tx";
794 uart4: serial@01c29000 {
795 compatible = "snps,dw-apb-uart";
796 reg = <0x01c29000 0x400>;
797 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&apb2_gates 20>;
801 resets = <&apb2_rst 20>;
802 dmas = <&dma 10>, <&dma 10>;
803 dma-names = "rx", "tx";
807 uart5: serial@01c29400 {
808 compatible = "snps,dw-apb-uart";
809 reg = <0x01c29400 0x400>;
810 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&apb2_gates 21>;
814 resets = <&apb2_rst 21>;
815 dmas = <&dma 22>, <&dma 22>;
816 dma-names = "rx", "tx";
821 compatible = "allwinner,sun6i-a31-i2c";
822 reg = <0x01c2ac00 0x400>;
823 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&apb2_gates 0>;
825 resets = <&apb2_rst 0>;
827 #address-cells = <1>;
832 compatible = "allwinner,sun6i-a31-i2c";
833 reg = <0x01c2b000 0x400>;
834 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&apb2_gates 1>;
836 resets = <&apb2_rst 1>;
838 #address-cells = <1>;
843 compatible = "allwinner,sun6i-a31-i2c";
844 reg = <0x01c2b400 0x400>;
845 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&apb2_gates 2>;
847 resets = <&apb2_rst 2>;
849 #address-cells = <1>;
854 compatible = "allwinner,sun6i-a31-i2c";
855 reg = <0x01c2b800 0x400>;
856 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&apb2_gates 3>;
858 resets = <&apb2_rst 3>;
860 #address-cells = <1>;
864 gmac: ethernet@01c30000 {
865 compatible = "allwinner,sun7i-a20-gmac";
866 reg = <0x01c30000 0x1054>;
867 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "macirq";
869 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
870 clock-names = "stmmaceth", "allwinner_gmac_tx";
871 resets = <&ahb1_rst 17>;
872 reset-names = "stmmaceth";
875 snps,force_sf_dma_mode;
877 #address-cells = <1>;
881 crypto: crypto-engine@01c15000 {
882 compatible = "allwinner,sun4i-a10-crypto";
883 reg = <0x01c15000 0x1000>;
884 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&ahb1_gates 5>, <&ss_clk>;
886 clock-names = "ahb", "mod";
887 resets = <&ahb1_rst 5>;
892 compatible = "allwinner,sun6i-a31-hstimer",
893 "allwinner,sun7i-a20-hstimer";
894 reg = <0x01c60000 0x1000>;
895 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&ahb1_gates 19>;
900 resets = <&ahb1_rst 19>;
904 compatible = "allwinner,sun6i-a31-spi";
905 reg = <0x01c68000 0x1000>;
906 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&ahb1_gates 20>, <&spi0_clk>;
908 clock-names = "ahb", "mod";
909 dmas = <&dma 23>, <&dma 23>;
910 dma-names = "rx", "tx";
911 resets = <&ahb1_rst 20>;
916 compatible = "allwinner,sun6i-a31-spi";
917 reg = <0x01c69000 0x1000>;
918 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&ahb1_gates 21>, <&spi1_clk>;
920 clock-names = "ahb", "mod";
921 dmas = <&dma 24>, <&dma 24>;
922 dma-names = "rx", "tx";
923 resets = <&ahb1_rst 21>;
928 compatible = "allwinner,sun6i-a31-spi";
929 reg = <0x01c6a000 0x1000>;
930 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ahb1_gates 22>, <&spi2_clk>;
932 clock-names = "ahb", "mod";
933 dmas = <&dma 25>, <&dma 25>;
934 dma-names = "rx", "tx";
935 resets = <&ahb1_rst 22>;
940 compatible = "allwinner,sun6i-a31-spi";
941 reg = <0x01c6b000 0x1000>;
942 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&ahb1_gates 23>, <&spi3_clk>;
944 clock-names = "ahb", "mod";
945 dmas = <&dma 26>, <&dma 26>;
946 dma-names = "rx", "tx";
947 resets = <&ahb1_rst 23>;
951 gic: interrupt-controller@01c81000 {
952 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
953 reg = <0x01c81000 0x1000>,
957 interrupt-controller;
958 #interrupt-cells = <3>;
959 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
963 compatible = "allwinner,sun6i-a31-rtc";
964 reg = <0x01f00000 0x54>;
965 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
969 nmi_intc: interrupt-controller@01f00c0c {
970 compatible = "allwinner,sun6i-a31-sc-nmi";
971 interrupt-controller;
972 #interrupt-cells = <2>;
973 reg = <0x01f00c0c 0x38>;
974 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
978 compatible = "allwinner,sun6i-a31-prcm";
979 reg = <0x01f01400 0x200>;
982 compatible = "allwinner,sun6i-a31-ar100-clk";
984 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
986 clock-output-names = "ar100";
990 compatible = "fixed-factor-clock";
995 clock-output-names = "ahb0";
999 compatible = "allwinner,sun6i-a31-apb0-clk";
1002 clock-output-names = "apb0";
1005 apb0_gates: apb0_gates_clk {
1006 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1009 clock-output-names = "apb0_pio", "apb0_ir",
1010 "apb0_timer", "apb0_p2wi",
1011 "apb0_uart", "apb0_1wire",
1017 compatible = "allwinner,sun4i-a10-mod0-clk";
1018 clocks = <&osc32k>, <&osc24M>;
1019 clock-output-names = "ir";
1022 apb0_rst: apb0_rst {
1023 compatible = "allwinner,sun6i-a31-clock-reset";
1029 compatible = "allwinner,sun6i-a31-cpuconfig";
1030 reg = <0x01f01c00 0x300>;
1034 compatible = "allwinner,sun5i-a13-ir";
1035 clocks = <&apb0_gates 1>, <&ir_clk>;
1036 clock-names = "apb", "ir";
1037 resets = <&apb0_rst 1>;
1038 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1039 reg = <0x01f02000 0x40>;
1040 status = "disabled";
1043 r_pio: pinctrl@01f02c00 {
1044 compatible = "allwinner,sun6i-a31-r-pinctrl";
1045 reg = <0x01f02c00 0x400>;
1046 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&apb0_gates 0>;
1049 resets = <&apb0_rst 0>;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1057 allwinner,pins = "PL4";
1058 allwinner,function = "s_ir";
1059 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1060 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1064 allwinner,pins = "PL0", "PL1";
1065 allwinner,function = "s_p2wi";
1066 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1067 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1071 p2wi: i2c@01f03400 {
1072 compatible = "allwinner,sun6i-a31-p2wi";
1073 reg = <0x01f03400 0x400>;
1074 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&apb0_gates 3>;
1076 clock-frequency = <100000>;
1077 resets = <&apb0_rst 3>;
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&p2wi_pins>;
1080 status = "disabled";
1081 #address-cells = <1>;