2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
65 simplefb_hdmi: framebuffer-lcd0-hdmi {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
76 simplefb_lcd: framebuffer-lcd0 {
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
98 enable-method = "allwinner,sun6i-a31";
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
122 clocks = <&ccu CLK_CPU>;
123 clock-latency = <244144>; /* 8 32k periods */
131 #cooling-cells = <2>;
135 compatible = "arm,cortex-a7";
138 clocks = <&ccu CLK_CPU>;
139 clock-latency = <244144>; /* 8 32k periods */
147 #cooling-cells = <2>;
151 compatible = "arm,cortex-a7";
154 clocks = <&ccu CLK_CPU>;
155 clock-latency = <244144>; /* 8 32k periods */
163 #cooling-cells = <2>;
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
172 thermal-sensors = <&rtp>;
176 trip = <&cpu_alert0>;
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
180 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185 cpu_alert0: cpu_alert0 {
187 temperature = <70000>;
194 temperature = <100000>;
203 compatible = "arm,cortex-a7-pmu";
204 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
217 compatible = "fixed-clock";
218 clock-frequency = <24000000>;
219 clock-accuracy = <50000>;
220 clock-output-names = "osc24M";
225 compatible = "fixed-clock";
226 clock-frequency = <32768>;
227 clock-accuracy = <50000>;
228 clock-output-names = "ext_osc32k";
232 * The following two are dummy clocks, placeholders
233 * used in the gmac_tx clock. The gmac driver will
234 * choose one parent depending on the PHY interface
235 * mode, using clk_set_rate auto-reparenting.
237 * The actual TX clock rate is not controlled by the
240 mii_phy_tx_clk: clk-mii-phy-tx {
242 compatible = "fixed-clock";
243 clock-frequency = <25000000>;
244 clock-output-names = "mii_phy_tx";
247 gmac_int_tx_clk: clk-gmac-int-tx {
249 compatible = "fixed-clock";
250 clock-frequency = <125000000>;
251 clock-output-names = "gmac_int_tx";
254 gmac_tx_clk: clk@1c200d0 {
256 compatible = "allwinner,sun7i-a20-gmac-clk";
257 reg = <0x01c200d0 0x4>;
258 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
259 clock-output-names = "gmac_tx";
264 compatible = "allwinner,sun6i-a31-display-engine";
265 allwinner,pipelines = <&fe0>, <&fe1>;
270 compatible = "simple-bus";
271 #address-cells = <1>;
275 dma: dma-controller@1c02000 {
276 compatible = "allwinner,sun6i-a31-dma";
277 reg = <0x01c02000 0x1000>;
278 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_AHB1_DMA>;
280 resets = <&ccu RST_AHB1_DMA>;
284 tcon0: lcd-controller@1c0c000 {
285 compatible = "allwinner,sun6i-a31-tcon";
286 reg = <0x01c0c000 0x1000>;
287 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
288 resets = <&ccu RST_AHB1_LCD0>;
290 clocks = <&ccu CLK_AHB1_LCD0>,
296 clock-output-names = "tcon0-pixel-clock";
300 #address-cells = <1>;
304 #address-cells = <1>;
308 tcon0_in_drc0: endpoint@0 {
310 remote-endpoint = <&drc0_out_tcon0>;
313 tcon0_in_drc1: endpoint@1 {
315 remote-endpoint = <&drc1_out_tcon0>;
320 #address-cells = <1>;
324 tcon0_out_hdmi: endpoint@1 {
326 remote-endpoint = <&hdmi_in_tcon0>;
327 allwinner,tcon-channel = <1>;
333 tcon1: lcd-controller@1c0d000 {
334 compatible = "allwinner,sun6i-a31-tcon";
335 reg = <0x01c0d000 0x1000>;
336 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
337 resets = <&ccu RST_AHB1_LCD1>;
339 clocks = <&ccu CLK_AHB1_LCD1>,
345 clock-output-names = "tcon1-pixel-clock";
349 #address-cells = <1>;
353 #address-cells = <1>;
357 tcon1_in_drc0: endpoint@0 {
359 remote-endpoint = <&drc0_out_tcon1>;
362 tcon1_in_drc1: endpoint@1 {
364 remote-endpoint = <&drc1_out_tcon1>;
369 #address-cells = <1>;
373 tcon1_out_hdmi: endpoint@1 {
375 remote-endpoint = <&hdmi_in_tcon1>;
376 allwinner,tcon-channel = <1>;
383 compatible = "allwinner,sun7i-a20-mmc";
384 reg = <0x01c0f000 0x1000>;
385 clocks = <&ccu CLK_AHB1_MMC0>,
387 <&ccu CLK_MMC0_OUTPUT>,
388 <&ccu CLK_MMC0_SAMPLE>;
393 resets = <&ccu RST_AHB1_MMC0>;
395 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&mmc0_pins>;
399 #address-cells = <1>;
404 compatible = "allwinner,sun7i-a20-mmc";
405 reg = <0x01c10000 0x1000>;
406 clocks = <&ccu CLK_AHB1_MMC1>,
408 <&ccu CLK_MMC1_OUTPUT>,
409 <&ccu CLK_MMC1_SAMPLE>;
414 resets = <&ccu RST_AHB1_MMC1>;
416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&mmc1_pins>;
420 #address-cells = <1>;
425 compatible = "allwinner,sun7i-a20-mmc";
426 reg = <0x01c11000 0x1000>;
427 clocks = <&ccu CLK_AHB1_MMC2>,
429 <&ccu CLK_MMC2_OUTPUT>,
430 <&ccu CLK_MMC2_SAMPLE>;
435 resets = <&ccu RST_AHB1_MMC2>;
437 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
444 compatible = "allwinner,sun7i-a20-mmc";
445 reg = <0x01c12000 0x1000>;
446 clocks = <&ccu CLK_AHB1_MMC3>,
448 <&ccu CLK_MMC3_OUTPUT>,
449 <&ccu CLK_MMC3_SAMPLE>;
454 resets = <&ccu RST_AHB1_MMC3>;
456 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>;
463 compatible = "allwinner,sun6i-a31-hdmi";
464 reg = <0x01c16000 0x1000>;
465 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
468 <&ccu CLK_PLL_VIDEO0_2X>,
469 <&ccu CLK_PLL_VIDEO1_2X>;
470 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
471 resets = <&ccu RST_AHB1_HDMI>;
473 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
474 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
478 #address-cells = <1>;
482 #address-cells = <1>;
486 hdmi_in_tcon0: endpoint@0 {
488 remote-endpoint = <&tcon0_out_hdmi>;
491 hdmi_in_tcon1: endpoint@1 {
493 remote-endpoint = <&tcon1_out_hdmi>;
503 usb_otg: usb@1c19000 {
504 compatible = "allwinner,sun6i-a31-musb";
505 reg = <0x01c19000 0x0400>;
506 clocks = <&ccu CLK_AHB1_OTG>;
507 resets = <&ccu RST_AHB1_OTG>;
508 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-names = "mc";
512 extcon = <&usbphy 0>;
517 usbphy: phy@1c19400 {
518 compatible = "allwinner,sun6i-a31-usb-phy";
519 reg = <0x01c19400 0x10>,
522 reg-names = "phy_ctrl",
525 clocks = <&ccu CLK_USB_PHY0>,
528 clock-names = "usb0_phy",
531 resets = <&ccu RST_USB_PHY0>,
534 reset-names = "usb0_reset",
542 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
543 reg = <0x01c1a000 0x100>;
544 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&ccu CLK_AHB1_EHCI0>;
546 resets = <&ccu RST_AHB1_EHCI0>;
552 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
553 reg = <0x01c1a400 0x100>;
554 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
556 resets = <&ccu RST_AHB1_OHCI0>;
562 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
563 reg = <0x01c1b000 0x100>;
564 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&ccu CLK_AHB1_EHCI1>;
566 resets = <&ccu RST_AHB1_EHCI1>;
572 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
573 reg = <0x01c1b400 0x100>;
574 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
576 resets = <&ccu RST_AHB1_OHCI1>;
582 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
583 reg = <0x01c1c400 0x100>;
584 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
586 resets = <&ccu RST_AHB1_OHCI2>;
591 compatible = "allwinner,sun6i-a31-ccu";
592 reg = <0x01c20000 0x400>;
593 clocks = <&osc24M>, <&rtc 0>;
594 clock-names = "hosc", "losc";
599 pio: pinctrl@1c20800 {
600 compatible = "allwinner,sun6i-a31-pinctrl";
601 reg = <0x01c20800 0x400>;
602 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
607 clock-names = "apb", "hosc", "losc";
609 interrupt-controller;
610 #interrupt-cells = <3>;
613 gmac_gmii_pins: gmac-gmii-pins {
614 pins = "PA0", "PA1", "PA2", "PA3",
615 "PA4", "PA5", "PA6", "PA7",
616 "PA8", "PA9", "PA10", "PA11",
617 "PA12", "PA13", "PA14", "PA15",
618 "PA16", "PA17", "PA18", "PA19",
619 "PA20", "PA21", "PA22", "PA23",
620 "PA24", "PA25", "PA26", "PA27";
623 * data lines in GMII mode run at 125MHz and
624 * might need a higher signal drive strength
626 drive-strength = <30>;
629 gmac_mii_pins: gmac-mii-pins {
630 pins = "PA0", "PA1", "PA2", "PA3",
631 "PA8", "PA9", "PA11",
632 "PA12", "PA13", "PA14", "PA19",
633 "PA20", "PA21", "PA22", "PA23",
634 "PA24", "PA26", "PA27";
638 gmac_rgmii_pins: gmac-rgmii-pins {
639 pins = "PA0", "PA1", "PA2", "PA3",
640 "PA9", "PA10", "PA11",
641 "PA12", "PA13", "PA14", "PA19",
642 "PA20", "PA25", "PA26", "PA27";
645 * data lines in RGMII mode use DDR mode
646 * and need a higher signal drive strength
648 drive-strength = <40>;
651 i2c0_pins: i2c0-pins {
652 pins = "PH14", "PH15";
656 i2c1_pins: i2c1-pins {
657 pins = "PH16", "PH17";
661 i2c2_pins: i2c2-pins {
662 pins = "PH18", "PH19";
666 lcd0_rgb888_pins: lcd0-rgb888-pins {
667 pins = "PD0", "PD1", "PD2", "PD3",
668 "PD4", "PD5", "PD6", "PD7",
669 "PD8", "PD9", "PD10", "PD11",
670 "PD12", "PD13", "PD14", "PD15",
671 "PD16", "PD17", "PD18", "PD19",
672 "PD20", "PD21", "PD22", "PD23",
673 "PD24", "PD25", "PD26", "PD27";
677 mmc0_pins: mmc0-pins {
678 pins = "PF0", "PF1", "PF2",
681 drive-strength = <30>;
685 mmc1_pins: mmc1-pins {
686 pins = "PG0", "PG1", "PG2", "PG3",
689 drive-strength = <30>;
693 mmc2_4bit_pins: mmc2-4bit-pins {
694 pins = "PC6", "PC7", "PC8", "PC9",
697 drive-strength = <30>;
701 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
702 pins = "PC6", "PC7", "PC8", "PC9",
703 "PC10", "PC11", "PC12",
704 "PC13", "PC14", "PC15",
707 drive-strength = <30>;
711 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
712 pins = "PC6", "PC7", "PC8", "PC9",
713 "PC10", "PC11", "PC12",
714 "PC13", "PC14", "PC15",
717 drive-strength = <40>;
721 spdif_tx_pin: spdif-tx-pin {
726 uart0_ph_pins: uart0-ph-pins {
727 pins = "PH20", "PH21";
733 compatible = "allwinner,sun4i-a10-timer";
734 reg = <0x01c20c00 0xa0>;
735 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
744 wdt1: watchdog@1c20ca0 {
745 compatible = "allwinner,sun6i-a31-wdt";
746 reg = <0x01c20ca0 0x20>;
747 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
751 spdif: spdif@1c21000 {
752 #sound-dai-cells = <0>;
753 compatible = "allwinner,sun6i-a31-spdif";
754 reg = <0x01c21000 0x400>;
755 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
757 resets = <&ccu RST_APB1_SPDIF>;
758 clock-names = "apb", "spdif";
759 dmas = <&dma 2>, <&dma 2>;
760 dma-names = "rx", "tx";
765 #sound-dai-cells = <0>;
766 compatible = "allwinner,sun6i-a31-i2s";
767 reg = <0x01c22000 0x400>;
768 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
770 resets = <&ccu RST_APB1_DAUDIO0>;
771 clock-names = "apb", "mod";
772 dmas = <&dma 3>, <&dma 3>;
773 dma-names = "rx", "tx";
778 #sound-dai-cells = <0>;
779 compatible = "allwinner,sun6i-a31-i2s";
780 reg = <0x01c22400 0x400>;
781 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
783 resets = <&ccu RST_APB1_DAUDIO1>;
784 clock-names = "apb", "mod";
785 dmas = <&dma 4>, <&dma 4>;
786 dma-names = "rx", "tx";
790 lradc: lradc@1c22800 {
791 compatible = "allwinner,sun4i-a10-lradc-keys";
792 reg = <0x01c22800 0x100>;
793 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
798 compatible = "allwinner,sun6i-a31-ts";
799 reg = <0x01c25000 0x100>;
800 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
801 #thermal-sensor-cells = <0>;
804 uart0: serial@1c28000 {
805 compatible = "snps,dw-apb-uart";
806 reg = <0x01c28000 0x400>;
807 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&ccu CLK_APB2_UART0>;
811 resets = <&ccu RST_APB2_UART0>;
812 dmas = <&dma 6>, <&dma 6>;
813 dma-names = "rx", "tx";
817 uart1: serial@1c28400 {
818 compatible = "snps,dw-apb-uart";
819 reg = <0x01c28400 0x400>;
820 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&ccu CLK_APB2_UART1>;
824 resets = <&ccu RST_APB2_UART1>;
825 dmas = <&dma 7>, <&dma 7>;
826 dma-names = "rx", "tx";
830 uart2: serial@1c28800 {
831 compatible = "snps,dw-apb-uart";
832 reg = <0x01c28800 0x400>;
833 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&ccu CLK_APB2_UART2>;
837 resets = <&ccu RST_APB2_UART2>;
838 dmas = <&dma 8>, <&dma 8>;
839 dma-names = "rx", "tx";
843 uart3: serial@1c28c00 {
844 compatible = "snps,dw-apb-uart";
845 reg = <0x01c28c00 0x400>;
846 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&ccu CLK_APB2_UART3>;
850 resets = <&ccu RST_APB2_UART3>;
851 dmas = <&dma 9>, <&dma 9>;
852 dma-names = "rx", "tx";
856 uart4: serial@1c29000 {
857 compatible = "snps,dw-apb-uart";
858 reg = <0x01c29000 0x400>;
859 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&ccu CLK_APB2_UART4>;
863 resets = <&ccu RST_APB2_UART4>;
864 dmas = <&dma 10>, <&dma 10>;
865 dma-names = "rx", "tx";
869 uart5: serial@1c29400 {
870 compatible = "snps,dw-apb-uart";
871 reg = <0x01c29400 0x400>;
872 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&ccu CLK_APB2_UART5>;
876 resets = <&ccu RST_APB2_UART5>;
877 dmas = <&dma 22>, <&dma 22>;
878 dma-names = "rx", "tx";
883 compatible = "allwinner,sun6i-a31-i2c";
884 reg = <0x01c2ac00 0x400>;
885 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&ccu CLK_APB2_I2C0>;
887 resets = <&ccu RST_APB2_I2C0>;
888 pinctrl-names = "default";
889 pinctrl-0 = <&i2c0_pins>;
891 #address-cells = <1>;
896 compatible = "allwinner,sun6i-a31-i2c";
897 reg = <0x01c2b000 0x400>;
898 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&ccu CLK_APB2_I2C1>;
900 resets = <&ccu RST_APB2_I2C1>;
901 pinctrl-names = "default";
902 pinctrl-0 = <&i2c1_pins>;
904 #address-cells = <1>;
909 compatible = "allwinner,sun6i-a31-i2c";
910 reg = <0x01c2b400 0x400>;
911 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&ccu CLK_APB2_I2C2>;
913 resets = <&ccu RST_APB2_I2C2>;
914 pinctrl-names = "default";
915 pinctrl-0 = <&i2c2_pins>;
917 #address-cells = <1>;
922 compatible = "allwinner,sun6i-a31-i2c";
923 reg = <0x01c2b800 0x400>;
924 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&ccu CLK_APB2_I2C3>;
926 resets = <&ccu RST_APB2_I2C3>;
928 #address-cells = <1>;
932 gmac: ethernet@1c30000 {
933 compatible = "allwinner,sun7i-a20-gmac";
934 reg = <0x01c30000 0x1054>;
935 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
936 interrupt-names = "macirq";
937 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
938 clock-names = "stmmaceth", "allwinner_gmac_tx";
939 resets = <&ccu RST_AHB1_EMAC>;
940 reset-names = "stmmaceth";
943 snps,force_sf_dma_mode;
947 compatible = "snps,dwmac-mdio";
948 #address-cells = <1>;
953 crypto: crypto-engine@1c15000 {
954 compatible = "allwinner,sun6i-a31-crypto",
955 "allwinner,sun4i-a10-crypto";
956 reg = <0x01c15000 0x1000>;
957 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
959 clock-names = "ahb", "mod";
960 resets = <&ccu RST_AHB1_SS>;
964 codec: codec@1c22c00 {
965 #sound-dai-cells = <0>;
966 compatible = "allwinner,sun6i-a31-codec";
967 reg = <0x01c22c00 0x400>;
968 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
970 clock-names = "apb", "codec";
971 resets = <&ccu RST_APB1_CODEC>;
972 dmas = <&dma 15>, <&dma 15>;
973 dma-names = "rx", "tx";
978 compatible = "allwinner,sun6i-a31-hstimer",
979 "allwinner,sun7i-a20-hstimer";
980 reg = <0x01c60000 0x1000>;
981 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&ccu CLK_AHB1_HSTIMER>;
986 resets = <&ccu RST_AHB1_HSTIMER>;
990 compatible = "allwinner,sun6i-a31-spi";
991 reg = <0x01c68000 0x1000>;
992 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
994 clock-names = "ahb", "mod";
995 dmas = <&dma 23>, <&dma 23>;
996 dma-names = "rx", "tx";
997 resets = <&ccu RST_AHB1_SPI0>;
999 #address-cells = <1>;
1004 compatible = "allwinner,sun6i-a31-spi";
1005 reg = <0x01c69000 0x1000>;
1006 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1008 clock-names = "ahb", "mod";
1009 dmas = <&dma 24>, <&dma 24>;
1010 dma-names = "rx", "tx";
1011 resets = <&ccu RST_AHB1_SPI1>;
1012 status = "disabled";
1013 #address-cells = <1>;
1018 compatible = "allwinner,sun6i-a31-spi";
1019 reg = <0x01c6a000 0x1000>;
1020 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1022 clock-names = "ahb", "mod";
1023 dmas = <&dma 25>, <&dma 25>;
1024 dma-names = "rx", "tx";
1025 resets = <&ccu RST_AHB1_SPI2>;
1026 status = "disabled";
1027 #address-cells = <1>;
1032 compatible = "allwinner,sun6i-a31-spi";
1033 reg = <0x01c6b000 0x1000>;
1034 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1036 clock-names = "ahb", "mod";
1037 dmas = <&dma 26>, <&dma 26>;
1038 dma-names = "rx", "tx";
1039 resets = <&ccu RST_AHB1_SPI3>;
1040 status = "disabled";
1041 #address-cells = <1>;
1045 gic: interrupt-controller@1c81000 {
1046 compatible = "arm,gic-400";
1047 reg = <0x01c81000 0x1000>,
1048 <0x01c82000 0x2000>,
1049 <0x01c84000 0x2000>,
1050 <0x01c86000 0x2000>;
1051 interrupt-controller;
1052 #interrupt-cells = <3>;
1053 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1056 fe0: display-frontend@1e00000 {
1057 compatible = "allwinner,sun6i-a31-display-frontend";
1058 reg = <0x01e00000 0x20000>;
1059 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1061 <&ccu CLK_DRAM_FE0>;
1062 clock-names = "ahb", "mod",
1064 resets = <&ccu RST_AHB1_FE0>;
1067 #address-cells = <1>;
1071 #address-cells = <1>;
1075 fe0_out_be0: endpoint@0 {
1077 remote-endpoint = <&be0_in_fe0>;
1080 fe0_out_be1: endpoint@1 {
1082 remote-endpoint = <&be1_in_fe0>;
1088 fe1: display-frontend@1e20000 {
1089 compatible = "allwinner,sun6i-a31-display-frontend";
1090 reg = <0x01e20000 0x20000>;
1091 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1093 <&ccu CLK_DRAM_FE1>;
1094 clock-names = "ahb", "mod",
1096 resets = <&ccu RST_AHB1_FE1>;
1099 #address-cells = <1>;
1103 #address-cells = <1>;
1107 fe1_out_be0: endpoint@0 {
1109 remote-endpoint = <&be0_in_fe1>;
1112 fe1_out_be1: endpoint@1 {
1114 remote-endpoint = <&be1_in_fe1>;
1120 be1: display-backend@1e40000 {
1121 compatible = "allwinner,sun6i-a31-display-backend";
1122 reg = <0x01e40000 0x10000>;
1123 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1125 <&ccu CLK_DRAM_BE1>;
1126 clock-names = "ahb", "mod",
1128 resets = <&ccu RST_AHB1_BE1>;
1130 assigned-clocks = <&ccu CLK_BE1>;
1131 assigned-clock-rates = <300000000>;
1134 #address-cells = <1>;
1138 #address-cells = <1>;
1142 be1_in_fe0: endpoint@0 {
1144 remote-endpoint = <&fe0_out_be1>;
1147 be1_in_fe1: endpoint@1 {
1149 remote-endpoint = <&fe1_out_be1>;
1154 #address-cells = <1>;
1158 be1_out_drc1: endpoint@1 {
1160 remote-endpoint = <&drc1_in_be1>;
1167 compatible = "allwinner,sun6i-a31-drc";
1168 reg = <0x01e50000 0x10000>;
1169 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1171 <&ccu CLK_DRAM_DRC1>;
1172 clock-names = "ahb", "mod",
1174 resets = <&ccu RST_AHB1_DRC1>;
1176 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1177 assigned-clock-rates = <300000000>;
1180 #address-cells = <1>;
1184 #address-cells = <1>;
1188 drc1_in_be1: endpoint@1 {
1190 remote-endpoint = <&be1_out_drc1>;
1195 #address-cells = <1>;
1199 drc1_out_tcon0: endpoint@0 {
1201 remote-endpoint = <&tcon0_in_drc1>;
1204 drc1_out_tcon1: endpoint@1 {
1206 remote-endpoint = <&tcon1_in_drc1>;
1212 be0: display-backend@1e60000 {
1213 compatible = "allwinner,sun6i-a31-display-backend";
1214 reg = <0x01e60000 0x10000>;
1215 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1217 <&ccu CLK_DRAM_BE0>;
1218 clock-names = "ahb", "mod",
1220 resets = <&ccu RST_AHB1_BE0>;
1222 assigned-clocks = <&ccu CLK_BE0>;
1223 assigned-clock-rates = <300000000>;
1226 #address-cells = <1>;
1230 #address-cells = <1>;
1234 be0_in_fe0: endpoint@0 {
1236 remote-endpoint = <&fe0_out_be0>;
1239 be0_in_fe1: endpoint@1 {
1241 remote-endpoint = <&fe1_out_be0>;
1248 be0_out_drc0: endpoint {
1249 remote-endpoint = <&drc0_in_be0>;
1256 compatible = "allwinner,sun6i-a31-drc";
1257 reg = <0x01e70000 0x10000>;
1258 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1260 <&ccu CLK_DRAM_DRC0>;
1261 clock-names = "ahb", "mod",
1263 resets = <&ccu RST_AHB1_DRC0>;
1265 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1266 assigned-clock-rates = <300000000>;
1269 #address-cells = <1>;
1275 drc0_in_be0: endpoint {
1276 remote-endpoint = <&be0_out_drc0>;
1281 #address-cells = <1>;
1285 drc0_out_tcon0: endpoint@0 {
1287 remote-endpoint = <&tcon0_in_drc0>;
1290 drc0_out_tcon1: endpoint@1 {
1292 remote-endpoint = <&tcon1_in_drc0>;
1300 compatible = "allwinner,sun6i-a31-rtc";
1301 reg = <0x01f00000 0x54>;
1302 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1305 clock-output-names = "osc32k";
1308 nmi_intc: interrupt-controller@1f00c00 {
1309 compatible = "allwinner,sun6i-a31-r-intc";
1310 interrupt-controller;
1311 #interrupt-cells = <2>;
1312 reg = <0x01f00c00 0x400>;
1313 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1317 compatible = "allwinner,sun6i-a31-prcm";
1318 reg = <0x01f01400 0x200>;
1321 compatible = "allwinner,sun6i-a31-ar100-clk";
1323 clocks = <&rtc 0>, <&osc24M>,
1324 <&ccu CLK_PLL_PERIPH>,
1325 <&ccu CLK_PLL_PERIPH>;
1326 clock-output-names = "ar100";
1330 compatible = "fixed-factor-clock";
1335 clock-output-names = "ahb0";
1339 compatible = "allwinner,sun6i-a31-apb0-clk";
1342 clock-output-names = "apb0";
1345 apb0_gates: apb0_gates_clk {
1346 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1349 clock-output-names = "apb0_pio", "apb0_ir",
1350 "apb0_timer", "apb0_p2wi",
1351 "apb0_uart", "apb0_1wire",
1357 compatible = "allwinner,sun4i-a10-mod0-clk";
1358 clocks = <&rtc 0>, <&osc24M>;
1359 clock-output-names = "ir";
1362 apb0_rst: apb0_rst {
1363 compatible = "allwinner,sun6i-a31-clock-reset";
1369 compatible = "allwinner,sun6i-a31-cpuconfig";
1370 reg = <0x01f01c00 0x300>;
1374 compatible = "allwinner,sun6i-a31-ir";
1375 clocks = <&apb0_gates 1>, <&ir_clk>;
1376 clock-names = "apb", "ir";
1377 resets = <&apb0_rst 1>;
1378 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1379 reg = <0x01f02000 0x40>;
1380 status = "disabled";
1383 r_pio: pinctrl@1f02c00 {
1384 compatible = "allwinner,sun6i-a31-r-pinctrl";
1385 reg = <0x01f02c00 0x400>;
1386 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1388 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
1389 clock-names = "apb", "hosc", "losc";
1390 resets = <&apb0_rst 0>;
1392 interrupt-controller;
1393 #interrupt-cells = <3>;
1396 s_ir_rx_pin: s-ir-rx-pin {
1401 s_p2wi_pins: s-p2wi-pins {
1402 pins = "PL0", "PL1";
1403 function = "s_p2wi";
1408 compatible = "allwinner,sun6i-a31-p2wi";
1409 reg = <0x01f03400 0x400>;
1410 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&apb0_gates 3>;
1412 clock-frequency = <100000>;
1413 resets = <&apb0_rst 3>;
1414 pinctrl-names = "default";
1415 pinctrl-0 = <&s_p2wi_pins>;
1416 status = "disabled";
1417 #address-cells = <1>;