arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 /include/ "skeleton.dtsi"
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57         };
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  66                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  67                         clocks = <&pll6 0>;
  68                         status = "disabled";
  69                 };
  70         };
  71
  72         cpus {
  73                 enable-method = "allwinner,sun6i-a31";
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76
  77                 cpu@0 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <0>;
  81                 };
  82
  83                 cpu@1 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                 };
  88
  89                 cpu@2 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <2>;
  93                 };
  94
  95                 cpu@3 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <3>;
  99                 };
 100         };
 101
 102         memory {
 103                 reg = <0x40000000 0x80000000>;
 104         };
 105
 106         pmu {
 107                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 108                 interrupts = <0 120 4>,
 109                              <0 121 4>,
 110                              <0 122 4>,
 111                              <0 123 4>;
 112         };
 113
 114         clocks {
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges;
 118
 119                 osc24M: osc24M {
 120                         #clock-cells = <0>;
 121                         compatible = "fixed-clock";
 122                         clock-frequency = <24000000>;
 123                 };
 124
 125                 osc32k: clk@0 {
 126                         #clock-cells = <0>;
 127                         compatible = "fixed-clock";
 128                         clock-frequency = <32768>;
 129                         clock-output-names = "osc32k";
 130                 };
 131
 132                 pll1: clk@01c20000 {
 133                         #clock-cells = <0>;
 134                         compatible = "allwinner,sun6i-a31-pll1-clk";
 135                         reg = <0x01c20000 0x4>;
 136                         clocks = <&osc24M>;
 137                         clock-output-names = "pll1";
 138                 };
 139
 140                 pll6: clk@01c20028 {
 141                         #clock-cells = <1>;
 142                         compatible = "allwinner,sun6i-a31-pll6-clk";
 143                         reg = <0x01c20028 0x4>;
 144                         clocks = <&osc24M>;
 145                         clock-output-names = "pll6", "pll6x2";
 146                 };
 147
 148                 cpu: cpu@01c20050 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-a10-cpu-clk";
 151                         reg = <0x01c20050 0x4>;
 152
 153                         /*
 154                          * PLL1 is listed twice here.
 155                          * While it looks suspicious, it's actually documented
 156                          * that way both in the datasheet and in the code from
 157                          * Allwinner.
 158                          */
 159                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 160                         clock-output-names = "cpu";
 161                 };
 162
 163                 axi: axi@01c20050 {
 164                         #clock-cells = <0>;
 165                         compatible = "allwinner,sun4i-a10-axi-clk";
 166                         reg = <0x01c20050 0x4>;
 167                         clocks = <&cpu>;
 168                         clock-output-names = "axi";
 169                 };
 170
 171                 ahb1: ahb1@01c20054 {
 172                         #clock-cells = <0>;
 173                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 174                         reg = <0x01c20054 0x4>;
 175                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 176                         clock-output-names = "ahb1";
 177                 };
 178
 179                 ahb1_gates: clk@01c20060 {
 180                         #clock-cells = <1>;
 181                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 182                         reg = <0x01c20060 0x8>;
 183                         clocks = <&ahb1>;
 184                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 185                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 186                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 187                                         "ahb1_nand0", "ahb1_sdram",
 188                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 189                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 190                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 191                                         "ahb1_ehci1", "ahb1_ohci0",
 192                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 193                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 194                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 195                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 196                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 197                                         "ahb1_drc0", "ahb1_drc1";
 198                 };
 199
 200                 apb1: apb1@01c20054 {
 201                         #clock-cells = <0>;
 202                         compatible = "allwinner,sun4i-a10-apb0-clk";
 203                         reg = <0x01c20054 0x4>;
 204                         clocks = <&ahb1>;
 205                         clock-output-names = "apb1";
 206                 };
 207
 208                 apb1_gates: clk@01c20068 {
 209                         #clock-cells = <1>;
 210                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 211                         reg = <0x01c20068 0x4>;
 212                         clocks = <&apb1>;
 213                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 214                                         "apb1_pio", "apb1_daudio0",
 215                                         "apb1_daudio1";
 216                 };
 217
 218                 apb2: clk@01c20058 {
 219                         #clock-cells = <0>;
 220                         compatible = "allwinner,sun4i-a10-apb1-clk";
 221                         reg = <0x01c20058 0x4>;
 222                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 223                         clock-output-names = "apb2";
 224                 };
 225
 226                 apb2_gates: clk@01c2006c {
 227                         #clock-cells = <1>;
 228                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 229                         reg = <0x01c2006c 0x4>;
 230                         clocks = <&apb2>;
 231                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 232                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 233                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 234                                         "apb2_uart4", "apb2_uart5";
 235                 };
 236
 237                 mmc0_clk: clk@01c20088 {
 238                         #clock-cells = <1>;
 239                         compatible = "allwinner,sun4i-a10-mmc-clk";
 240                         reg = <0x01c20088 0x4>;
 241                         clocks = <&osc24M>, <&pll6 0>;
 242                         clock-output-names = "mmc0",
 243                                              "mmc0_output",
 244                                              "mmc0_sample";
 245                 };
 246
 247                 mmc1_clk: clk@01c2008c {
 248                         #clock-cells = <1>;
 249                         compatible = "allwinner,sun4i-a10-mmc-clk";
 250                         reg = <0x01c2008c 0x4>;
 251                         clocks = <&osc24M>, <&pll6 0>;
 252                         clock-output-names = "mmc1",
 253                                              "mmc1_output",
 254                                              "mmc1_sample";
 255                 };
 256
 257                 mmc2_clk: clk@01c20090 {
 258                         #clock-cells = <1>;
 259                         compatible = "allwinner,sun4i-a10-mmc-clk";
 260                         reg = <0x01c20090 0x4>;
 261                         clocks = <&osc24M>, <&pll6 0>;
 262                         clock-output-names = "mmc2",
 263                                              "mmc2_output",
 264                                              "mmc2_sample";
 265                 };
 266
 267                 mmc3_clk: clk@01c20094 {
 268                         #clock-cells = <1>;
 269                         compatible = "allwinner,sun4i-a10-mmc-clk";
 270                         reg = <0x01c20094 0x4>;
 271                         clocks = <&osc24M>, <&pll6 0>;
 272                         clock-output-names = "mmc3",
 273                                              "mmc3_output",
 274                                              "mmc3_sample";
 275                 };
 276
 277                 spi0_clk: clk@01c200a0 {
 278                         #clock-cells = <0>;
 279                         compatible = "allwinner,sun4i-a10-mod0-clk";
 280                         reg = <0x01c200a0 0x4>;
 281                         clocks = <&osc24M>, <&pll6 0>;
 282                         clock-output-names = "spi0";
 283                 };
 284
 285                 spi1_clk: clk@01c200a4 {
 286                         #clock-cells = <0>;
 287                         compatible = "allwinner,sun4i-a10-mod0-clk";
 288                         reg = <0x01c200a4 0x4>;
 289                         clocks = <&osc24M>, <&pll6 0>;
 290                         clock-output-names = "spi1";
 291                 };
 292
 293                 spi2_clk: clk@01c200a8 {
 294                         #clock-cells = <0>;
 295                         compatible = "allwinner,sun4i-a10-mod0-clk";
 296                         reg = <0x01c200a8 0x4>;
 297                         clocks = <&osc24M>, <&pll6 0>;
 298                         clock-output-names = "spi2";
 299                 };
 300
 301                 spi3_clk: clk@01c200ac {
 302                         #clock-cells = <0>;
 303                         compatible = "allwinner,sun4i-a10-mod0-clk";
 304                         reg = <0x01c200ac 0x4>;
 305                         clocks = <&osc24M>, <&pll6 0>;
 306                         clock-output-names = "spi3";
 307                 };
 308
 309                 usb_clk: clk@01c200cc {
 310                         #clock-cells = <1>;
 311                         #reset-cells = <1>;
 312                         compatible = "allwinner,sun6i-a31-usb-clk";
 313                         reg = <0x01c200cc 0x4>;
 314                         clocks = <&osc24M>;
 315                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 316                                              "usb_ohci0", "usb_ohci1",
 317                                              "usb_ohci2";
 318                 };
 319
 320                 /*
 321                  * The following two are dummy clocks, placeholders used in the gmac_tx
 322                  * clock. The gmac driver will choose one parent depending on the PHY
 323                  * interface mode, using clk_set_rate auto-reparenting.
 324                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 325                  */
 326                 mii_phy_tx_clk: clk@1 {
 327                         #clock-cells = <0>;
 328                         compatible = "fixed-clock";
 329                         clock-frequency = <25000000>;
 330                         clock-output-names = "mii_phy_tx";
 331                 };
 332
 333                 gmac_int_tx_clk: clk@2 {
 334                         #clock-cells = <0>;
 335                         compatible = "fixed-clock";
 336                         clock-frequency = <125000000>;
 337                         clock-output-names = "gmac_int_tx";
 338                 };
 339
 340                 gmac_tx_clk: clk@01c200d0 {
 341                         #clock-cells = <0>;
 342                         compatible = "allwinner,sun7i-a20-gmac-clk";
 343                         reg = <0x01c200d0 0x4>;
 344                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 345                         clock-output-names = "gmac_tx";
 346                 };
 347         };
 348
 349         soc@01c00000 {
 350                 compatible = "simple-bus";
 351                 #address-cells = <1>;
 352                 #size-cells = <1>;
 353                 ranges;
 354
 355                 dma: dma-controller@01c02000 {
 356                         compatible = "allwinner,sun6i-a31-dma";
 357                         reg = <0x01c02000 0x1000>;
 358                         interrupts = <0 50 4>;
 359                         clocks = <&ahb1_gates 6>;
 360                         resets = <&ahb1_rst 6>;
 361                         #dma-cells = <1>;
 362
 363                         /* DMA controller requires AHB1 clocked from PLL6 */
 364                         assigned-clocks = <&ahb1>;
 365                         assigned-clock-parents = <&pll6 0>;
 366                 };
 367
 368                 mmc0: mmc@01c0f000 {
 369                         compatible = "allwinner,sun5i-a13-mmc";
 370                         reg = <0x01c0f000 0x1000>;
 371                         clocks = <&ahb1_gates 8>,
 372                                  <&mmc0_clk 0>,
 373                                  <&mmc0_clk 1>,
 374                                  <&mmc0_clk 2>;
 375                         clock-names = "ahb",
 376                                       "mmc",
 377                                       "output",
 378                                       "sample";
 379                         resets = <&ahb1_rst 8>;
 380                         reset-names = "ahb";
 381                         interrupts = <0 60 4>;
 382                         status = "disabled";
 383                 };
 384
 385                 mmc1: mmc@01c10000 {
 386                         compatible = "allwinner,sun5i-a13-mmc";
 387                         reg = <0x01c10000 0x1000>;
 388                         clocks = <&ahb1_gates 9>,
 389                                  <&mmc1_clk 0>,
 390                                  <&mmc1_clk 1>,
 391                                  <&mmc1_clk 2>;
 392                         clock-names = "ahb",
 393                                       "mmc",
 394                                       "output",
 395                                       "sample";
 396                         resets = <&ahb1_rst 9>;
 397                         reset-names = "ahb";
 398                         interrupts = <0 61 4>;
 399                         status = "disabled";
 400                 };
 401
 402                 mmc2: mmc@01c11000 {
 403                         compatible = "allwinner,sun5i-a13-mmc";
 404                         reg = <0x01c11000 0x1000>;
 405                         clocks = <&ahb1_gates 10>,
 406                                  <&mmc2_clk 0>,
 407                                  <&mmc2_clk 1>,
 408                                  <&mmc2_clk 2>;
 409                         clock-names = "ahb",
 410                                       "mmc",
 411                                       "output",
 412                                       "sample";
 413                         resets = <&ahb1_rst 10>;
 414                         reset-names = "ahb";
 415                         interrupts = <0 62 4>;
 416                         status = "disabled";
 417                 };
 418
 419                 mmc3: mmc@01c12000 {
 420                         compatible = "allwinner,sun5i-a13-mmc";
 421                         reg = <0x01c12000 0x1000>;
 422                         clocks = <&ahb1_gates 11>,
 423                                  <&mmc3_clk 0>,
 424                                  <&mmc3_clk 1>,
 425                                  <&mmc3_clk 2>;
 426                         clock-names = "ahb",
 427                                       "mmc",
 428                                       "output",
 429                                       "sample";
 430                         resets = <&ahb1_rst 11>;
 431                         reset-names = "ahb";
 432                         interrupts = <0 63 4>;
 433                         status = "disabled";
 434                 };
 435
 436                 usbphy: phy@01c19400 {
 437                         compatible = "allwinner,sun6i-a31-usb-phy";
 438                         reg = <0x01c19400 0x10>,
 439                               <0x01c1a800 0x4>,
 440                               <0x01c1b800 0x4>;
 441                         reg-names = "phy_ctrl",
 442                                     "pmu1",
 443                                     "pmu2";
 444                         clocks = <&usb_clk 8>,
 445                                  <&usb_clk 9>,
 446                                  <&usb_clk 10>;
 447                         clock-names = "usb0_phy",
 448                                       "usb1_phy",
 449                                       "usb2_phy";
 450                         resets = <&usb_clk 0>,
 451                                  <&usb_clk 1>,
 452                                  <&usb_clk 2>;
 453                         reset-names = "usb0_reset",
 454                                       "usb1_reset",
 455                                       "usb2_reset";
 456                         status = "disabled";
 457                         #phy-cells = <1>;
 458                 };
 459
 460                 ehci0: usb@01c1a000 {
 461                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 462                         reg = <0x01c1a000 0x100>;
 463                         interrupts = <0 72 4>;
 464                         clocks = <&ahb1_gates 26>;
 465                         resets = <&ahb1_rst 26>;
 466                         phys = <&usbphy 1>;
 467                         phy-names = "usb";
 468                         status = "disabled";
 469                 };
 470
 471                 ohci0: usb@01c1a400 {
 472                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 473                         reg = <0x01c1a400 0x100>;
 474                         interrupts = <0 73 4>;
 475                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 476                         resets = <&ahb1_rst 29>;
 477                         phys = <&usbphy 1>;
 478                         phy-names = "usb";
 479                         status = "disabled";
 480                 };
 481
 482                 ehci1: usb@01c1b000 {
 483                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 484                         reg = <0x01c1b000 0x100>;
 485                         interrupts = <0 74 4>;
 486                         clocks = <&ahb1_gates 27>;
 487                         resets = <&ahb1_rst 27>;
 488                         phys = <&usbphy 2>;
 489                         phy-names = "usb";
 490                         status = "disabled";
 491                 };
 492
 493                 ohci1: usb@01c1b400 {
 494                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 495                         reg = <0x01c1b400 0x100>;
 496                         interrupts = <0 75 4>;
 497                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 498                         resets = <&ahb1_rst 30>;
 499                         phys = <&usbphy 2>;
 500                         phy-names = "usb";
 501                         status = "disabled";
 502                 };
 503
 504                 ohci2: usb@01c1c400 {
 505                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 506                         reg = <0x01c1c400 0x100>;
 507                         interrupts = <0 77 4>;
 508                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 509                         resets = <&ahb1_rst 31>;
 510                         status = "disabled";
 511                 };
 512
 513                 pio: pinctrl@01c20800 {
 514                         compatible = "allwinner,sun6i-a31-pinctrl";
 515                         reg = <0x01c20800 0x400>;
 516                         interrupts = <0 11 4>,
 517                                      <0 15 4>,
 518                                      <0 16 4>,
 519                                      <0 17 4>;
 520                         clocks = <&apb1_gates 5>;
 521                         gpio-controller;
 522                         interrupt-controller;
 523                         #interrupt-cells = <2>;
 524                         #size-cells = <0>;
 525                         #gpio-cells = <3>;
 526
 527                         uart0_pins_a: uart0@0 {
 528                                 allwinner,pins = "PH20", "PH21";
 529                                 allwinner,function = "uart0";
 530                                 allwinner,drive = <0>;
 531                                 allwinner,pull = <0>;
 532                         };
 533
 534                         i2c0_pins_a: i2c0@0 {
 535                                 allwinner,pins = "PH14", "PH15";
 536                                 allwinner,function = "i2c0";
 537                                 allwinner,drive = <0>;
 538                                 allwinner,pull = <0>;
 539                         };
 540
 541                         i2c1_pins_a: i2c1@0 {
 542                                 allwinner,pins = "PH16", "PH17";
 543                                 allwinner,function = "i2c1";
 544                                 allwinner,drive = <0>;
 545                                 allwinner,pull = <0>;
 546                         };
 547
 548                         i2c2_pins_a: i2c2@0 {
 549                                 allwinner,pins = "PH18", "PH19";
 550                                 allwinner,function = "i2c2";
 551                                 allwinner,drive = <0>;
 552                                 allwinner,pull = <0>;
 553                         };
 554
 555                         mmc0_pins_a: mmc0@0 {
 556                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 557                                 allwinner,function = "mmc0";
 558                                 allwinner,drive = <2>;
 559                                 allwinner,pull = <0>;
 560                         };
 561
 562                         gmac_pins_mii_a: gmac_mii@0 {
 563                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 564                                                 "PA8", "PA9", "PA11",
 565                                                 "PA12", "PA13", "PA14", "PA19",
 566                                                 "PA20", "PA21", "PA22", "PA23",
 567                                                 "PA24", "PA26", "PA27";
 568                                 allwinner,function = "gmac";
 569                                 allwinner,drive = <0>;
 570                                 allwinner,pull = <0>;
 571                         };
 572
 573                         gmac_pins_gmii_a: gmac_gmii@0 {
 574                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 575                                                 "PA4", "PA5", "PA6", "PA7",
 576                                                 "PA8", "PA9", "PA10", "PA11",
 577                                                 "PA12", "PA13", "PA14", "PA15",
 578                                                 "PA16", "PA17", "PA18", "PA19",
 579                                                 "PA20", "PA21", "PA22", "PA23",
 580                                                 "PA24", "PA25", "PA26", "PA27";
 581                                 allwinner,function = "gmac";
 582                                 /*
 583                                  * data lines in GMII mode run at 125MHz and
 584                                  * might need a higher signal drive strength
 585                                  */
 586                                 allwinner,drive = <2>;
 587                                 allwinner,pull = <0>;
 588                         };
 589
 590                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 591                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 592                                                 "PA9", "PA10", "PA11",
 593                                                 "PA12", "PA13", "PA14", "PA19",
 594                                                 "PA20", "PA25", "PA26", "PA27";
 595                                 allwinner,function = "gmac";
 596                                 /*
 597                                  * data lines in RGMII mode use DDR mode
 598                                  * and need a higher signal drive strength
 599                                  */
 600                                 allwinner,drive = <3>;
 601                                 allwinner,pull = <0>;
 602                         };
 603                 };
 604
 605                 ahb1_rst: reset@01c202c0 {
 606                         #reset-cells = <1>;
 607                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 608                         reg = <0x01c202c0 0xc>;
 609                 };
 610
 611                 apb1_rst: reset@01c202d0 {
 612                         #reset-cells = <1>;
 613                         compatible = "allwinner,sun6i-a31-clock-reset";
 614                         reg = <0x01c202d0 0x4>;
 615                 };
 616
 617                 apb2_rst: reset@01c202d8 {
 618                         #reset-cells = <1>;
 619                         compatible = "allwinner,sun6i-a31-clock-reset";
 620                         reg = <0x01c202d8 0x4>;
 621                 };
 622
 623                 timer@01c20c00 {
 624                         compatible = "allwinner,sun4i-a10-timer";
 625                         reg = <0x01c20c00 0xa0>;
 626                         interrupts = <0 18 4>,
 627                                      <0 19 4>,
 628                                      <0 20 4>,
 629                                      <0 21 4>,
 630                                      <0 22 4>;
 631                         clocks = <&osc24M>;
 632                 };
 633
 634                 wdt1: watchdog@01c20ca0 {
 635                         compatible = "allwinner,sun6i-a31-wdt";
 636                         reg = <0x01c20ca0 0x20>;
 637                 };
 638
 639                 uart0: serial@01c28000 {
 640                         compatible = "snps,dw-apb-uart";
 641                         reg = <0x01c28000 0x400>;
 642                         interrupts = <0 0 4>;
 643                         reg-shift = <2>;
 644                         reg-io-width = <4>;
 645                         clocks = <&apb2_gates 16>;
 646                         resets = <&apb2_rst 16>;
 647                         dmas = <&dma 6>, <&dma 6>;
 648                         dma-names = "rx", "tx";
 649                         status = "disabled";
 650                 };
 651
 652                 uart1: serial@01c28400 {
 653                         compatible = "snps,dw-apb-uart";
 654                         reg = <0x01c28400 0x400>;
 655                         interrupts = <0 1 4>;
 656                         reg-shift = <2>;
 657                         reg-io-width = <4>;
 658                         clocks = <&apb2_gates 17>;
 659                         resets = <&apb2_rst 17>;
 660                         dmas = <&dma 7>, <&dma 7>;
 661                         dma-names = "rx", "tx";
 662                         status = "disabled";
 663                 };
 664
 665                 uart2: serial@01c28800 {
 666                         compatible = "snps,dw-apb-uart";
 667                         reg = <0x01c28800 0x400>;
 668                         interrupts = <0 2 4>;
 669                         reg-shift = <2>;
 670                         reg-io-width = <4>;
 671                         clocks = <&apb2_gates 18>;
 672                         resets = <&apb2_rst 18>;
 673                         dmas = <&dma 8>, <&dma 8>;
 674                         dma-names = "rx", "tx";
 675                         status = "disabled";
 676                 };
 677
 678                 uart3: serial@01c28c00 {
 679                         compatible = "snps,dw-apb-uart";
 680                         reg = <0x01c28c00 0x400>;
 681                         interrupts = <0 3 4>;
 682                         reg-shift = <2>;
 683                         reg-io-width = <4>;
 684                         clocks = <&apb2_gates 19>;
 685                         resets = <&apb2_rst 19>;
 686                         dmas = <&dma 9>, <&dma 9>;
 687                         dma-names = "rx", "tx";
 688                         status = "disabled";
 689                 };
 690
 691                 uart4: serial@01c29000 {
 692                         compatible = "snps,dw-apb-uart";
 693                         reg = <0x01c29000 0x400>;
 694                         interrupts = <0 4 4>;
 695                         reg-shift = <2>;
 696                         reg-io-width = <4>;
 697                         clocks = <&apb2_gates 20>;
 698                         resets = <&apb2_rst 20>;
 699                         dmas = <&dma 10>, <&dma 10>;
 700                         dma-names = "rx", "tx";
 701                         status = "disabled";
 702                 };
 703
 704                 uart5: serial@01c29400 {
 705                         compatible = "snps,dw-apb-uart";
 706                         reg = <0x01c29400 0x400>;
 707                         interrupts = <0 5 4>;
 708                         reg-shift = <2>;
 709                         reg-io-width = <4>;
 710                         clocks = <&apb2_gates 21>;
 711                         resets = <&apb2_rst 21>;
 712                         dmas = <&dma 22>, <&dma 22>;
 713                         dma-names = "rx", "tx";
 714                         status = "disabled";
 715                 };
 716
 717                 i2c0: i2c@01c2ac00 {
 718                         compatible = "allwinner,sun6i-a31-i2c";
 719                         reg = <0x01c2ac00 0x400>;
 720                         interrupts = <0 6 4>;
 721                         clocks = <&apb2_gates 0>;
 722                         resets = <&apb2_rst 0>;
 723                         status = "disabled";
 724                         #address-cells = <1>;
 725                         #size-cells = <0>;
 726                 };
 727
 728                 i2c1: i2c@01c2b000 {
 729                         compatible = "allwinner,sun6i-a31-i2c";
 730                         reg = <0x01c2b000 0x400>;
 731                         interrupts = <0 7 4>;
 732                         clocks = <&apb2_gates 1>;
 733                         resets = <&apb2_rst 1>;
 734                         status = "disabled";
 735                         #address-cells = <1>;
 736                         #size-cells = <0>;
 737                 };
 738
 739                 i2c2: i2c@01c2b400 {
 740                         compatible = "allwinner,sun6i-a31-i2c";
 741                         reg = <0x01c2b400 0x400>;
 742                         interrupts = <0 8 4>;
 743                         clocks = <&apb2_gates 2>;
 744                         resets = <&apb2_rst 2>;
 745                         status = "disabled";
 746                         #address-cells = <1>;
 747                         #size-cells = <0>;
 748                 };
 749
 750                 i2c3: i2c@01c2b800 {
 751                         compatible = "allwinner,sun6i-a31-i2c";
 752                         reg = <0x01c2b800 0x400>;
 753                         interrupts = <0 9 4>;
 754                         clocks = <&apb2_gates 3>;
 755                         resets = <&apb2_rst 3>;
 756                         status = "disabled";
 757                         #address-cells = <1>;
 758                         #size-cells = <0>;
 759                 };
 760
 761                 gmac: ethernet@01c30000 {
 762                         compatible = "allwinner,sun7i-a20-gmac";
 763                         reg = <0x01c30000 0x1054>;
 764                         interrupts = <0 82 4>;
 765                         interrupt-names = "macirq";
 766                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 767                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 768                         resets = <&ahb1_rst 17>;
 769                         reset-names = "stmmaceth";
 770                         snps,pbl = <2>;
 771                         snps,fixed-burst;
 772                         snps,force_sf_dma_mode;
 773                         status = "disabled";
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776                 };
 777
 778                 timer@01c60000 {
 779                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 780                         reg = <0x01c60000 0x1000>;
 781                         interrupts = <0 51 4>,
 782                                      <0 52 4>,
 783                                      <0 53 4>,
 784                                      <0 54 4>;
 785                         clocks = <&ahb1_gates 19>;
 786                         resets = <&ahb1_rst 19>;
 787                 };
 788
 789                 spi0: spi@01c68000 {
 790                         compatible = "allwinner,sun6i-a31-spi";
 791                         reg = <0x01c68000 0x1000>;
 792                         interrupts = <0 65 4>;
 793                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 794                         clock-names = "ahb", "mod";
 795                         dmas = <&dma 23>, <&dma 23>;
 796                         dma-names = "rx", "tx";
 797                         resets = <&ahb1_rst 20>;
 798                         status = "disabled";
 799                 };
 800
 801                 spi1: spi@01c69000 {
 802                         compatible = "allwinner,sun6i-a31-spi";
 803                         reg = <0x01c69000 0x1000>;
 804                         interrupts = <0 66 4>;
 805                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 806                         clock-names = "ahb", "mod";
 807                         dmas = <&dma 24>, <&dma 24>;
 808                         dma-names = "rx", "tx";
 809                         resets = <&ahb1_rst 21>;
 810                         status = "disabled";
 811                 };
 812
 813                 spi2: spi@01c6a000 {
 814                         compatible = "allwinner,sun6i-a31-spi";
 815                         reg = <0x01c6a000 0x1000>;
 816                         interrupts = <0 67 4>;
 817                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 818                         clock-names = "ahb", "mod";
 819                         dmas = <&dma 25>, <&dma 25>;
 820                         dma-names = "rx", "tx";
 821                         resets = <&ahb1_rst 22>;
 822                         status = "disabled";
 823                 };
 824
 825                 spi3: spi@01c6b000 {
 826                         compatible = "allwinner,sun6i-a31-spi";
 827                         reg = <0x01c6b000 0x1000>;
 828                         interrupts = <0 68 4>;
 829                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 830                         clock-names = "ahb", "mod";
 831                         dmas = <&dma 26>, <&dma 26>;
 832                         dma-names = "rx", "tx";
 833                         resets = <&ahb1_rst 23>;
 834                         status = "disabled";
 835                 };
 836
 837                 gic: interrupt-controller@01c81000 {
 838                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 839                         reg = <0x01c81000 0x1000>,
 840                               <0x01c82000 0x1000>,
 841                               <0x01c84000 0x2000>,
 842                               <0x01c86000 0x2000>;
 843                         interrupt-controller;
 844                         #interrupt-cells = <3>;
 845                         interrupts = <1 9 0xf04>;
 846                 };
 847
 848                 rtc: rtc@01f00000 {
 849                         compatible = "allwinner,sun6i-a31-rtc";
 850                         reg = <0x01f00000 0x54>;
 851                         interrupts = <0 40 4>, <0 41 4>;
 852                 };
 853
 854                 nmi_intc: interrupt-controller@01f00c0c {
 855                         compatible = "allwinner,sun6i-a31-sc-nmi";
 856                         interrupt-controller;
 857                         #interrupt-cells = <2>;
 858                         reg = <0x01f00c0c 0x38>;
 859                         interrupts = <0 32 4>;
 860                 };
 861
 862                 prcm@01f01400 {
 863                         compatible = "allwinner,sun6i-a31-prcm";
 864                         reg = <0x01f01400 0x200>;
 865
 866                         ar100: ar100_clk {
 867                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 868                                 #clock-cells = <0>;
 869                                 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 870                                 clock-output-names = "ar100";
 871                         };
 872
 873                         ahb0: ahb0_clk {
 874                                 compatible = "fixed-factor-clock";
 875                                 #clock-cells = <0>;
 876                                 clock-div = <1>;
 877                                 clock-mult = <1>;
 878                                 clocks = <&ar100>;
 879                                 clock-output-names = "ahb0";
 880                         };
 881
 882                         apb0: apb0_clk {
 883                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 884                                 #clock-cells = <0>;
 885                                 clocks = <&ahb0>;
 886                                 clock-output-names = "apb0";
 887                         };
 888
 889                         apb0_gates: apb0_gates_clk {
 890                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 891                                 #clock-cells = <1>;
 892                                 clocks = <&apb0>;
 893                                 clock-output-names = "apb0_pio", "apb0_ir",
 894                                                 "apb0_timer", "apb0_p2wi",
 895                                                 "apb0_uart", "apb0_1wire",
 896                                                 "apb0_i2c";
 897                         };
 898
 899                         apb0_rst: apb0_rst {
 900                                 compatible = "allwinner,sun6i-a31-clock-reset";
 901                                 #reset-cells = <1>;
 902                         };
 903                 };
 904
 905                 cpucfg@01f01c00 {
 906                         compatible = "allwinner,sun6i-a31-cpuconfig";
 907                         reg = <0x01f01c00 0x300>;
 908                 };
 909
 910                 r_pio: pinctrl@01f02c00 {
 911                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 912                         reg = <0x01f02c00 0x400>;
 913                         interrupts = <0 45 4>,
 914                                      <0 46 4>;
 915                         clocks = <&apb0_gates 0>;
 916                         resets = <&apb0_rst 0>;
 917                         gpio-controller;
 918                         interrupt-controller;
 919                         #interrupt-cells = <2>;
 920                         #size-cells = <0>;
 921                         #gpio-cells = <3>;
 922                 };
 923         };
 924 };