arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 simplefb_hdmi: framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  70                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  71                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  72                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 simplefb_lcd: framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  81                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  82                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  83                         status = "disabled";
  84                 };
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93                 clock-frequency = <24000000>;
  94                 arm,cpu-registers-not-fw-configured;
  95         };
  96
  97         cpus {
  98                 enable-method = "allwinner,sun6i-a31";
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 1008000 1200000
 111                                 864000  1200000
 112                                 720000  1100000
 113                                 480000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                 };
 117
 118                 cpu1: cpu@1 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         reg = <1>;
 122                         clocks = <&ccu CLK_CPU>;
 123                         clock-latency = <244144>; /* 8 32k periods */
 124                         operating-points = <
 125                                 /* kHz    uV */
 126                                 1008000 1200000
 127                                 864000  1200000
 128                                 720000  1100000
 129                                 480000  1000000
 130                                 >;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu2: cpu@2 {
 135                         compatible = "arm,cortex-a7";
 136                         device_type = "cpu";
 137                         reg = <2>;
 138                         clocks = <&ccu CLK_CPU>;
 139                         clock-latency = <244144>; /* 8 32k periods */
 140                         operating-points = <
 141                                 /* kHz    uV */
 142                                 1008000 1200000
 143                                 864000  1200000
 144                                 720000  1100000
 145                                 480000  1000000
 146                                 >;
 147                         #cooling-cells = <2>;
 148                 };
 149
 150                 cpu3: cpu@3 {
 151                         compatible = "arm,cortex-a7";
 152                         device_type = "cpu";
 153                         reg = <3>;
 154                         clocks = <&ccu CLK_CPU>;
 155                         clock-latency = <244144>; /* 8 32k periods */
 156                         operating-points = <
 157                                 /* kHz    uV */
 158                                 1008000 1200000
 159                                 864000  1200000
 160                                 720000  1100000
 161                                 480000  1000000
 162                                 >;
 163                         #cooling-cells = <2>;
 164                 };
 165         };
 166
 167         thermal-zones {
 168                 cpu_thermal {
 169                         /* milliseconds */
 170                         polling-delay-passive = <250>;
 171                         polling-delay = <1000>;
 172                         thermal-sensors = <&rtp>;
 173
 174                         cooling-maps {
 175                                 map0 {
 176                                         trip = <&cpu_alert0>;
 177                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 178                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 179                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182                         };
 183
 184                         trips {
 185                                 cpu_alert0: cpu_alert0 {
 186                                         /* milliCelsius */
 187                                         temperature = <70000>;
 188                                         hysteresis = <2000>;
 189                                         type = "passive";
 190                                 };
 191
 192                                 cpu_crit: cpu_crit {
 193                                         /* milliCelsius */
 194                                         temperature = <100000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200         };
 201
 202         pmu {
 203                 compatible = "arm,cortex-a7-pmu";
 204                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 208         };
 209
 210         clocks {
 211                 #address-cells = <1>;
 212                 #size-cells = <1>;
 213                 ranges;
 214
 215                 osc24M: clk-24M {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <24000000>;
 219                 };
 220
 221                 osc32k: clk-32k {
 222                         #clock-cells = <0>;
 223                         compatible = "fixed-clock";
 224                         clock-frequency = <32768>;
 225                         clock-output-names = "osc32k";
 226                 };
 227
 228                 /*
 229                  * The following two are dummy clocks, placeholders
 230                  * used in the gmac_tx clock. The gmac driver will
 231                  * choose one parent depending on the PHY interface
 232                  * mode, using clk_set_rate auto-reparenting.
 233                  *
 234                  * The actual TX clock rate is not controlled by the
 235                  * gmac_tx clock.
 236                  */
 237                 mii_phy_tx_clk: clk-mii-phy-tx {
 238                         #clock-cells = <0>;
 239                         compatible = "fixed-clock";
 240                         clock-frequency = <25000000>;
 241                         clock-output-names = "mii_phy_tx";
 242                 };
 243
 244                 gmac_int_tx_clk: clk-gmac-int-tx {
 245                         #clock-cells = <0>;
 246                         compatible = "fixed-clock";
 247                         clock-frequency = <125000000>;
 248                         clock-output-names = "gmac_int_tx";
 249                 };
 250
 251                 gmac_tx_clk: clk@1c200d0 {
 252                         #clock-cells = <0>;
 253                         compatible = "allwinner,sun7i-a20-gmac-clk";
 254                         reg = <0x01c200d0 0x4>;
 255                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 256                         clock-output-names = "gmac_tx";
 257                 };
 258         };
 259
 260         de: display-engine {
 261                 compatible = "allwinner,sun6i-a31-display-engine";
 262                 allwinner,pipelines = <&fe0>, <&fe1>;
 263                 status = "disabled";
 264         };
 265
 266         soc {
 267                 compatible = "simple-bus";
 268                 #address-cells = <1>;
 269                 #size-cells = <1>;
 270                 ranges;
 271
 272                 dma: dma-controller@1c02000 {
 273                         compatible = "allwinner,sun6i-a31-dma";
 274                         reg = <0x01c02000 0x1000>;
 275                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&ccu CLK_AHB1_DMA>;
 277                         resets = <&ccu RST_AHB1_DMA>;
 278                         #dma-cells = <1>;
 279                 };
 280
 281                 tcon0: lcd-controller@1c0c000 {
 282                         compatible = "allwinner,sun6i-a31-tcon";
 283                         reg = <0x01c0c000 0x1000>;
 284                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 285                         resets = <&ccu RST_AHB1_LCD0>;
 286                         reset-names = "lcd";
 287                         clocks = <&ccu CLK_AHB1_LCD0>,
 288                                  <&ccu CLK_LCD0_CH0>,
 289                                  <&ccu CLK_LCD0_CH1>;
 290                         clock-names = "ahb",
 291                                       "tcon-ch0",
 292                                       "tcon-ch1";
 293                         clock-output-names = "tcon0-pixel-clock";
 294
 295                         ports {
 296                                 #address-cells = <1>;
 297                                 #size-cells = <0>;
 298
 299                                 tcon0_in: port@0 {
 300                                         #address-cells = <1>;
 301                                         #size-cells = <0>;
 302                                         reg = <0>;
 303
 304                                         tcon0_in_drc0: endpoint@0 {
 305                                                 reg = <0>;
 306                                                 remote-endpoint = <&drc0_out_tcon0>;
 307                                         };
 308
 309                                         tcon0_in_drc1: endpoint@1 {
 310                                                 reg = <1>;
 311                                                 remote-endpoint = <&drc1_out_tcon0>;
 312                                         };
 313                                 };
 314
 315                                 tcon0_out: port@1 {
 316                                         #address-cells = <1>;
 317                                         #size-cells = <0>;
 318                                         reg = <1>;
 319
 320                                         tcon0_out_hdmi: endpoint@1 {
 321                                                 reg = <1>;
 322                                                 remote-endpoint = <&hdmi_in_tcon0>;
 323                                                 allwinner,tcon-channel = <1>;
 324                                         };
 325                                 };
 326                         };
 327                 };
 328
 329                 tcon1: lcd-controller@1c0d000 {
 330                         compatible = "allwinner,sun6i-a31-tcon";
 331                         reg = <0x01c0d000 0x1000>;
 332                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 333                         resets = <&ccu RST_AHB1_LCD1>;
 334                         reset-names = "lcd";
 335                         clocks = <&ccu CLK_AHB1_LCD1>,
 336                                  <&ccu CLK_LCD1_CH0>,
 337                                  <&ccu CLK_LCD1_CH1>;
 338                         clock-names = "ahb",
 339                                       "tcon-ch0",
 340                                       "tcon-ch1";
 341                         clock-output-names = "tcon1-pixel-clock";
 342
 343                         ports {
 344                                 #address-cells = <1>;
 345                                 #size-cells = <0>;
 346
 347                                 tcon1_in: port@0 {
 348                                         #address-cells = <1>;
 349                                         #size-cells = <0>;
 350                                         reg = <0>;
 351
 352                                         tcon1_in_drc0: endpoint@0 {
 353                                                 reg = <0>;
 354                                                 remote-endpoint = <&drc0_out_tcon1>;
 355                                         };
 356
 357                                         tcon1_in_drc1: endpoint@1 {
 358                                                 reg = <1>;
 359                                                 remote-endpoint = <&drc1_out_tcon1>;
 360                                         };
 361                                 };
 362
 363                                 tcon1_out: port@1 {
 364                                         #address-cells = <1>;
 365                                         #size-cells = <0>;
 366                                         reg = <1>;
 367
 368                                         tcon1_out_hdmi: endpoint@1 {
 369                                                 reg = <1>;
 370                                                 remote-endpoint = <&hdmi_in_tcon1>;
 371                                                 allwinner,tcon-channel = <1>;
 372                                         };
 373                                 };
 374                         };
 375                 };
 376
 377                 mmc0: mmc@1c0f000 {
 378                         compatible = "allwinner,sun7i-a20-mmc";
 379                         reg = <0x01c0f000 0x1000>;
 380                         clocks = <&ccu CLK_AHB1_MMC0>,
 381                                  <&ccu CLK_MMC0>,
 382                                  <&ccu CLK_MMC0_OUTPUT>,
 383                                  <&ccu CLK_MMC0_SAMPLE>;
 384                         clock-names = "ahb",
 385                                       "mmc",
 386                                       "output",
 387                                       "sample";
 388                         resets = <&ccu RST_AHB1_MMC0>;
 389                         reset-names = "ahb";
 390                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                         pinctrl-names = "default";
 392                         pinctrl-0 = <&mmc0_pins>;
 393                         status = "disabled";
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                 };
 397
 398                 mmc1: mmc@1c10000 {
 399                         compatible = "allwinner,sun7i-a20-mmc";
 400                         reg = <0x01c10000 0x1000>;
 401                         clocks = <&ccu CLK_AHB1_MMC1>,
 402                                  <&ccu CLK_MMC1>,
 403                                  <&ccu CLK_MMC1_OUTPUT>,
 404                                  <&ccu CLK_MMC1_SAMPLE>;
 405                         clock-names = "ahb",
 406                                       "mmc",
 407                                       "output",
 408                                       "sample";
 409                         resets = <&ccu RST_AHB1_MMC1>;
 410                         reset-names = "ahb";
 411                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 412                         pinctrl-names = "default";
 413                         pinctrl-0 = <&mmc1_pins>;
 414                         status = "disabled";
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                 };
 418
 419                 mmc2: mmc@1c11000 {
 420                         compatible = "allwinner,sun7i-a20-mmc";
 421                         reg = <0x01c11000 0x1000>;
 422                         clocks = <&ccu CLK_AHB1_MMC2>,
 423                                  <&ccu CLK_MMC2>,
 424                                  <&ccu CLK_MMC2_OUTPUT>,
 425                                  <&ccu CLK_MMC2_SAMPLE>;
 426                         clock-names = "ahb",
 427                                       "mmc",
 428                                       "output",
 429                                       "sample";
 430                         resets = <&ccu RST_AHB1_MMC2>;
 431                         reset-names = "ahb";
 432                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 433                         status = "disabled";
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                 };
 437
 438                 mmc3: mmc@1c12000 {
 439                         compatible = "allwinner,sun7i-a20-mmc";
 440                         reg = <0x01c12000 0x1000>;
 441                         clocks = <&ccu CLK_AHB1_MMC3>,
 442                                  <&ccu CLK_MMC3>,
 443                                  <&ccu CLK_MMC3_OUTPUT>,
 444                                  <&ccu CLK_MMC3_SAMPLE>;
 445                         clock-names = "ahb",
 446                                       "mmc",
 447                                       "output",
 448                                       "sample";
 449                         resets = <&ccu RST_AHB1_MMC3>;
 450                         reset-names = "ahb";
 451                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 452                         status = "disabled";
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                 };
 456
 457                 hdmi: hdmi@1c16000 {
 458                         compatible = "allwinner,sun6i-a31-hdmi";
 459                         reg = <0x01c16000 0x1000>;
 460                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
 462                                  <&ccu CLK_HDMI_DDC>,
 463                                  <&ccu CLK_PLL_VIDEO0_2X>,
 464                                  <&ccu CLK_PLL_VIDEO1_2X>;
 465                         clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
 466                         resets = <&ccu RST_AHB1_HDMI>;
 467                         reset-names = "ahb";
 468                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 469                         dmas = <&dma 13>, <&dma 13>, <&dma 14>;
 470                         status = "disabled";
 471
 472                         ports {
 473                                 #address-cells = <1>;
 474                                 #size-cells = <0>;
 475
 476                                 hdmi_in: port@0 {
 477                                         #address-cells = <1>;
 478                                         #size-cells = <0>;
 479                                         reg = <0>;
 480
 481                                         hdmi_in_tcon0: endpoint@0 {
 482                                                 reg = <0>;
 483                                                 remote-endpoint = <&tcon0_out_hdmi>;
 484                                         };
 485
 486                                         hdmi_in_tcon1: endpoint@1 {
 487                                                 reg = <1>;
 488                                                 remote-endpoint = <&tcon1_out_hdmi>;
 489                                         };
 490                                 };
 491
 492                                 hdmi_out: port@1 {
 493                                         #address-cells = <1>;
 494                                         #size-cells = <0>;
 495                                         reg = <1>;
 496                                 };
 497                         };
 498                 };
 499
 500                 usb_otg: usb@1c19000 {
 501                         compatible = "allwinner,sun6i-a31-musb";
 502                         reg = <0x01c19000 0x0400>;
 503                         clocks = <&ccu CLK_AHB1_OTG>;
 504                         resets = <&ccu RST_AHB1_OTG>;
 505                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 506                         interrupt-names = "mc";
 507                         phys = <&usbphy 0>;
 508                         phy-names = "usb";
 509                         extcon = <&usbphy 0>;
 510                         status = "disabled";
 511                 };
 512
 513                 usbphy: phy@1c19400 {
 514                         compatible = "allwinner,sun6i-a31-usb-phy";
 515                         reg = <0x01c19400 0x10>,
 516                               <0x01c1a800 0x4>,
 517                               <0x01c1b800 0x4>;
 518                         reg-names = "phy_ctrl",
 519                                     "pmu1",
 520                                     "pmu2";
 521                         clocks = <&ccu CLK_USB_PHY0>,
 522                                  <&ccu CLK_USB_PHY1>,
 523                                  <&ccu CLK_USB_PHY2>;
 524                         clock-names = "usb0_phy",
 525                                       "usb1_phy",
 526                                       "usb2_phy";
 527                         resets = <&ccu RST_USB_PHY0>,
 528                                  <&ccu RST_USB_PHY1>,
 529                                  <&ccu RST_USB_PHY2>;
 530                         reset-names = "usb0_reset",
 531                                       "usb1_reset",
 532                                       "usb2_reset";
 533                         status = "disabled";
 534                         #phy-cells = <1>;
 535                 };
 536
 537                 ehci0: usb@1c1a000 {
 538                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 539                         reg = <0x01c1a000 0x100>;
 540                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&ccu CLK_AHB1_EHCI0>;
 542                         resets = <&ccu RST_AHB1_EHCI0>;
 543                         phys = <&usbphy 1>;
 544                         phy-names = "usb";
 545                         status = "disabled";
 546                 };
 547
 548                 ohci0: usb@1c1a400 {
 549                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 550                         reg = <0x01c1a400 0x100>;
 551                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 553                         resets = <&ccu RST_AHB1_OHCI0>;
 554                         phys = <&usbphy 1>;
 555                         phy-names = "usb";
 556                         status = "disabled";
 557                 };
 558
 559                 ehci1: usb@1c1b000 {
 560                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 561                         reg = <0x01c1b000 0x100>;
 562                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&ccu CLK_AHB1_EHCI1>;
 564                         resets = <&ccu RST_AHB1_EHCI1>;
 565                         phys = <&usbphy 2>;
 566                         phy-names = "usb";
 567                         status = "disabled";
 568                 };
 569
 570                 ohci1: usb@1c1b400 {
 571                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 572                         reg = <0x01c1b400 0x100>;
 573                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 575                         resets = <&ccu RST_AHB1_OHCI1>;
 576                         phys = <&usbphy 2>;
 577                         phy-names = "usb";
 578                         status = "disabled";
 579                 };
 580
 581                 ohci2: usb@1c1c400 {
 582                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 583                         reg = <0x01c1c400 0x100>;
 584                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 585                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 586                         resets = <&ccu RST_AHB1_OHCI2>;
 587                         status = "disabled";
 588                 };
 589
 590                 ccu: clock@1c20000 {
 591                         compatible = "allwinner,sun6i-a31-ccu";
 592                         reg = <0x01c20000 0x400>;
 593                         clocks = <&osc24M>, <&osc32k>;
 594                         clock-names = "hosc", "losc";
 595                         #clock-cells = <1>;
 596                         #reset-cells = <1>;
 597                 };
 598
 599                 pio: pinctrl@1c20800 {
 600                         compatible = "allwinner,sun6i-a31-pinctrl";
 601                         reg = <0x01c20800 0x400>;
 602                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 604                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 605                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
 607                         clock-names = "apb", "hosc", "losc";
 608                         gpio-controller;
 609                         interrupt-controller;
 610                         #interrupt-cells = <3>;
 611                         #gpio-cells = <3>;
 612
 613                         gmac_gmii_pins: gmac-gmii-pins {
 614                                 pins = "PA0", "PA1", "PA2", "PA3",
 615                                                 "PA4", "PA5", "PA6", "PA7",
 616                                                 "PA8", "PA9", "PA10", "PA11",
 617                                                 "PA12", "PA13", "PA14", "PA15",
 618                                                 "PA16", "PA17", "PA18", "PA19",
 619                                                 "PA20", "PA21", "PA22", "PA23",
 620                                                 "PA24", "PA25", "PA26", "PA27";
 621                                 function = "gmac";
 622                                 /*
 623                                  * data lines in GMII mode run at 125MHz and
 624                                  * might need a higher signal drive strength
 625                                  */
 626                                 drive-strength = <30>;
 627                         };
 628
 629                         gmac_mii_pins: gmac-mii-pins {
 630                                 pins = "PA0", "PA1", "PA2", "PA3",
 631                                                 "PA8", "PA9", "PA11",
 632                                                 "PA12", "PA13", "PA14", "PA19",
 633                                                 "PA20", "PA21", "PA22", "PA23",
 634                                                 "PA24", "PA26", "PA27";
 635                                 function = "gmac";
 636                         };
 637
 638                         gmac_rgmii_pins: gmac-rgmii-pins {
 639                                 pins = "PA0", "PA1", "PA2", "PA3",
 640                                                 "PA9", "PA10", "PA11",
 641                                                 "PA12", "PA13", "PA14", "PA19",
 642                                                 "PA20", "PA25", "PA26", "PA27";
 643                                 function = "gmac";
 644                                 /*
 645                                  * data lines in RGMII mode use DDR mode
 646                                  * and need a higher signal drive strength
 647                                  */
 648                                 drive-strength = <40>;
 649                         };
 650
 651                         i2c0_pins: i2c0-pins {
 652                                 pins = "PH14", "PH15";
 653                                 function = "i2c0";
 654                         };
 655
 656                         i2c1_pins: i2c1-pins {
 657                                 pins = "PH16", "PH17";
 658                                 function = "i2c1";
 659                         };
 660
 661                         i2c2_pins: i2c2-pins {
 662                                 pins = "PH18", "PH19";
 663                                 function = "i2c2";
 664                         };
 665
 666                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 667                                 pins = "PD0", "PD1", "PD2", "PD3",
 668                                                  "PD4", "PD5", "PD6", "PD7",
 669                                                  "PD8", "PD9", "PD10", "PD11",
 670                                                  "PD12", "PD13", "PD14", "PD15",
 671                                                  "PD16", "PD17", "PD18", "PD19",
 672                                                  "PD20", "PD21", "PD22", "PD23",
 673                                                  "PD24", "PD25", "PD26", "PD27";
 674                                 function = "lcd0";
 675                         };
 676
 677                         mmc0_pins: mmc0-pins {
 678                                 pins = "PF0", "PF1", "PF2",
 679                                                  "PF3", "PF4", "PF5";
 680                                 function = "mmc0";
 681                                 drive-strength = <30>;
 682                                 bias-pull-up;
 683                         };
 684
 685                         mmc1_pins: mmc1-pins {
 686                                 pins = "PG0", "PG1", "PG2", "PG3",
 687                                                  "PG4", "PG5";
 688                                 function = "mmc1";
 689                                 drive-strength = <30>;
 690                                 bias-pull-up;
 691                         };
 692
 693                         mmc2_4bit_pins: mmc2-4bit-pins {
 694                                 pins = "PC6", "PC7", "PC8", "PC9",
 695                                                  "PC10", "PC11";
 696                                 function = "mmc2";
 697                                 drive-strength = <30>;
 698                                 bias-pull-up;
 699                         };
 700
 701                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 702                                 pins = "PC6", "PC7", "PC8", "PC9",
 703                                                  "PC10", "PC11", "PC12",
 704                                                  "PC13", "PC14", "PC15",
 705                                                  "PC24";
 706                                 function = "mmc2";
 707                                 drive-strength = <30>;
 708                                 bias-pull-up;
 709                         };
 710
 711                         mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
 712                                 pins = "PC6", "PC7", "PC8", "PC9",
 713                                                  "PC10", "PC11", "PC12",
 714                                                  "PC13", "PC14", "PC15",
 715                                                  "PC24";
 716                                 function = "mmc3";
 717                                 drive-strength = <40>;
 718                                 bias-pull-up;
 719                         };
 720
 721                         spdif_tx_pin: spdif-tx-pin {
 722                                 pins = "PH28";
 723                                 function = "spdif";
 724                         };
 725
 726                         uart0_ph_pins: uart0-ph-pins {
 727                                 pins = "PH20", "PH21";
 728                                 function = "uart0";
 729                         };
 730                 };
 731
 732                 timer@1c20c00 {
 733                         compatible = "allwinner,sun4i-a10-timer";
 734                         reg = <0x01c20c00 0xa0>;
 735                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 740                         clocks = <&osc24M>;
 741                 };
 742
 743                 wdt1: watchdog@1c20ca0 {
 744                         compatible = "allwinner,sun6i-a31-wdt";
 745                         reg = <0x01c20ca0 0x20>;
 746                 };
 747
 748                 spdif: spdif@1c21000 {
 749                         #sound-dai-cells = <0>;
 750                         compatible = "allwinner,sun6i-a31-spdif";
 751                         reg = <0x01c21000 0x400>;
 752                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 753                         clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
 754                         resets = <&ccu RST_APB1_SPDIF>;
 755                         clock-names = "apb", "spdif";
 756                         dmas = <&dma 2>, <&dma 2>;
 757                         dma-names = "rx", "tx";
 758                         status = "disabled";
 759                 };
 760
 761                 i2s0: i2s@1c22000 {
 762                         #sound-dai-cells = <0>;
 763                         compatible = "allwinner,sun6i-a31-i2s";
 764                         reg = <0x01c22000 0x400>;
 765                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 766                         clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
 767                         resets = <&ccu RST_APB1_DAUDIO0>;
 768                         clock-names = "apb", "mod";
 769                         dmas = <&dma 3>, <&dma 3>;
 770                         dma-names = "rx", "tx";
 771                         status = "disabled";
 772                 };
 773
 774                 i2s1: i2s@1c22400 {
 775                         #sound-dai-cells = <0>;
 776                         compatible = "allwinner,sun6i-a31-i2s";
 777                         reg = <0x01c22400 0x400>;
 778                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
 780                         resets = <&ccu RST_APB1_DAUDIO1>;
 781                         clock-names = "apb", "mod";
 782                         dmas = <&dma 4>, <&dma 4>;
 783                         dma-names = "rx", "tx";
 784                         status = "disabled";
 785                 };
 786
 787                 lradc: lradc@1c22800 {
 788                         compatible = "allwinner,sun4i-a10-lradc-keys";
 789                         reg = <0x01c22800 0x100>;
 790                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 791                         status = "disabled";
 792                 };
 793
 794                 rtp: rtp@1c25000 {
 795                         compatible = "allwinner,sun6i-a31-ts";
 796                         reg = <0x01c25000 0x100>;
 797                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 798                         #thermal-sensor-cells = <0>;
 799                 };
 800
 801                 uart0: serial@1c28000 {
 802                         compatible = "snps,dw-apb-uart";
 803                         reg = <0x01c28000 0x400>;
 804                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 805                         reg-shift = <2>;
 806                         reg-io-width = <4>;
 807                         clocks = <&ccu CLK_APB2_UART0>;
 808                         resets = <&ccu RST_APB2_UART0>;
 809                         dmas = <&dma 6>, <&dma 6>;
 810                         dma-names = "rx", "tx";
 811                         status = "disabled";
 812                 };
 813
 814                 uart1: serial@1c28400 {
 815                         compatible = "snps,dw-apb-uart";
 816                         reg = <0x01c28400 0x400>;
 817                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 818                         reg-shift = <2>;
 819                         reg-io-width = <4>;
 820                         clocks = <&ccu CLK_APB2_UART1>;
 821                         resets = <&ccu RST_APB2_UART1>;
 822                         dmas = <&dma 7>, <&dma 7>;
 823                         dma-names = "rx", "tx";
 824                         status = "disabled";
 825                 };
 826
 827                 uart2: serial@1c28800 {
 828                         compatible = "snps,dw-apb-uart";
 829                         reg = <0x01c28800 0x400>;
 830                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 831                         reg-shift = <2>;
 832                         reg-io-width = <4>;
 833                         clocks = <&ccu CLK_APB2_UART2>;
 834                         resets = <&ccu RST_APB2_UART2>;
 835                         dmas = <&dma 8>, <&dma 8>;
 836                         dma-names = "rx", "tx";
 837                         status = "disabled";
 838                 };
 839
 840                 uart3: serial@1c28c00 {
 841                         compatible = "snps,dw-apb-uart";
 842                         reg = <0x01c28c00 0x400>;
 843                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 844                         reg-shift = <2>;
 845                         reg-io-width = <4>;
 846                         clocks = <&ccu CLK_APB2_UART3>;
 847                         resets = <&ccu RST_APB2_UART3>;
 848                         dmas = <&dma 9>, <&dma 9>;
 849                         dma-names = "rx", "tx";
 850                         status = "disabled";
 851                 };
 852
 853                 uart4: serial@1c29000 {
 854                         compatible = "snps,dw-apb-uart";
 855                         reg = <0x01c29000 0x400>;
 856                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 857                         reg-shift = <2>;
 858                         reg-io-width = <4>;
 859                         clocks = <&ccu CLK_APB2_UART4>;
 860                         resets = <&ccu RST_APB2_UART4>;
 861                         dmas = <&dma 10>, <&dma 10>;
 862                         dma-names = "rx", "tx";
 863                         status = "disabled";
 864                 };
 865
 866                 uart5: serial@1c29400 {
 867                         compatible = "snps,dw-apb-uart";
 868                         reg = <0x01c29400 0x400>;
 869                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 870                         reg-shift = <2>;
 871                         reg-io-width = <4>;
 872                         clocks = <&ccu CLK_APB2_UART5>;
 873                         resets = <&ccu RST_APB2_UART5>;
 874                         dmas = <&dma 22>, <&dma 22>;
 875                         dma-names = "rx", "tx";
 876                         status = "disabled";
 877                 };
 878
 879                 i2c0: i2c@1c2ac00 {
 880                         compatible = "allwinner,sun6i-a31-i2c";
 881                         reg = <0x01c2ac00 0x400>;
 882                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 883                         clocks = <&ccu CLK_APB2_I2C0>;
 884                         resets = <&ccu RST_APB2_I2C0>;
 885                         pinctrl-names = "default";
 886                         pinctrl-0 = <&i2c0_pins>;
 887                         status = "disabled";
 888                         #address-cells = <1>;
 889                         #size-cells = <0>;
 890                 };
 891
 892                 i2c1: i2c@1c2b000 {
 893                         compatible = "allwinner,sun6i-a31-i2c";
 894                         reg = <0x01c2b000 0x400>;
 895                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&ccu CLK_APB2_I2C1>;
 897                         resets = <&ccu RST_APB2_I2C1>;
 898                         pinctrl-names = "default";
 899                         pinctrl-0 = <&i2c1_pins>;
 900                         status = "disabled";
 901                         #address-cells = <1>;
 902                         #size-cells = <0>;
 903                 };
 904
 905                 i2c2: i2c@1c2b400 {
 906                         compatible = "allwinner,sun6i-a31-i2c";
 907                         reg = <0x01c2b400 0x400>;
 908                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 909                         clocks = <&ccu CLK_APB2_I2C2>;
 910                         resets = <&ccu RST_APB2_I2C2>;
 911                         pinctrl-names = "default";
 912                         pinctrl-0 = <&i2c2_pins>;
 913                         status = "disabled";
 914                         #address-cells = <1>;
 915                         #size-cells = <0>;
 916                 };
 917
 918                 i2c3: i2c@1c2b800 {
 919                         compatible = "allwinner,sun6i-a31-i2c";
 920                         reg = <0x01c2b800 0x400>;
 921                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 922                         clocks = <&ccu CLK_APB2_I2C3>;
 923                         resets = <&ccu RST_APB2_I2C3>;
 924                         status = "disabled";
 925                         #address-cells = <1>;
 926                         #size-cells = <0>;
 927                 };
 928
 929                 gmac: ethernet@1c30000 {
 930                         compatible = "allwinner,sun7i-a20-gmac";
 931                         reg = <0x01c30000 0x1054>;
 932                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 933                         interrupt-names = "macirq";
 934                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 935                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 936                         resets = <&ccu RST_AHB1_EMAC>;
 937                         reset-names = "stmmaceth";
 938                         snps,pbl = <2>;
 939                         snps,fixed-burst;
 940                         snps,force_sf_dma_mode;
 941                         status = "disabled";
 942                         #address-cells = <1>;
 943                         #size-cells = <0>;
 944                 };
 945
 946                 crypto: crypto-engine@1c15000 {
 947                         compatible = "allwinner,sun6i-a31-crypto",
 948                                      "allwinner,sun4i-a10-crypto";
 949                         reg = <0x01c15000 0x1000>;
 950                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 951                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 952                         clock-names = "ahb", "mod";
 953                         resets = <&ccu RST_AHB1_SS>;
 954                         reset-names = "ahb";
 955                 };
 956
 957                 codec: codec@1c22c00 {
 958                         #sound-dai-cells = <0>;
 959                         compatible = "allwinner,sun6i-a31-codec";
 960                         reg = <0x01c22c00 0x400>;
 961                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 962                         clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
 963                         clock-names = "apb", "codec";
 964                         resets = <&ccu RST_APB1_CODEC>;
 965                         dmas = <&dma 15>, <&dma 15>;
 966                         dma-names = "rx", "tx";
 967                         status = "disabled";
 968                 };
 969
 970                 timer@1c60000 {
 971                         compatible = "allwinner,sun6i-a31-hstimer",
 972                                      "allwinner,sun7i-a20-hstimer";
 973                         reg = <0x01c60000 0x1000>;
 974                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 975                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 976                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 977                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 978                         clocks = <&ccu CLK_AHB1_HSTIMER>;
 979                         resets = <&ccu RST_AHB1_HSTIMER>;
 980                 };
 981
 982                 spi0: spi@1c68000 {
 983                         compatible = "allwinner,sun6i-a31-spi";
 984                         reg = <0x01c68000 0x1000>;
 985                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 986                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
 987                         clock-names = "ahb", "mod";
 988                         dmas = <&dma 23>, <&dma 23>;
 989                         dma-names = "rx", "tx";
 990                         resets = <&ccu RST_AHB1_SPI0>;
 991                         status = "disabled";
 992                 };
 993
 994                 spi1: spi@1c69000 {
 995                         compatible = "allwinner,sun6i-a31-spi";
 996                         reg = <0x01c69000 0x1000>;
 997                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
 999                         clock-names = "ahb", "mod";
1000                         dmas = <&dma 24>, <&dma 24>;
1001                         dma-names = "rx", "tx";
1002                         resets = <&ccu RST_AHB1_SPI1>;
1003                         status = "disabled";
1004                 };
1005
1006                 spi2: spi@1c6a000 {
1007                         compatible = "allwinner,sun6i-a31-spi";
1008                         reg = <0x01c6a000 0x1000>;
1009                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1010                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1011                         clock-names = "ahb", "mod";
1012                         dmas = <&dma 25>, <&dma 25>;
1013                         dma-names = "rx", "tx";
1014                         resets = <&ccu RST_AHB1_SPI2>;
1015                         status = "disabled";
1016                 };
1017
1018                 spi3: spi@1c6b000 {
1019                         compatible = "allwinner,sun6i-a31-spi";
1020                         reg = <0x01c6b000 0x1000>;
1021                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1022                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1023                         clock-names = "ahb", "mod";
1024                         dmas = <&dma 26>, <&dma 26>;
1025                         dma-names = "rx", "tx";
1026                         resets = <&ccu RST_AHB1_SPI3>;
1027                         status = "disabled";
1028                 };
1029
1030                 gic: interrupt-controller@1c81000 {
1031                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1032                         reg = <0x01c81000 0x1000>,
1033                               <0x01c82000 0x2000>,
1034                               <0x01c84000 0x2000>,
1035                               <0x01c86000 0x2000>;
1036                         interrupt-controller;
1037                         #interrupt-cells = <3>;
1038                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1039                 };
1040
1041                 fe0: display-frontend@1e00000 {
1042                         compatible = "allwinner,sun6i-a31-display-frontend";
1043                         reg = <0x01e00000 0x20000>;
1044                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1045                         clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1046                                  <&ccu CLK_DRAM_FE0>;
1047                         clock-names = "ahb", "mod",
1048                                       "ram";
1049                         resets = <&ccu RST_AHB1_FE0>;
1050
1051                         ports {
1052                                 #address-cells = <1>;
1053                                 #size-cells = <0>;
1054
1055                                 fe0_out: port@1 {
1056                                         #address-cells = <1>;
1057                                         #size-cells = <0>;
1058                                         reg = <1>;
1059
1060                                         fe0_out_be0: endpoint@0 {
1061                                                 reg = <0>;
1062                                                 remote-endpoint = <&be0_in_fe0>;
1063                                         };
1064
1065                                         fe0_out_be1: endpoint@1 {
1066                                                 reg = <1>;
1067                                                 remote-endpoint = <&be1_in_fe0>;
1068                                         };
1069                                 };
1070                         };
1071                 };
1072
1073                 fe1: display-frontend@1e20000 {
1074                         compatible = "allwinner,sun6i-a31-display-frontend";
1075                         reg = <0x01e20000 0x20000>;
1076                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1077                         clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1078                                  <&ccu CLK_DRAM_FE1>;
1079                         clock-names = "ahb", "mod",
1080                                       "ram";
1081                         resets = <&ccu RST_AHB1_FE1>;
1082
1083                         ports {
1084                                 #address-cells = <1>;
1085                                 #size-cells = <0>;
1086
1087                                 fe1_out: port@1 {
1088                                         #address-cells = <1>;
1089                                         #size-cells = <0>;
1090                                         reg = <1>;
1091
1092                                         fe1_out_be0: endpoint@0 {
1093                                                 reg = <0>;
1094                                                 remote-endpoint = <&be0_in_fe1>;
1095                                         };
1096
1097                                         fe1_out_be1: endpoint@1 {
1098                                                 reg = <1>;
1099                                                 remote-endpoint = <&be1_in_fe1>;
1100                                         };
1101                                 };
1102                         };
1103                 };
1104
1105                 be1: display-backend@1e40000 {
1106                         compatible = "allwinner,sun6i-a31-display-backend";
1107                         reg = <0x01e40000 0x10000>;
1108                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1109                         clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1110                                  <&ccu CLK_DRAM_BE1>;
1111                         clock-names = "ahb", "mod",
1112                                       "ram";
1113                         resets = <&ccu RST_AHB1_BE1>;
1114
1115                         assigned-clocks = <&ccu CLK_BE1>;
1116                         assigned-clock-rates = <300000000>;
1117
1118                         ports {
1119                                 #address-cells = <1>;
1120                                 #size-cells = <0>;
1121
1122                                 be1_in: port@0 {
1123                                         #address-cells = <1>;
1124                                         #size-cells = <0>;
1125                                         reg = <0>;
1126
1127                                         be1_in_fe0: endpoint@0 {
1128                                                 reg = <0>;
1129                                                 remote-endpoint = <&fe0_out_be1>;
1130                                         };
1131
1132                                         be1_in_fe1: endpoint@1 {
1133                                                 reg = <1>;
1134                                                 remote-endpoint = <&fe1_out_be1>;
1135                                         };
1136                                 };
1137
1138                                 be1_out: port@1 {
1139                                         #address-cells = <1>;
1140                                         #size-cells = <0>;
1141                                         reg = <1>;
1142
1143                                         be1_out_drc1: endpoint@1 {
1144                                                 reg = <1>;
1145                                                 remote-endpoint = <&drc1_in_be1>;
1146                                         };
1147                                 };
1148                         };
1149                 };
1150
1151                 drc1: drc@1e50000 {
1152                         compatible = "allwinner,sun6i-a31-drc";
1153                         reg = <0x01e50000 0x10000>;
1154                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1155                         clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1156                                  <&ccu CLK_DRAM_DRC1>;
1157                         clock-names = "ahb", "mod",
1158                                       "ram";
1159                         resets = <&ccu RST_AHB1_DRC1>;
1160
1161                         assigned-clocks = <&ccu CLK_IEP_DRC1>;
1162                         assigned-clock-rates = <300000000>;
1163
1164                         ports {
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167
1168                                 drc1_in: port@0 {
1169                                         #address-cells = <1>;
1170                                         #size-cells = <0>;
1171                                         reg = <0>;
1172
1173                                         drc1_in_be1: endpoint@1 {
1174                                                 reg = <1>;
1175                                                 remote-endpoint = <&be1_out_drc1>;
1176                                         };
1177                                 };
1178
1179                                 drc1_out: port@1 {
1180                                         #address-cells = <1>;
1181                                         #size-cells = <0>;
1182                                         reg = <1>;
1183
1184                                         drc1_out_tcon0: endpoint@0 {
1185                                                 reg = <0>;
1186                                                 remote-endpoint = <&tcon0_in_drc1>;
1187                                         };
1188
1189                                         drc1_out_tcon1: endpoint@1 {
1190                                                 reg = <1>;
1191                                                 remote-endpoint = <&tcon1_in_drc1>;
1192                                         };
1193                                 };
1194                         };
1195                 };
1196
1197                 be0: display-backend@1e60000 {
1198                         compatible = "allwinner,sun6i-a31-display-backend";
1199                         reg = <0x01e60000 0x10000>;
1200                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1201                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1202                                  <&ccu CLK_DRAM_BE0>;
1203                         clock-names = "ahb", "mod",
1204                                       "ram";
1205                         resets = <&ccu RST_AHB1_BE0>;
1206
1207                         assigned-clocks = <&ccu CLK_BE0>;
1208                         assigned-clock-rates = <300000000>;
1209
1210                         ports {
1211                                 #address-cells = <1>;
1212                                 #size-cells = <0>;
1213
1214                                 be0_in: port@0 {
1215                                         #address-cells = <1>;
1216                                         #size-cells = <0>;
1217                                         reg = <0>;
1218
1219                                         be0_in_fe0: endpoint@0 {
1220                                                 reg = <0>;
1221                                                 remote-endpoint = <&fe0_out_be0>;
1222                                         };
1223
1224                                         be0_in_fe1: endpoint@1 {
1225                                                 reg = <1>;
1226                                                 remote-endpoint = <&fe1_out_be0>;
1227                                         };
1228                                 };
1229
1230                                 be0_out: port@1 {
1231                                         #address-cells = <1>;
1232                                         #size-cells = <0>;
1233                                         reg = <1>;
1234
1235                                         be0_out_drc0: endpoint@0 {
1236                                                 reg = <0>;
1237                                                 remote-endpoint = <&drc0_in_be0>;
1238                                         };
1239                                 };
1240                         };
1241                 };
1242
1243                 drc0: drc@1e70000 {
1244                         compatible = "allwinner,sun6i-a31-drc";
1245                         reg = <0x01e70000 0x10000>;
1246                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1247                         clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1248                                  <&ccu CLK_DRAM_DRC0>;
1249                         clock-names = "ahb", "mod",
1250                                       "ram";
1251                         resets = <&ccu RST_AHB1_DRC0>;
1252
1253                         assigned-clocks = <&ccu CLK_IEP_DRC0>;
1254                         assigned-clock-rates = <300000000>;
1255
1256                         ports {
1257                                 #address-cells = <1>;
1258                                 #size-cells = <0>;
1259
1260                                 drc0_in: port@0 {
1261                                         #address-cells = <1>;
1262                                         #size-cells = <0>;
1263                                         reg = <0>;
1264
1265                                         drc0_in_be0: endpoint@0 {
1266                                                 reg = <0>;
1267                                                 remote-endpoint = <&be0_out_drc0>;
1268                                         };
1269                                 };
1270
1271                                 drc0_out: port@1 {
1272                                         #address-cells = <1>;
1273                                         #size-cells = <0>;
1274                                         reg = <1>;
1275
1276                                         drc0_out_tcon0: endpoint@0 {
1277                                                 reg = <0>;
1278                                                 remote-endpoint = <&tcon0_in_drc0>;
1279                                         };
1280
1281                                         drc0_out_tcon1: endpoint@1 {
1282                                                 reg = <1>;
1283                                                 remote-endpoint = <&tcon1_in_drc0>;
1284                                         };
1285                                 };
1286                         };
1287                 };
1288
1289                 rtc: rtc@1f00000 {
1290                         compatible = "allwinner,sun6i-a31-rtc";
1291                         reg = <0x01f00000 0x54>;
1292                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1293                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1294                 };
1295
1296                 nmi_intc: interrupt-controller@1f00c00 {
1297                         compatible = "allwinner,sun6i-a31-r-intc";
1298                         interrupt-controller;
1299                         #interrupt-cells = <2>;
1300                         reg = <0x01f00c00 0x400>;
1301                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1302                 };
1303
1304                 prcm@1f01400 {
1305                         compatible = "allwinner,sun6i-a31-prcm";
1306                         reg = <0x01f01400 0x200>;
1307
1308                         ar100: ar100_clk {
1309                                 compatible = "allwinner,sun6i-a31-ar100-clk";
1310                                 #clock-cells = <0>;
1311                                 clocks = <&osc32k>, <&osc24M>,
1312                                          <&ccu CLK_PLL_PERIPH>,
1313                                          <&ccu CLK_PLL_PERIPH>;
1314                                 clock-output-names = "ar100";
1315                         };
1316
1317                         ahb0: ahb0_clk {
1318                                 compatible = "fixed-factor-clock";
1319                                 #clock-cells = <0>;
1320                                 clock-div = <1>;
1321                                 clock-mult = <1>;
1322                                 clocks = <&ar100>;
1323                                 clock-output-names = "ahb0";
1324                         };
1325
1326                         apb0: apb0_clk {
1327                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1328                                 #clock-cells = <0>;
1329                                 clocks = <&ahb0>;
1330                                 clock-output-names = "apb0";
1331                         };
1332
1333                         apb0_gates: apb0_gates_clk {
1334                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1335                                 #clock-cells = <1>;
1336                                 clocks = <&apb0>;
1337                                 clock-output-names = "apb0_pio", "apb0_ir",
1338                                                 "apb0_timer", "apb0_p2wi",
1339                                                 "apb0_uart", "apb0_1wire",
1340                                                 "apb0_i2c";
1341                         };
1342
1343                         ir_clk: ir_clk {
1344                                 #clock-cells = <0>;
1345                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1346                                 clocks = <&osc32k>, <&osc24M>;
1347                                 clock-output-names = "ir";
1348                         };
1349
1350                         apb0_rst: apb0_rst {
1351                                 compatible = "allwinner,sun6i-a31-clock-reset";
1352                                 #reset-cells = <1>;
1353                         };
1354                 };
1355
1356                 cpucfg@1f01c00 {
1357                         compatible = "allwinner,sun6i-a31-cpuconfig";
1358                         reg = <0x01f01c00 0x300>;
1359                 };
1360
1361                 ir: ir@1f02000 {
1362                         compatible = "allwinner,sun5i-a13-ir";
1363                         clocks = <&apb0_gates 1>, <&ir_clk>;
1364                         clock-names = "apb", "ir";
1365                         resets = <&apb0_rst 1>;
1366                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1367                         reg = <0x01f02000 0x40>;
1368                         status = "disabled";
1369                 };
1370
1371                 r_pio: pinctrl@1f02c00 {
1372                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1373                         reg = <0x01f02c00 0x400>;
1374                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1375                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1376                         clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1377                         clock-names = "apb", "hosc", "losc";
1378                         resets = <&apb0_rst 0>;
1379                         gpio-controller;
1380                         interrupt-controller;
1381                         #interrupt-cells = <3>;
1382                         #size-cells = <0>;
1383                         #gpio-cells = <3>;
1384
1385                         s_ir_rx_pin: s-ir-rx-pin {
1386                                 pins = "PL4";
1387                                 function = "s_ir";
1388                         };
1389
1390                         s_p2wi_pins: s-p2wi-pins {
1391                                 pins = "PL0", "PL1";
1392                                 function = "s_p2wi";
1393                         };
1394                 };
1395
1396                 p2wi: i2c@1f03400 {
1397                         compatible = "allwinner,sun6i-a31-p2wi";
1398                         reg = <0x01f03400 0x400>;
1399                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1400                         clocks = <&apb0_gates 3>;
1401                         clock-frequency = <100000>;
1402                         resets = <&apb0_rst 3>;
1403                         pinctrl-names = "default";
1404                         pinctrl-0 = <&s_p2wi_pins>;
1405                         status = "disabled";
1406                         #address-cells = <1>;
1407                         #size-cells = <0>;
1408                 };
1409         };
1410 };