2 * Copyright 2012 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
16 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/dma/sun4i-a10.h>
19 #include <dt-bindings/pinctrl/sun4i-a10.h>
22 interrupt-parent = <&intc>;
30 compatible = "allwinner,simple-framebuffer",
32 allwinner,pipeline = "de_be0-lcd0";
33 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
44 compatible = "arm,cortex-a8";
47 clock-latency = <244144>; /* 8 32k periods */
59 cooling-min-level = <0>;
60 cooling-max-level = <6>;
67 polling-delay-passive = <250>;
68 polling-delay = <1000>;
69 thermal-sensors = <&rtp>;
74 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
79 cpu_alert0: cpu_alert0 {
81 temperature = <850000>;
88 temperature = <100000>;
97 reg = <0x40000000 0x20000000>;
101 #address-cells = <1>;
106 * This is a dummy clock, to be used as placeholder on
107 * other mux clocks when a specific parent clock is not
108 * yet implemented. It should be dropped when the driver
113 compatible = "fixed-clock";
114 clock-frequency = <0>;
117 osc24M: clk@01c20050 {
119 compatible = "allwinner,sun4i-a10-osc-clk";
120 reg = <0x01c20050 0x4>;
121 clock-frequency = <24000000>;
122 clock-output-names = "osc24M";
127 compatible = "fixed-clock";
128 clock-frequency = <32768>;
129 clock-output-names = "osc32k";
134 compatible = "allwinner,sun4i-a10-pll1-clk";
135 reg = <0x01c20000 0x4>;
137 clock-output-names = "pll1";
142 compatible = "allwinner,sun4i-a10-pll1-clk";
143 reg = <0x01c20018 0x4>;
145 clock-output-names = "pll4";
150 compatible = "allwinner,sun4i-a10-pll5-clk";
151 reg = <0x01c20020 0x4>;
153 clock-output-names = "pll5_ddr", "pll5_other";
158 compatible = "allwinner,sun4i-a10-pll6-clk";
159 reg = <0x01c20028 0x4>;
161 clock-output-names = "pll6_sata", "pll6_other", "pll6";
167 compatible = "allwinner,sun4i-a10-cpu-clk";
168 reg = <0x01c20054 0x4>;
169 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
170 clock-output-names = "cpu";
175 compatible = "allwinner,sun4i-a10-axi-clk";
176 reg = <0x01c20054 0x4>;
178 clock-output-names = "axi";
181 axi_gates: clk@01c2005c {
183 compatible = "allwinner,sun4i-a10-axi-gates-clk";
184 reg = <0x01c2005c 0x4>;
186 clock-output-names = "axi_dram";
191 compatible = "allwinner,sun4i-a10-ahb-clk";
192 reg = <0x01c20054 0x4>;
194 clock-output-names = "ahb";
197 ahb_gates: clk@01c20060 {
199 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
200 reg = <0x01c20060 0x8>;
202 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
203 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
204 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
205 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
206 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
207 "ahb_de_fe", "ahb_iep", "ahb_mali400";
210 apb0: apb0@01c20054 {
212 compatible = "allwinner,sun4i-a10-apb0-clk";
213 reg = <0x01c20054 0x4>;
215 clock-output-names = "apb0";
218 apb0_gates: clk@01c20068 {
220 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
221 reg = <0x01c20068 0x4>;
223 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
228 compatible = "allwinner,sun4i-a10-apb1-clk";
229 reg = <0x01c20058 0x4>;
230 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
231 clock-output-names = "apb1";
234 apb1_gates: clk@01c2006c {
236 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
237 reg = <0x01c2006c 0x4>;
239 clock-output-names = "apb1_i2c0", "apb1_i2c1",
240 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
243 nand_clk: clk@01c20080 {
245 compatible = "allwinner,sun4i-a10-mod0-clk";
246 reg = <0x01c20080 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "nand";
251 ms_clk: clk@01c20084 {
253 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c20084 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "ms";
259 mmc0_clk: clk@01c20088 {
261 compatible = "allwinner,sun4i-a10-mmc-clk";
262 reg = <0x01c20088 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "mmc0",
269 mmc1_clk: clk@01c2008c {
271 compatible = "allwinner,sun4i-a10-mmc-clk";
272 reg = <0x01c2008c 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "mmc1",
279 mmc2_clk: clk@01c20090 {
281 compatible = "allwinner,sun4i-a10-mmc-clk";
282 reg = <0x01c20090 0x4>;
283 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
284 clock-output-names = "mmc2",
289 ts_clk: clk@01c20098 {
291 compatible = "allwinner,sun4i-a10-mod0-clk";
292 reg = <0x01c20098 0x4>;
293 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
294 clock-output-names = "ts";
297 ss_clk: clk@01c2009c {
299 compatible = "allwinner,sun4i-a10-mod0-clk";
300 reg = <0x01c2009c 0x4>;
301 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
302 clock-output-names = "ss";
305 spi0_clk: clk@01c200a0 {
307 compatible = "allwinner,sun4i-a10-mod0-clk";
308 reg = <0x01c200a0 0x4>;
309 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
310 clock-output-names = "spi0";
313 spi1_clk: clk@01c200a4 {
315 compatible = "allwinner,sun4i-a10-mod0-clk";
316 reg = <0x01c200a4 0x4>;
317 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
318 clock-output-names = "spi1";
321 spi2_clk: clk@01c200a8 {
323 compatible = "allwinner,sun4i-a10-mod0-clk";
324 reg = <0x01c200a8 0x4>;
325 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
326 clock-output-names = "spi2";
329 ir0_clk: clk@01c200b0 {
331 compatible = "allwinner,sun4i-a10-mod0-clk";
332 reg = <0x01c200b0 0x4>;
333 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
334 clock-output-names = "ir0";
337 usb_clk: clk@01c200cc {
340 compatible = "allwinner,sun5i-a13-usb-clk";
341 reg = <0x01c200cc 0x4>;
343 clock-output-names = "usb_ohci0", "usb_phy";
346 mbus_clk: clk@01c2015c {
348 compatible = "allwinner,sun5i-a13-mbus-clk";
349 reg = <0x01c2015c 0x4>;
350 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
351 clock-output-names = "mbus";
356 compatible = "simple-bus";
357 #address-cells = <1>;
361 dma: dma-controller@01c02000 {
362 compatible = "allwinner,sun4i-a10-dma";
363 reg = <0x01c02000 0x1000>;
365 clocks = <&ahb_gates 6>;
370 compatible = "allwinner,sun4i-a10-spi";
371 reg = <0x01c05000 0x1000>;
373 clocks = <&ahb_gates 20>, <&spi0_clk>;
374 clock-names = "ahb", "mod";
375 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
376 <&dma SUN4I_DMA_DEDICATED 26>;
377 dma-names = "rx", "tx";
379 #address-cells = <1>;
384 compatible = "allwinner,sun4i-a10-spi";
385 reg = <0x01c06000 0x1000>;
387 clocks = <&ahb_gates 21>, <&spi1_clk>;
388 clock-names = "ahb", "mod";
389 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
390 <&dma SUN4I_DMA_DEDICATED 8>;
391 dma-names = "rx", "tx";
393 #address-cells = <1>;
398 compatible = "allwinner,sun5i-a13-mmc";
399 reg = <0x01c0f000 0x1000>;
400 clocks = <&ahb_gates 8>,
413 compatible = "allwinner,sun5i-a13-mmc";
414 reg = <0x01c11000 0x1000>;
415 clocks = <&ahb_gates 10>,
427 usbphy: phy@01c13400 {
429 compatible = "allwinner,sun5i-a13-usb-phy";
430 reg = <0x01c13400 0x10 0x01c14800 0x4>;
431 reg-names = "phy_ctrl", "pmu1";
432 clocks = <&usb_clk 8>;
433 clock-names = "usb_phy";
434 resets = <&usb_clk 0>, <&usb_clk 1>;
435 reset-names = "usb0_reset", "usb1_reset";
439 ehci0: usb@01c14000 {
440 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
441 reg = <0x01c14000 0x100>;
443 clocks = <&ahb_gates 1>;
449 ohci0: usb@01c14400 {
450 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
451 reg = <0x01c14400 0x100>;
453 clocks = <&usb_clk 6>, <&ahb_gates 2>;
460 compatible = "allwinner,sun4i-a10-spi";
461 reg = <0x01c17000 0x1000>;
463 clocks = <&ahb_gates 22>, <&spi2_clk>;
464 clock-names = "ahb", "mod";
465 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
466 <&dma SUN4I_DMA_DEDICATED 28>;
467 dma-names = "rx", "tx";
469 #address-cells = <1>;
473 intc: interrupt-controller@01c20400 {
474 compatible = "allwinner,sun4i-a10-ic";
475 reg = <0x01c20400 0x400>;
476 interrupt-controller;
477 #interrupt-cells = <1>;
480 pio: pinctrl@01c20800 {
481 compatible = "allwinner,sun5i-a13-pinctrl";
482 reg = <0x01c20800 0x400>;
484 clocks = <&apb0_gates 5>;
486 interrupt-controller;
487 #interrupt-cells = <2>;
491 uart1_pins_a: uart1@0 {
492 allwinner,pins = "PE10", "PE11";
493 allwinner,function = "uart1";
494 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
495 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
498 uart1_pins_b: uart1@1 {
499 allwinner,pins = "PG3", "PG4";
500 allwinner,function = "uart1";
501 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
502 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
505 i2c0_pins_a: i2c0@0 {
506 allwinner,pins = "PB0", "PB1";
507 allwinner,function = "i2c0";
508 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
509 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
512 i2c1_pins_a: i2c1@0 {
513 allwinner,pins = "PB15", "PB16";
514 allwinner,function = "i2c1";
515 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
516 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
519 i2c2_pins_a: i2c2@0 {
520 allwinner,pins = "PB17", "PB18";
521 allwinner,function = "i2c2";
522 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
523 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
526 mmc0_pins_a: mmc0@0 {
527 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
528 allwinner,function = "mmc0";
529 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
530 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
535 compatible = "allwinner,sun4i-a10-timer";
536 reg = <0x01c20c00 0x90>;
541 wdt: watchdog@01c20c90 {
542 compatible = "allwinner,sun4i-a10-wdt";
543 reg = <0x01c20c90 0x10>;
546 lradc: lradc@01c22800 {
547 compatible = "allwinner,sun4i-a10-lradc-keys";
548 reg = <0x01c22800 0x100>;
553 sid: eeprom@01c23800 {
554 compatible = "allwinner,sun4i-a10-sid";
555 reg = <0x01c23800 0x10>;
559 compatible = "allwinner,sun4i-a10-ts";
560 reg = <0x01c25000 0x100>;
562 #thermal-sensor-cells = <0>;
565 uart1: serial@01c28400 {
566 compatible = "snps,dw-apb-uart";
567 reg = <0x01c28400 0x400>;
571 clocks = <&apb1_gates 17>;
575 uart3: serial@01c28c00 {
576 compatible = "snps,dw-apb-uart";
577 reg = <0x01c28c00 0x400>;
581 clocks = <&apb1_gates 19>;
586 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
587 reg = <0x01c2ac00 0x400>;
589 clocks = <&apb1_gates 0>;
591 #address-cells = <1>;
596 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
597 reg = <0x01c2b000 0x400>;
599 clocks = <&apb1_gates 1>;
601 #address-cells = <1>;
606 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
607 reg = <0x01c2b400 0x400>;
609 clocks = <&apb1_gates 2>;
611 #address-cells = <1>;
616 compatible = "allwinner,sun5i-a13-hstimer";
617 reg = <0x01c60000 0x1000>;
618 interrupts = <82>, <83>;
619 clocks = <&ahb_gates 28>;