2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
16 #include <dt-bindings/dma/sun4i-a10.h>
17 #include <dt-bindings/pinctrl/sun4i-a10.h>
20 interrupt-parent = <&intc>;
32 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
33 allwinner,pipeline = "de_be0-lcd0-hdmi";
34 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
40 compatible = "allwinner,simple-framebuffer",
42 allwinner,pipeline = "de_be0-lcd0";
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
50 compatible = "arm,cortex-a8";
55 reg = <0x40000000 0x20000000>;
64 * This is a dummy clock, to be used as placeholder on
65 * other mux clocks when a specific parent clock is not
66 * yet implemented. It should be dropped when the driver
71 compatible = "fixed-clock";
72 clock-frequency = <0>;
75 osc24M: clk@01c20050 {
77 compatible = "allwinner,sun4i-a10-osc-clk";
78 reg = <0x01c20050 0x4>;
79 clock-frequency = <24000000>;
80 clock-output-names = "osc24M";
85 compatible = "fixed-clock";
86 clock-frequency = <32768>;
87 clock-output-names = "osc32k";
92 compatible = "allwinner,sun4i-a10-pll1-clk";
93 reg = <0x01c20000 0x4>;
95 clock-output-names = "pll1";
100 compatible = "allwinner,sun4i-a10-pll1-clk";
101 reg = <0x01c20018 0x4>;
103 clock-output-names = "pll4";
108 compatible = "allwinner,sun4i-a10-pll5-clk";
109 reg = <0x01c20020 0x4>;
111 clock-output-names = "pll5_ddr", "pll5_other";
116 compatible = "allwinner,sun4i-a10-pll6-clk";
117 reg = <0x01c20028 0x4>;
119 clock-output-names = "pll6_sata", "pll6_other", "pll6";
125 compatible = "allwinner,sun4i-a10-cpu-clk";
126 reg = <0x01c20054 0x4>;
127 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
128 clock-output-names = "cpu";
133 compatible = "allwinner,sun4i-a10-axi-clk";
134 reg = <0x01c20054 0x4>;
136 clock-output-names = "axi";
139 axi_gates: clk@01c2005c {
141 compatible = "allwinner,sun4i-a10-axi-gates-clk";
142 reg = <0x01c2005c 0x4>;
144 clock-output-names = "axi_dram";
149 compatible = "allwinner,sun4i-a10-ahb-clk";
150 reg = <0x01c20054 0x4>;
152 clock-output-names = "ahb";
155 ahb_gates: clk@01c20060 {
157 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
158 reg = <0x01c20060 0x8>;
160 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
161 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
162 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
163 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
164 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
165 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
166 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
169 apb0: apb0@01c20054 {
171 compatible = "allwinner,sun4i-a10-apb0-clk";
172 reg = <0x01c20054 0x4>;
174 clock-output-names = "apb0";
177 apb0_gates: clk@01c20068 {
179 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
180 reg = <0x01c20068 0x4>;
182 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
183 "apb0_ir", "apb0_keypad";
188 compatible = "allwinner,sun4i-a10-apb1-clk";
189 reg = <0x01c20058 0x4>;
190 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
191 clock-output-names = "apb1";
194 apb1_gates: clk@01c2006c {
196 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
197 reg = <0x01c2006c 0x4>;
199 clock-output-names = "apb1_i2c0", "apb1_i2c1",
200 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
201 "apb1_uart2", "apb1_uart3";
204 nand_clk: clk@01c20080 {
206 compatible = "allwinner,sun4i-a10-mod0-clk";
207 reg = <0x01c20080 0x4>;
208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
209 clock-output-names = "nand";
212 ms_clk: clk@01c20084 {
214 compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20084 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "ms";
220 mmc0_clk: clk@01c20088 {
222 compatible = "allwinner,sun4i-a10-mod0-clk";
223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc0";
228 mmc1_clk: clk@01c2008c {
230 compatible = "allwinner,sun4i-a10-mod0-clk";
231 reg = <0x01c2008c 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc1";
236 mmc2_clk: clk@01c20090 {
238 compatible = "allwinner,sun4i-a10-mod0-clk";
239 reg = <0x01c20090 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc2";
244 ts_clk: clk@01c20098 {
246 compatible = "allwinner,sun4i-a10-mod0-clk";
247 reg = <0x01c20098 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "ts";
252 ss_clk: clk@01c2009c {
254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c2009c 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "ss";
260 spi0_clk: clk@01c200a0 {
262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c200a0 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "spi0";
268 spi1_clk: clk@01c200a4 {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c200a4 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "spi1";
276 spi2_clk: clk@01c200a8 {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c200a8 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "spi2";
284 ir0_clk: clk@01c200b0 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200b0 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "ir0";
292 usb_clk: clk@01c200cc {
295 compatible = "allwinner,sun5i-a13-usb-clk";
296 reg = <0x01c200cc 0x4>;
298 clock-output-names = "usb_ohci0", "usb_phy";
301 mbus_clk: clk@01c2015c {
303 compatible = "allwinner,sun5i-a13-mbus-clk";
304 reg = <0x01c2015c 0x4>;
305 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
306 clock-output-names = "mbus";
311 compatible = "simple-bus";
312 #address-cells = <1>;
316 dma: dma-controller@01c02000 {
317 compatible = "allwinner,sun4i-a10-dma";
318 reg = <0x01c02000 0x1000>;
320 clocks = <&ahb_gates 6>;
325 compatible = "allwinner,sun4i-a10-spi";
326 reg = <0x01c05000 0x1000>;
328 clocks = <&ahb_gates 20>, <&spi0_clk>;
329 clock-names = "ahb", "mod";
330 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
331 <&dma SUN4I_DMA_DEDICATED 26>;
332 dma-names = "rx", "tx";
334 #address-cells = <1>;
339 compatible = "allwinner,sun4i-a10-spi";
340 reg = <0x01c06000 0x1000>;
342 clocks = <&ahb_gates 21>, <&spi1_clk>;
343 clock-names = "ahb", "mod";
344 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
345 <&dma SUN4I_DMA_DEDICATED 8>;
346 dma-names = "rx", "tx";
348 #address-cells = <1>;
352 emac: ethernet@01c0b000 {
353 compatible = "allwinner,sun4i-a10-emac";
354 reg = <0x01c0b000 0x1000>;
356 clocks = <&ahb_gates 17>;
360 mdio: mdio@01c0b080 {
361 compatible = "allwinner,sun4i-a10-mdio";
362 reg = <0x01c0b080 0x14>;
364 #address-cells = <1>;
369 compatible = "allwinner,sun5i-a13-mmc";
370 reg = <0x01c0f000 0x1000>;
371 clocks = <&ahb_gates 8>, <&mmc0_clk>;
372 clock-names = "ahb", "mmc";
378 compatible = "allwinner,sun5i-a13-mmc";
379 reg = <0x01c10000 0x1000>;
380 clocks = <&ahb_gates 9>, <&mmc1_clk>;
381 clock-names = "ahb", "mmc";
387 compatible = "allwinner,sun5i-a13-mmc";
388 reg = <0x01c11000 0x1000>;
389 clocks = <&ahb_gates 10>, <&mmc2_clk>;
390 clock-names = "ahb", "mmc";
395 usbphy: phy@01c13400 {
397 compatible = "allwinner,sun5i-a13-usb-phy";
398 reg = <0x01c13400 0x10 0x01c14800 0x4>;
399 reg-names = "phy_ctrl", "pmu1";
400 clocks = <&usb_clk 8>;
401 clock-names = "usb_phy";
402 resets = <&usb_clk 0>, <&usb_clk 1>;
403 reset-names = "usb0_reset", "usb1_reset";
407 ehci0: usb@01c14000 {
408 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
409 reg = <0x01c14000 0x100>;
411 clocks = <&ahb_gates 1>;
417 ohci0: usb@01c14400 {
418 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
419 reg = <0x01c14400 0x100>;
421 clocks = <&usb_clk 6>, <&ahb_gates 2>;
428 compatible = "allwinner,sun4i-a10-spi";
429 reg = <0x01c17000 0x1000>;
431 clocks = <&ahb_gates 22>, <&spi2_clk>;
432 clock-names = "ahb", "mod";
433 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
434 <&dma SUN4I_DMA_DEDICATED 28>;
435 dma-names = "rx", "tx";
437 #address-cells = <1>;
441 intc: interrupt-controller@01c20400 {
442 compatible = "allwinner,sun4i-a10-ic";
443 reg = <0x01c20400 0x400>;
444 interrupt-controller;
445 #interrupt-cells = <1>;
448 pio: pinctrl@01c20800 {
449 compatible = "allwinner,sun5i-a10s-pinctrl";
450 reg = <0x01c20800 0x400>;
452 clocks = <&apb0_gates 5>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
459 uart0_pins_a: uart0@0 {
460 allwinner,pins = "PB19", "PB20";
461 allwinner,function = "uart0";
462 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
463 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
466 uart2_pins_a: uart2@0 {
467 allwinner,pins = "PC18", "PC19";
468 allwinner,function = "uart2";
469 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
470 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
473 uart3_pins_a: uart3@0 {
474 allwinner,pins = "PG9", "PG10";
475 allwinner,function = "uart3";
476 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
477 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
480 emac_pins_a: emac0@0 {
481 allwinner,pins = "PA0", "PA1", "PA2",
482 "PA3", "PA4", "PA5", "PA6",
483 "PA7", "PA8", "PA9", "PA10",
484 "PA11", "PA12", "PA13", "PA14",
486 allwinner,function = "emac";
487 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
488 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
491 i2c0_pins_a: i2c0@0 {
492 allwinner,pins = "PB0", "PB1";
493 allwinner,function = "i2c0";
494 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
495 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
498 i2c1_pins_a: i2c1@0 {
499 allwinner,pins = "PB15", "PB16";
500 allwinner,function = "i2c1";
501 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
502 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
505 i2c2_pins_a: i2c2@0 {
506 allwinner,pins = "PB17", "PB18";
507 allwinner,function = "i2c2";
508 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
509 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
512 mmc0_pins_a: mmc0@0 {
513 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
514 allwinner,function = "mmc0";
515 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
516 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
519 mmc1_pins_a: mmc1@0 {
520 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
521 allwinner,function = "mmc1";
522 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
523 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
528 compatible = "allwinner,sun4i-a10-timer";
529 reg = <0x01c20c00 0x90>;
534 wdt: watchdog@01c20c90 {
535 compatible = "allwinner,sun4i-a10-wdt";
536 reg = <0x01c20c90 0x10>;
539 lradc: lradc@01c22800 {
540 compatible = "allwinner,sun4i-a10-lradc-keys";
541 reg = <0x01c22800 0x100>;
546 sid: eeprom@01c23800 {
547 compatible = "allwinner,sun4i-a10-sid";
548 reg = <0x01c23800 0x10>;
552 compatible = "allwinner,sun4i-a10-ts";
553 reg = <0x01c25000 0x100>;
555 #thermal-sensor-cells = <0>;
558 uart0: serial@01c28000 {
559 compatible = "snps,dw-apb-uart";
560 reg = <0x01c28000 0x400>;
564 clocks = <&apb1_gates 16>;
568 uart1: serial@01c28400 {
569 compatible = "snps,dw-apb-uart";
570 reg = <0x01c28400 0x400>;
574 clocks = <&apb1_gates 17>;
578 uart2: serial@01c28800 {
579 compatible = "snps,dw-apb-uart";
580 reg = <0x01c28800 0x400>;
584 clocks = <&apb1_gates 18>;
588 uart3: serial@01c28c00 {
589 compatible = "snps,dw-apb-uart";
590 reg = <0x01c28c00 0x400>;
594 clocks = <&apb1_gates 19>;
599 #address-cells = <1>;
601 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
602 reg = <0x01c2ac00 0x400>;
604 clocks = <&apb1_gates 0>;
609 #address-cells = <1>;
611 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
612 reg = <0x01c2b000 0x400>;
614 clocks = <&apb1_gates 1>;
619 #address-cells = <1>;
621 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
622 reg = <0x01c2b400 0x400>;
624 clocks = <&apb1_gates 2>;
629 compatible = "allwinner,sun5i-a13-hstimer";
630 reg = <0x01c60000 0x1000>;
631 interrupts = <82>, <83>;
632 clocks = <&ahb_gates 28>;