2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
52 interrupt-parent = <&intc>;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
110 #address-cells = <1>;
114 compatible = "arm,cortex-a8";
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
125 #cooling-cells = <2>;
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 cpu_alert0: cpu-alert0 {
146 temperature = <850000>;
153 temperature = <100000>;
162 #address-cells = <1>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-output-names = "osc24M";
175 compatible = "fixed-clock";
176 clock-frequency = <32768>;
177 clock-output-names = "osc32k";
182 compatible = "allwinner,sun4i-a10-display-engine";
183 allwinner,pipelines = <&fe0>, <&fe1>;
188 compatible = "arm,cortex-a8-pmu";
193 #address-cells = <1>;
197 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
199 compatible = "shared-dma-pool";
201 alloc-ranges = <0x4a000000 0x6000000>;
208 compatible = "simple-bus";
209 #address-cells = <1>;
213 system-control@1c00000 {
214 compatible = "allwinner,sun4i-a10-system-control";
215 reg = <0x01c00000 0x30>;
216 #address-cells = <1>;
221 compatible = "mmio-sram";
222 reg = <0x00000000 0xc000>;
223 #address-cells = <1>;
225 ranges = <0 0x00000000 0xc000>;
227 emac_sram: sram-section@8000 {
228 compatible = "allwinner,sun4i-a10-sram-a3-a4";
229 reg = <0x8000 0x4000>;
235 compatible = "mmio-sram";
236 reg = <0x00010000 0x1000>;
237 #address-cells = <1>;
239 ranges = <0 0x00010000 0x1000>;
241 otg_sram: sram-section@0 {
242 compatible = "allwinner,sun4i-a10-sram-d";
243 reg = <0x0000 0x1000>;
248 sram_c: sram@1d00000 {
249 compatible = "mmio-sram";
250 reg = <0x01d00000 0xd0000>;
251 #address-cells = <1>;
253 ranges = <0 0x01d00000 0xd0000>;
255 ve_sram: sram-section@0 {
256 compatible = "allwinner,sun4i-a10-sram-c1";
257 reg = <0x000000 0x80000>;
262 dma: dma-controller@1c02000 {
263 compatible = "allwinner,sun4i-a10-dma";
264 reg = <0x01c02000 0x1000>;
266 clocks = <&ccu CLK_AHB_DMA>;
270 nfc: nand-controller@1c03000 {
271 compatible = "allwinner,sun4i-a10-nand";
272 reg = <0x01c03000 0x1000>;
274 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
275 clock-names = "ahb", "mod";
276 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
279 #address-cells = <1>;
284 compatible = "allwinner,sun4i-a10-spi";
285 reg = <0x01c05000 0x1000>;
287 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
288 clock-names = "ahb", "mod";
289 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
290 <&dma SUN4I_DMA_DEDICATED 26>;
291 dma-names = "rx", "tx";
293 #address-cells = <1>;
298 compatible = "allwinner,sun4i-a10-spi";
299 reg = <0x01c06000 0x1000>;
301 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
302 clock-names = "ahb", "mod";
303 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
304 <&dma SUN4I_DMA_DEDICATED 8>;
305 dma-names = "rx", "tx";
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
309 #address-cells = <1>;
313 emac: ethernet@1c0b000 {
314 compatible = "allwinner,sun4i-a10-emac";
315 reg = <0x01c0b000 0x1000>;
317 clocks = <&ccu CLK_AHB_EMAC>;
318 allwinner,sram = <&emac_sram 1>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&emac_pins>;
325 compatible = "allwinner,sun4i-a10-mdio";
326 reg = <0x01c0b080 0x14>;
328 #address-cells = <1>;
332 tcon0: lcd-controller@1c0c000 {
333 compatible = "allwinner,sun4i-a10-tcon";
334 reg = <0x01c0c000 0x1000>;
336 resets = <&ccu RST_TCON0>;
338 clocks = <&ccu CLK_AHB_LCD0>,
339 <&ccu CLK_TCON0_CH0>,
340 <&ccu CLK_TCON0_CH1>;
344 clock-output-names = "tcon0-pixel-clock";
346 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
349 #address-cells = <1>;
353 #address-cells = <1>;
357 tcon0_in_be0: endpoint@0 {
359 remote-endpoint = <&be0_out_tcon0>;
362 tcon0_in_be1: endpoint@1 {
364 remote-endpoint = <&be1_out_tcon0>;
369 #address-cells = <1>;
373 tcon0_out_hdmi: endpoint@1 {
375 remote-endpoint = <&hdmi_in_tcon0>;
376 allwinner,tcon-channel = <1>;
382 tcon1: lcd-controller@1c0d000 {
383 compatible = "allwinner,sun4i-a10-tcon";
384 reg = <0x01c0d000 0x1000>;
386 resets = <&ccu RST_TCON1>;
388 clocks = <&ccu CLK_AHB_LCD1>,
389 <&ccu CLK_TCON1_CH0>,
390 <&ccu CLK_TCON1_CH1>;
394 clock-output-names = "tcon1-pixel-clock";
396 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
399 #address-cells = <1>;
403 #address-cells = <1>;
407 tcon1_in_be0: endpoint@0 {
409 remote-endpoint = <&be0_out_tcon1>;
412 tcon1_in_be1: endpoint@1 {
414 remote-endpoint = <&be1_out_tcon1>;
419 #address-cells = <1>;
423 tcon1_out_hdmi: endpoint@1 {
425 remote-endpoint = <&hdmi_in_tcon1>;
426 allwinner,tcon-channel = <1>;
432 video-codec@1c0e000 {
433 compatible = "allwinner,sun4i-a10-video-engine";
434 reg = <0x01c0e000 0x1000>;
435 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
437 clock-names = "ahb", "mod", "ram";
438 resets = <&ccu RST_VE>;
440 allwinner,sram = <&ve_sram 1>;
444 compatible = "allwinner,sun4i-a10-mmc";
445 reg = <0x01c0f000 0x1000>;
446 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
447 clock-names = "ahb", "mmc";
449 pinctrl-names = "default";
450 pinctrl-0 = <&mmc0_pins>;
452 #address-cells = <1>;
457 compatible = "allwinner,sun4i-a10-mmc";
458 reg = <0x01c10000 0x1000>;
459 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
460 clock-names = "ahb", "mmc";
463 #address-cells = <1>;
468 compatible = "allwinner,sun4i-a10-mmc";
469 reg = <0x01c11000 0x1000>;
470 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
471 clock-names = "ahb", "mmc";
474 #address-cells = <1>;
479 compatible = "allwinner,sun4i-a10-mmc";
480 reg = <0x01c12000 0x1000>;
481 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
482 clock-names = "ahb", "mmc";
485 #address-cells = <1>;
489 usb_otg: usb@1c13000 {
490 compatible = "allwinner,sun4i-a10-musb";
491 reg = <0x01c13000 0x0400>;
492 clocks = <&ccu CLK_AHB_OTG>;
494 interrupt-names = "mc";
497 extcon = <&usbphy 0>;
498 allwinner,sram = <&otg_sram 1>;
503 usbphy: phy@1c13400 {
505 compatible = "allwinner,sun4i-a10-usb-phy";
506 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
507 reg-names = "phy_ctrl", "pmu1", "pmu2";
508 clocks = <&ccu CLK_USB_PHY>;
509 clock-names = "usb_phy";
510 resets = <&ccu RST_USB_PHY0>,
513 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
518 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
519 reg = <0x01c14000 0x100>;
521 clocks = <&ccu CLK_AHB_EHCI0>;
527 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
528 reg = <0x01c14400 0x100>;
530 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
535 crypto: crypto-engine@1c15000 {
536 compatible = "allwinner,sun4i-a10-crypto";
537 reg = <0x01c15000 0x1000>;
539 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
540 clock-names = "ahb", "mod";
544 compatible = "allwinner,sun4i-a10-hdmi";
545 reg = <0x01c16000 0x1000>;
547 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
548 <&ccu CLK_PLL_VIDEO0_2X>,
549 <&ccu CLK_PLL_VIDEO1_2X>;
550 clock-names = "ahb", "mod", "pll-0", "pll-1";
551 dmas = <&dma SUN4I_DMA_NORMAL 16>,
552 <&dma SUN4I_DMA_NORMAL 16>,
553 <&dma SUN4I_DMA_DEDICATED 24>;
554 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
558 #address-cells = <1>;
562 #address-cells = <1>;
566 hdmi_in_tcon0: endpoint@0 {
568 remote-endpoint = <&tcon0_out_hdmi>;
571 hdmi_in_tcon1: endpoint@1 {
573 remote-endpoint = <&tcon1_out_hdmi>;
584 compatible = "allwinner,sun4i-a10-spi";
585 reg = <0x01c17000 0x1000>;
587 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
588 clock-names = "ahb", "mod";
589 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
590 <&dma SUN4I_DMA_DEDICATED 28>;
591 dma-names = "rx", "tx";
593 #address-cells = <1>;
598 compatible = "allwinner,sun4i-a10-ahci";
599 reg = <0x01c18000 0x1000>;
601 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
606 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
607 reg = <0x01c1c000 0x100>;
609 clocks = <&ccu CLK_AHB_EHCI1>;
615 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
616 reg = <0x01c1c400 0x100>;
618 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
624 compatible = "allwinner,sun4i-a10-spi";
625 reg = <0x01c1f000 0x1000>;
627 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
628 clock-names = "ahb", "mod";
629 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
630 <&dma SUN4I_DMA_DEDICATED 30>;
631 dma-names = "rx", "tx";
633 #address-cells = <1>;
638 compatible = "allwinner,sun4i-a10-ccu";
639 reg = <0x01c20000 0x400>;
640 clocks = <&osc24M>, <&osc32k>;
641 clock-names = "hosc", "losc";
646 intc: interrupt-controller@1c20400 {
647 compatible = "allwinner,sun4i-a10-ic";
648 reg = <0x01c20400 0x400>;
649 interrupt-controller;
650 #interrupt-cells = <1>;
653 pio: pinctrl@1c20800 {
654 compatible = "allwinner,sun4i-a10-pinctrl";
655 reg = <0x01c20800 0x400>;
657 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
658 clock-names = "apb", "hosc", "losc";
660 interrupt-controller;
661 #interrupt-cells = <3>;
664 can0_ph_pins: can0-ph-pins {
665 pins = "PH20", "PH21";
669 emac_pins: emac0-pins {
670 pins = "PA0", "PA1", "PA2",
671 "PA3", "PA4", "PA5", "PA6",
672 "PA7", "PA8", "PA9", "PA10",
673 "PA11", "PA12", "PA13", "PA14",
678 i2c0_pins: i2c0-pins {
683 i2c1_pins: i2c1-pins {
684 pins = "PB18", "PB19";
688 i2c2_pins: i2c2-pins {
689 pins = "PB20", "PB21";
693 ir0_rx_pins: ir0-rx-pin {
698 ir0_tx_pins: ir0-tx-pin {
703 ir1_rx_pins: ir1-rx-pin {
708 ir1_tx_pins: ir1-tx-pin {
713 mmc0_pins: mmc0-pins {
714 pins = "PF0", "PF1", "PF2",
717 drive-strength = <30>;
721 ps2_ch0_pins: ps2-ch0-pins {
722 pins = "PI20", "PI21";
726 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
727 pins = "PH12", "PH13";
741 spdif_tx_pin: spdif-tx-pin {
747 spi0_pi_pins: spi0-pi-pins {
748 pins = "PI11", "PI12", "PI13";
752 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
757 spi1_pins: spi1-pins {
758 pins = "PI17", "PI18", "PI19";
762 spi1_cs0_pin: spi1-cs0-pin {
767 spi2_pb_pins: spi2-pb-pins {
768 pins = "PB15", "PB16", "PB17";
772 spi2_pc_pins: spi2-pc-pins {
773 pins = "PC20", "PC21", "PC22";
777 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
782 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
787 uart0_pb_pins: uart0-pb-pins {
788 pins = "PB22", "PB23";
792 uart0_pf_pins: uart0-pf-pins {
797 uart1_pins: uart1-pins {
798 pins = "PA10", "PA11";
804 compatible = "allwinner,sun4i-a10-timer";
805 reg = <0x01c20c00 0x90>;
810 wdt: watchdog@1c20c90 {
811 compatible = "allwinner,sun4i-a10-wdt";
812 reg = <0x01c20c90 0x10>;
816 compatible = "allwinner,sun4i-a10-rtc";
817 reg = <0x01c20d00 0x20>;
822 compatible = "allwinner,sun4i-a10-pwm";
823 reg = <0x01c20e00 0xc>;
829 spdif: spdif@1c21000 {
830 #sound-dai-cells = <0>;
831 compatible = "allwinner,sun4i-a10-spdif";
832 reg = <0x01c21000 0x400>;
834 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
835 clock-names = "apb", "spdif";
836 dmas = <&dma SUN4I_DMA_NORMAL 2>,
837 <&dma SUN4I_DMA_NORMAL 2>;
838 dma-names = "rx", "tx";
843 compatible = "allwinner,sun4i-a10-ir";
844 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
845 clock-names = "apb", "ir";
847 reg = <0x01c21800 0x40>;
852 compatible = "allwinner,sun4i-a10-ir";
853 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
854 clock-names = "apb", "ir";
856 reg = <0x01c21c00 0x40>;
861 #sound-dai-cells = <0>;
862 compatible = "allwinner,sun4i-a10-i2s";
863 reg = <0x01c22400 0x400>;
865 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
866 clock-names = "apb", "mod";
867 dmas = <&dma SUN4I_DMA_NORMAL 3>,
868 <&dma SUN4I_DMA_NORMAL 3>;
869 dma-names = "rx", "tx";
873 lradc: lradc@1c22800 {
874 compatible = "allwinner,sun4i-a10-lradc-keys";
875 reg = <0x01c22800 0x100>;
880 codec: codec@1c22c00 {
881 #sound-dai-cells = <0>;
882 compatible = "allwinner,sun4i-a10-codec";
883 reg = <0x01c22c00 0x40>;
885 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
886 clock-names = "apb", "codec";
887 dmas = <&dma SUN4I_DMA_NORMAL 19>,
888 <&dma SUN4I_DMA_NORMAL 19>;
889 dma-names = "rx", "tx";
893 sid: eeprom@1c23800 {
894 compatible = "allwinner,sun4i-a10-sid";
895 reg = <0x01c23800 0x10>;
899 compatible = "allwinner,sun4i-a10-ts";
900 reg = <0x01c25000 0x100>;
902 #thermal-sensor-cells = <0>;
905 uart0: serial@1c28000 {
906 compatible = "snps,dw-apb-uart";
907 reg = <0x01c28000 0x400>;
911 clocks = <&ccu CLK_APB1_UART0>;
915 uart1: serial@1c28400 {
916 compatible = "snps,dw-apb-uart";
917 reg = <0x01c28400 0x400>;
921 clocks = <&ccu CLK_APB1_UART1>;
925 uart2: serial@1c28800 {
926 compatible = "snps,dw-apb-uart";
927 reg = <0x01c28800 0x400>;
931 clocks = <&ccu CLK_APB1_UART2>;
935 uart3: serial@1c28c00 {
936 compatible = "snps,dw-apb-uart";
937 reg = <0x01c28c00 0x400>;
941 clocks = <&ccu CLK_APB1_UART3>;
945 uart4: serial@1c29000 {
946 compatible = "snps,dw-apb-uart";
947 reg = <0x01c29000 0x400>;
951 clocks = <&ccu CLK_APB1_UART4>;
955 uart5: serial@1c29400 {
956 compatible = "snps,dw-apb-uart";
957 reg = <0x01c29400 0x400>;
961 clocks = <&ccu CLK_APB1_UART5>;
965 uart6: serial@1c29800 {
966 compatible = "snps,dw-apb-uart";
967 reg = <0x01c29800 0x400>;
971 clocks = <&ccu CLK_APB1_UART6>;
975 uart7: serial@1c29c00 {
976 compatible = "snps,dw-apb-uart";
977 reg = <0x01c29c00 0x400>;
981 clocks = <&ccu CLK_APB1_UART7>;
986 compatible = "allwinner,sun4i-a10-ps2";
987 reg = <0x01c2a000 0x400>;
989 clocks = <&ccu CLK_APB1_PS20>;
994 compatible = "allwinner,sun4i-a10-ps2";
995 reg = <0x01c2a400 0x400>;
997 clocks = <&ccu CLK_APB1_PS21>;
1002 compatible = "allwinner,sun4i-a10-i2c";
1003 reg = <0x01c2ac00 0x400>;
1005 clocks = <&ccu CLK_APB1_I2C0>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c0_pins>;
1008 status = "disabled";
1009 #address-cells = <1>;
1014 compatible = "allwinner,sun4i-a10-i2c";
1015 reg = <0x01c2b000 0x400>;
1017 clocks = <&ccu CLK_APB1_I2C1>;
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&i2c1_pins>;
1020 status = "disabled";
1021 #address-cells = <1>;
1026 compatible = "allwinner,sun4i-a10-i2c";
1027 reg = <0x01c2b400 0x400>;
1029 clocks = <&ccu CLK_APB1_I2C2>;
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&i2c2_pins>;
1032 status = "disabled";
1033 #address-cells = <1>;
1038 compatible = "allwinner,sun4i-a10-can";
1039 reg = <0x01c2bc00 0x400>;
1041 clocks = <&ccu CLK_APB1_CAN>;
1042 status = "disabled";
1046 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1047 reg = <0x01c40000 0x10000>;
1053 interrupt-names = "gp",
1058 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1059 clock-names = "bus", "core";
1060 resets = <&ccu RST_GPU>;
1062 assigned-clocks = <&ccu CLK_GPU>;
1063 assigned-clock-rates = <384000000>;
1066 fe0: display-frontend@1e00000 {
1067 compatible = "allwinner,sun4i-a10-display-frontend";
1068 reg = <0x01e00000 0x20000>;
1070 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1071 <&ccu CLK_DRAM_DE_FE0>;
1072 clock-names = "ahb", "mod",
1074 resets = <&ccu RST_DE_FE0>;
1077 #address-cells = <1>;
1081 #address-cells = <1>;
1085 fe0_out_be0: endpoint@0 {
1087 remote-endpoint = <&be0_in_fe0>;
1090 fe0_out_be1: endpoint@1 {
1092 remote-endpoint = <&be1_in_fe0>;
1098 fe1: display-frontend@1e20000 {
1099 compatible = "allwinner,sun4i-a10-display-frontend";
1100 reg = <0x01e20000 0x20000>;
1102 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1103 <&ccu CLK_DRAM_DE_FE1>;
1104 clock-names = "ahb", "mod",
1106 resets = <&ccu RST_DE_FE1>;
1109 #address-cells = <1>;
1113 #address-cells = <1>;
1117 fe1_out_be0: endpoint@0 {
1119 remote-endpoint = <&be0_in_fe1>;
1122 fe1_out_be1: endpoint@1 {
1124 remote-endpoint = <&be1_in_fe1>;
1130 be1: display-backend@1e40000 {
1131 compatible = "allwinner,sun4i-a10-display-backend";
1132 reg = <0x01e40000 0x10000>;
1134 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1135 <&ccu CLK_DRAM_DE_BE1>;
1136 clock-names = "ahb", "mod",
1138 resets = <&ccu RST_DE_BE1>;
1141 #address-cells = <1>;
1145 #address-cells = <1>;
1149 be1_in_fe0: endpoint@0 {
1151 remote-endpoint = <&fe0_out_be1>;
1154 be1_in_fe1: endpoint@1 {
1156 remote-endpoint = <&fe1_out_be1>;
1161 #address-cells = <1>;
1165 be1_out_tcon0: endpoint@0 {
1167 remote-endpoint = <&tcon0_in_be1>;
1170 be1_out_tcon1: endpoint@1 {
1172 remote-endpoint = <&tcon1_in_be1>;
1178 be0: display-backend@1e60000 {
1179 compatible = "allwinner,sun4i-a10-display-backend";
1180 reg = <0x01e60000 0x10000>;
1182 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1183 <&ccu CLK_DRAM_DE_BE0>;
1184 clock-names = "ahb", "mod",
1186 resets = <&ccu RST_DE_BE0>;
1189 #address-cells = <1>;
1193 #address-cells = <1>;
1197 be0_in_fe0: endpoint@0 {
1199 remote-endpoint = <&fe0_out_be0>;
1202 be0_in_fe1: endpoint@1 {
1204 remote-endpoint = <&fe1_out_be0>;
1209 #address-cells = <1>;
1213 be0_out_tcon0: endpoint@0 {
1215 remote-endpoint = <&tcon0_in_be0>;
1218 be0_out_tcon1: endpoint@1 {
1220 remote-endpoint = <&tcon1_in_be0>;