2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
16 interrupt-parent = <&intc>;
29 compatible = "arm,cortex-a8";
35 reg = <0x40000000 0x80000000>;
44 * This is a dummy clock, to be used as placeholder on
45 * other mux clocks when a specific parent clock is not
46 * yet implemented. It should be dropped when the driver
51 compatible = "fixed-clock";
52 clock-frequency = <0>;
55 osc24M: osc24M@01c20050 {
57 compatible = "allwinner,sun4i-osc-clk";
58 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
70 compatible = "allwinner,sun4i-pll1-clk";
71 reg = <0x01c20000 0x4>;
77 compatible = "allwinner,sun4i-pll1-clk";
78 reg = <0x01c20018 0x4>;
84 compatible = "allwinner,sun4i-pll5-clk";
85 reg = <0x01c20020 0x4>;
87 clock-output-names = "pll5_ddr", "pll5_other";
92 compatible = "allwinner,sun4i-pll6-clk";
93 reg = <0x01c20028 0x4>;
95 clock-output-names = "pll6_sata", "pll6_other", "pll6";
101 compatible = "allwinner,sun4i-cpu-clk";
102 reg = <0x01c20054 0x4>;
103 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 compatible = "allwinner,sun4i-axi-clk";
109 reg = <0x01c20054 0x4>;
113 axi_gates: axi_gates@01c2005c {
115 compatible = "allwinner,sun4i-axi-gates-clk";
116 reg = <0x01c2005c 0x4>;
118 clock-output-names = "axi_dram";
123 compatible = "allwinner,sun4i-ahb-clk";
124 reg = <0x01c20054 0x4>;
128 ahb_gates: ahb_gates@01c20060 {
130 compatible = "allwinner,sun4i-ahb-gates-clk";
131 reg = <0x01c20060 0x8>;
133 clock-output-names = "ahb_usb0", "ahb_ehci0",
134 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
135 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
136 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
137 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
138 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
139 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
140 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
141 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
142 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
143 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
146 apb0: apb0@01c20054 {
148 compatible = "allwinner,sun4i-apb0-clk";
149 reg = <0x01c20054 0x4>;
153 apb0_gates: apb0_gates@01c20068 {
155 compatible = "allwinner,sun4i-apb0-gates-clk";
156 reg = <0x01c20068 0x4>;
158 clock-output-names = "apb0_codec", "apb0_spdif",
159 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
160 "apb0_ir1", "apb0_keypad";
163 apb1_mux: apb1_mux@01c20058 {
165 compatible = "allwinner,sun4i-apb1-mux-clk";
166 reg = <0x01c20058 0x4>;
167 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 apb1: apb1@01c20058 {
172 compatible = "allwinner,sun4i-apb1-clk";
173 reg = <0x01c20058 0x4>;
174 clocks = <&apb1_mux>;
177 apb1_gates: apb1_gates@01c2006c {
179 compatible = "allwinner,sun4i-apb1-gates-clk";
180 reg = <0x01c2006c 0x4>;
182 clock-output-names = "apb1_i2c0", "apb1_i2c1",
183 "apb1_i2c2", "apb1_can", "apb1_scr",
184 "apb1_ps20", "apb1_ps21", "apb1_uart0",
185 "apb1_uart1", "apb1_uart2", "apb1_uart3",
186 "apb1_uart4", "apb1_uart5", "apb1_uart6",
190 nand_clk: clk@01c20080 {
192 compatible = "allwinner,sun4i-mod0-clk";
193 reg = <0x01c20080 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "nand";
198 ms_clk: clk@01c20084 {
200 compatible = "allwinner,sun4i-mod0-clk";
201 reg = <0x01c20084 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "ms";
206 mmc0_clk: clk@01c20088 {
208 compatible = "allwinner,sun4i-mod0-clk";
209 reg = <0x01c20088 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc0";
214 mmc1_clk: clk@01c2008c {
216 compatible = "allwinner,sun4i-mod0-clk";
217 reg = <0x01c2008c 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "mmc1";
222 mmc2_clk: clk@01c20090 {
224 compatible = "allwinner,sun4i-mod0-clk";
225 reg = <0x01c20090 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc2";
230 mmc3_clk: clk@01c20094 {
232 compatible = "allwinner,sun4i-mod0-clk";
233 reg = <0x01c20094 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc3";
238 ts_clk: clk@01c20098 {
240 compatible = "allwinner,sun4i-mod0-clk";
241 reg = <0x01c20098 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "ts";
246 ss_clk: clk@01c2009c {
248 compatible = "allwinner,sun4i-mod0-clk";
249 reg = <0x01c2009c 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "ss";
254 spi0_clk: clk@01c200a0 {
256 compatible = "allwinner,sun4i-mod0-clk";
257 reg = <0x01c200a0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "spi0";
262 spi1_clk: clk@01c200a4 {
264 compatible = "allwinner,sun4i-mod0-clk";
265 reg = <0x01c200a4 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "spi1";
270 spi2_clk: clk@01c200a8 {
272 compatible = "allwinner,sun4i-mod0-clk";
273 reg = <0x01c200a8 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi2";
278 pata_clk: clk@01c200ac {
280 compatible = "allwinner,sun4i-mod0-clk";
281 reg = <0x01c200ac 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "pata";
286 ir0_clk: clk@01c200b0 {
288 compatible = "allwinner,sun4i-mod0-clk";
289 reg = <0x01c200b0 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "ir0";
294 ir1_clk: clk@01c200b4 {
296 compatible = "allwinner,sun4i-mod0-clk";
297 reg = <0x01c200b4 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "ir1";
302 spi3_clk: clk@01c200d4 {
304 compatible = "allwinner,sun4i-mod0-clk";
305 reg = <0x01c200d4 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "spi3";
312 compatible = "simple-bus";
313 #address-cells = <1>;
317 emac: ethernet@01c0b000 {
318 compatible = "allwinner,sun4i-a10-emac";
319 reg = <0x01c0b000 0x1000>;
321 clocks = <&ahb_gates 17>;
326 compatible = "allwinner,sun4i-a10-mdio";
327 reg = <0x01c0b080 0x14>;
329 #address-cells = <1>;
333 intc: interrupt-controller@01c20400 {
334 compatible = "allwinner,sun4i-ic";
335 reg = <0x01c20400 0x400>;
336 interrupt-controller;
337 #interrupt-cells = <1>;
340 pio: pinctrl@01c20800 {
341 compatible = "allwinner,sun4i-a10-pinctrl";
342 reg = <0x01c20800 0x400>;
344 clocks = <&apb0_gates 5>;
346 interrupt-controller;
347 #address-cells = <1>;
351 uart0_pins_a: uart0@0 {
352 allwinner,pins = "PB22", "PB23";
353 allwinner,function = "uart0";
354 allwinner,drive = <0>;
355 allwinner,pull = <0>;
358 uart0_pins_b: uart0@1 {
359 allwinner,pins = "PF2", "PF4";
360 allwinner,function = "uart0";
361 allwinner,drive = <0>;
362 allwinner,pull = <0>;
365 uart1_pins_a: uart1@0 {
366 allwinner,pins = "PA10", "PA11";
367 allwinner,function = "uart1";
368 allwinner,drive = <0>;
369 allwinner,pull = <0>;
372 i2c0_pins_a: i2c0@0 {
373 allwinner,pins = "PB0", "PB1";
374 allwinner,function = "i2c0";
375 allwinner,drive = <0>;
376 allwinner,pull = <0>;
379 i2c1_pins_a: i2c1@0 {
380 allwinner,pins = "PB18", "PB19";
381 allwinner,function = "i2c1";
382 allwinner,drive = <0>;
383 allwinner,pull = <0>;
386 i2c2_pins_a: i2c2@0 {
387 allwinner,pins = "PB20", "PB21";
388 allwinner,function = "i2c2";
389 allwinner,drive = <0>;
390 allwinner,pull = <0>;
393 emac_pins_a: emac0@0 {
394 allwinner,pins = "PA0", "PA1", "PA2",
395 "PA3", "PA4", "PA5", "PA6",
396 "PA7", "PA8", "PA9", "PA10",
397 "PA11", "PA12", "PA13", "PA14",
399 allwinner,function = "emac";
400 allwinner,drive = <0>;
401 allwinner,pull = <0>;
406 compatible = "allwinner,sun4i-timer";
407 reg = <0x01c20c00 0x90>;
412 wdt: watchdog@01c20c90 {
413 compatible = "allwinner,sun4i-wdt";
414 reg = <0x01c20c90 0x10>;
418 compatible = "allwinner,sun4i-rtc";
419 reg = <0x01c20d00 0x20>;
423 sid: eeprom@01c23800 {
424 compatible = "allwinner,sun4i-sid";
425 reg = <0x01c23800 0x10>;
429 compatible = "allwinner,sun4i-a10-ts";
430 reg = <0x01c25000 0x100>;
434 uart0: serial@01c28000 {
435 compatible = "snps,dw-apb-uart";
436 reg = <0x01c28000 0x400>;
440 clocks = <&apb1_gates 16>;
444 uart1: serial@01c28400 {
445 compatible = "snps,dw-apb-uart";
446 reg = <0x01c28400 0x400>;
450 clocks = <&apb1_gates 17>;
454 uart2: serial@01c28800 {
455 compatible = "snps,dw-apb-uart";
456 reg = <0x01c28800 0x400>;
460 clocks = <&apb1_gates 18>;
464 uart3: serial@01c28c00 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0x01c28c00 0x400>;
470 clocks = <&apb1_gates 19>;
474 uart4: serial@01c29000 {
475 compatible = "snps,dw-apb-uart";
476 reg = <0x01c29000 0x400>;
480 clocks = <&apb1_gates 20>;
484 uart5: serial@01c29400 {
485 compatible = "snps,dw-apb-uart";
486 reg = <0x01c29400 0x400>;
490 clocks = <&apb1_gates 21>;
494 uart6: serial@01c29800 {
495 compatible = "snps,dw-apb-uart";
496 reg = <0x01c29800 0x400>;
500 clocks = <&apb1_gates 22>;
504 uart7: serial@01c29c00 {
505 compatible = "snps,dw-apb-uart";
506 reg = <0x01c29c00 0x400>;
510 clocks = <&apb1_gates 23>;
515 compatible = "allwinner,sun4i-i2c";
516 reg = <0x01c2ac00 0x400>;
518 clocks = <&apb1_gates 0>;
519 clock-frequency = <100000>;
524 compatible = "allwinner,sun4i-i2c";
525 reg = <0x01c2b000 0x400>;
527 clocks = <&apb1_gates 1>;
528 clock-frequency = <100000>;
533 compatible = "allwinner,sun4i-i2c";
534 reg = <0x01c2b400 0x400>;
536 clocks = <&apb1_gates 2>;
537 clock-frequency = <100000>;