2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
52 interrupt-parent = <&intc>;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
110 #address-cells = <1>;
114 compatible = "arm,cortex-a8";
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
125 #cooling-cells = <2>;
126 cooling-min-level = <0>;
127 cooling-max-level = <3>;
134 polling-delay-passive = <250>;
135 polling-delay = <1000>;
136 thermal-sensors = <&rtp>;
140 trip = <&cpu_alert0>;
141 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
146 cpu_alert0: cpu-alert0 {
148 temperature = <850000>;
155 temperature = <100000>;
164 #address-cells = <1>;
170 compatible = "fixed-clock";
171 clock-frequency = <24000000>;
172 clock-output-names = "osc24M";
177 compatible = "fixed-clock";
178 clock-frequency = <32768>;
179 clock-output-names = "osc32k";
184 compatible = "allwinner,sun4i-a10-display-engine";
185 allwinner,pipelines = <&fe0>, <&fe1>;
190 compatible = "simple-bus";
191 #address-cells = <1>;
195 sram-controller@1c00000 {
196 compatible = "allwinner,sun4i-a10-sram-controller";
197 reg = <0x01c00000 0x30>;
198 #address-cells = <1>;
203 compatible = "mmio-sram";
204 reg = <0x00000000 0xc000>;
205 #address-cells = <1>;
207 ranges = <0 0x00000000 0xc000>;
209 emac_sram: sram-section@8000 {
210 compatible = "allwinner,sun4i-a10-sram-a3-a4";
211 reg = <0x8000 0x4000>;
217 compatible = "mmio-sram";
218 reg = <0x00010000 0x1000>;
219 #address-cells = <1>;
221 ranges = <0 0x00010000 0x1000>;
223 otg_sram: sram-section@0 {
224 compatible = "allwinner,sun4i-a10-sram-d";
225 reg = <0x0000 0x1000>;
231 dma: dma-controller@1c02000 {
232 compatible = "allwinner,sun4i-a10-dma";
233 reg = <0x01c02000 0x1000>;
235 clocks = <&ccu CLK_AHB_DMA>;
240 compatible = "allwinner,sun4i-a10-nand";
241 reg = <0x01c03000 0x1000>;
243 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
244 clock-names = "ahb", "mod";
245 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
248 #address-cells = <1>;
253 compatible = "allwinner,sun4i-a10-spi";
254 reg = <0x01c05000 0x1000>;
256 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
257 clock-names = "ahb", "mod";
258 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
259 <&dma SUN4I_DMA_DEDICATED 26>;
260 dma-names = "rx", "tx";
262 #address-cells = <1>;
267 compatible = "allwinner,sun4i-a10-spi";
268 reg = <0x01c06000 0x1000>;
270 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
271 clock-names = "ahb", "mod";
272 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
273 <&dma SUN4I_DMA_DEDICATED 8>;
274 dma-names = "rx", "tx";
275 pinctrl-names = "default";
276 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
278 #address-cells = <1>;
282 emac: ethernet@1c0b000 {
283 compatible = "allwinner,sun4i-a10-emac";
284 reg = <0x01c0b000 0x1000>;
286 clocks = <&ccu CLK_AHB_EMAC>;
287 allwinner,sram = <&emac_sram 1>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&emac_pins>;
294 compatible = "allwinner,sun4i-a10-mdio";
295 reg = <0x01c0b080 0x14>;
297 #address-cells = <1>;
301 tcon0: lcd-controller@1c0c000 {
302 compatible = "allwinner,sun4i-a10-tcon";
303 reg = <0x01c0c000 0x1000>;
305 resets = <&ccu RST_TCON0>;
307 clocks = <&ccu CLK_AHB_LCD0>,
308 <&ccu CLK_TCON0_CH0>,
309 <&ccu CLK_TCON0_CH1>;
313 clock-output-names = "tcon0-pixel-clock";
314 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
317 #address-cells = <1>;
321 #address-cells = <1>;
325 tcon0_in_be0: endpoint@0 {
327 remote-endpoint = <&be0_out_tcon0>;
330 tcon0_in_be1: endpoint@1 {
332 remote-endpoint = <&be1_out_tcon0>;
337 #address-cells = <1>;
341 tcon0_out_hdmi: endpoint@1 {
343 remote-endpoint = <&hdmi_in_tcon0>;
344 allwinner,tcon-channel = <1>;
350 tcon1: lcd-controller@1c0d000 {
351 compatible = "allwinner,sun4i-a10-tcon";
352 reg = <0x01c0d000 0x1000>;
354 resets = <&ccu RST_TCON1>;
356 clocks = <&ccu CLK_AHB_LCD1>,
357 <&ccu CLK_TCON1_CH0>,
358 <&ccu CLK_TCON1_CH1>;
362 clock-output-names = "tcon1-pixel-clock";
363 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
366 #address-cells = <1>;
370 #address-cells = <1>;
374 tcon1_in_be0: endpoint@0 {
376 remote-endpoint = <&be0_out_tcon1>;
379 tcon1_in_be1: endpoint@1 {
381 remote-endpoint = <&be1_out_tcon1>;
386 #address-cells = <1>;
390 tcon1_out_hdmi: endpoint@1 {
392 remote-endpoint = <&hdmi_in_tcon1>;
393 allwinner,tcon-channel = <1>;
400 compatible = "allwinner,sun4i-a10-mmc";
401 reg = <0x01c0f000 0x1000>;
402 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
403 clock-names = "ahb", "mmc";
405 pinctrl-names = "default";
406 pinctrl-0 = <&mmc0_pins>;
408 #address-cells = <1>;
413 compatible = "allwinner,sun4i-a10-mmc";
414 reg = <0x01c10000 0x1000>;
415 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
416 clock-names = "ahb", "mmc";
419 #address-cells = <1>;
424 compatible = "allwinner,sun4i-a10-mmc";
425 reg = <0x01c11000 0x1000>;
426 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
427 clock-names = "ahb", "mmc";
430 #address-cells = <1>;
435 compatible = "allwinner,sun4i-a10-mmc";
436 reg = <0x01c12000 0x1000>;
437 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
438 clock-names = "ahb", "mmc";
441 #address-cells = <1>;
445 usb_otg: usb@1c13000 {
446 compatible = "allwinner,sun4i-a10-musb";
447 reg = <0x01c13000 0x0400>;
448 clocks = <&ccu CLK_AHB_OTG>;
450 interrupt-names = "mc";
453 extcon = <&usbphy 0>;
454 allwinner,sram = <&otg_sram 1>;
458 usbphy: phy@1c13400 {
460 compatible = "allwinner,sun4i-a10-usb-phy";
461 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
462 reg-names = "phy_ctrl", "pmu1", "pmu2";
463 clocks = <&ccu CLK_USB_PHY>;
464 clock-names = "usb_phy";
465 resets = <&ccu RST_USB_PHY0>,
468 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
473 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
474 reg = <0x01c14000 0x100>;
476 clocks = <&ccu CLK_AHB_EHCI0>;
483 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
484 reg = <0x01c14400 0x100>;
486 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
492 crypto: crypto-engine@1c15000 {
493 compatible = "allwinner,sun4i-a10-crypto";
494 reg = <0x01c15000 0x1000>;
496 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
497 clock-names = "ahb", "mod";
501 compatible = "allwinner,sun4i-a10-hdmi";
502 reg = <0x01c16000 0x1000>;
504 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
507 clock-names = "ahb", "mod", "pll-0", "pll-1";
508 dmas = <&dma SUN4I_DMA_NORMAL 16>,
509 <&dma SUN4I_DMA_NORMAL 16>,
510 <&dma SUN4I_DMA_DEDICATED 24>;
511 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
515 #address-cells = <1>;
519 #address-cells = <1>;
523 hdmi_in_tcon0: endpoint@0 {
525 remote-endpoint = <&tcon0_out_hdmi>;
528 hdmi_in_tcon1: endpoint@1 {
530 remote-endpoint = <&tcon1_out_hdmi>;
535 #address-cells = <1>;
543 compatible = "allwinner,sun4i-a10-spi";
544 reg = <0x01c17000 0x1000>;
546 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
547 clock-names = "ahb", "mod";
548 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
549 <&dma SUN4I_DMA_DEDICATED 28>;
550 dma-names = "rx", "tx";
552 #address-cells = <1>;
557 compatible = "allwinner,sun4i-a10-ahci";
558 reg = <0x01c18000 0x1000>;
560 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
565 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
566 reg = <0x01c1c000 0x100>;
568 clocks = <&ccu CLK_AHB_EHCI1>;
575 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
576 reg = <0x01c1c400 0x100>;
578 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
585 compatible = "allwinner,sun4i-a10-spi";
586 reg = <0x01c1f000 0x1000>;
588 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
589 clock-names = "ahb", "mod";
590 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
591 <&dma SUN4I_DMA_DEDICATED 30>;
592 dma-names = "rx", "tx";
594 #address-cells = <1>;
599 compatible = "allwinner,sun4i-a10-ccu";
600 reg = <0x01c20000 0x400>;
601 clocks = <&osc24M>, <&osc32k>;
602 clock-names = "hosc", "losc";
607 intc: interrupt-controller@1c20400 {
608 compatible = "allwinner,sun4i-a10-ic";
609 reg = <0x01c20400 0x400>;
610 interrupt-controller;
611 #interrupt-cells = <1>;
614 pio: pinctrl@1c20800 {
615 compatible = "allwinner,sun4i-a10-pinctrl";
616 reg = <0x01c20800 0x400>;
618 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
619 clock-names = "apb", "hosc", "losc";
621 interrupt-controller;
622 #interrupt-cells = <3>;
625 can0_ph_pins: can0-ph-pins {
626 pins = "PH20", "PH21";
630 emac_pins: emac0-pins {
631 pins = "PA0", "PA1", "PA2",
632 "PA3", "PA4", "PA5", "PA6",
633 "PA7", "PA8", "PA9", "PA10",
634 "PA11", "PA12", "PA13", "PA14",
639 i2c0_pins: i2c0-pins {
644 i2c1_pins: i2c1-pins {
645 pins = "PB18", "PB19";
649 i2c2_pins: i2c2-pins {
650 pins = "PB20", "PB21";
654 ir0_rx_pins: ir0-rx-pin {
659 ir0_tx_pins: ir0-tx-pin {
664 ir1_rx_pins: ir1-rx-pin {
669 ir1_tx_pins: ir1-tx-pin {
674 mmc0_pins: mmc0-pins {
675 pins = "PF0", "PF1", "PF2",
678 drive-strength = <30>;
682 ps2_ch0_pins: ps2-ch0-pins {
683 pins = "PI20", "PI21";
687 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
688 pins = "PH12", "PH13";
702 spdif_tx_pin: spdif-tx-pin {
708 spi0_pi_pins: spi0-pi-pins {
709 pins = "PI11", "PI12", "PI13";
713 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
718 spi1_pins: spi1-pins {
719 pins = "PI17", "PI18", "PI19";
723 spi1_cs0_pin: spi1-cs0-pin {
728 spi2_pb_pins: spi2-pb-pins {
729 pins = "PB15", "PB16", "PB17";
733 spi2_pc_pins: spi2-pc-pins {
734 pins = "PC20", "PC21", "PC22";
738 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
743 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
748 uart0_pb_pins: uart0-pb-pins {
749 pins = "PB22", "PB23";
753 uart0_pf_pins: uart0-pf-pins {
758 uart1_pins: uart1-pins {
759 pins = "PA10", "PA11";
765 compatible = "allwinner,sun4i-a10-timer";
766 reg = <0x01c20c00 0x90>;
771 wdt: watchdog@1c20c90 {
772 compatible = "allwinner,sun4i-a10-wdt";
773 reg = <0x01c20c90 0x10>;
777 compatible = "allwinner,sun4i-a10-rtc";
778 reg = <0x01c20d00 0x20>;
783 compatible = "allwinner,sun4i-a10-pwm";
784 reg = <0x01c20e00 0xc>;
790 spdif: spdif@1c21000 {
791 #sound-dai-cells = <0>;
792 compatible = "allwinner,sun4i-a10-spdif";
793 reg = <0x01c21000 0x400>;
795 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
796 clock-names = "apb", "spdif";
797 dmas = <&dma SUN4I_DMA_NORMAL 2>,
798 <&dma SUN4I_DMA_NORMAL 2>;
799 dma-names = "rx", "tx";
804 compatible = "allwinner,sun4i-a10-ir";
805 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
806 clock-names = "apb", "ir";
808 reg = <0x01c21800 0x40>;
813 compatible = "allwinner,sun4i-a10-ir";
814 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
815 clock-names = "apb", "ir";
817 reg = <0x01c21c00 0x40>;
822 #sound-dai-cells = <0>;
823 compatible = "allwinner,sun4i-a10-i2s";
824 reg = <0x01c22400 0x400>;
826 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
827 clock-names = "apb", "mod";
828 dmas = <&dma SUN4I_DMA_NORMAL 3>,
829 <&dma SUN4I_DMA_NORMAL 3>;
830 dma-names = "rx", "tx";
834 lradc: lradc@1c22800 {
835 compatible = "allwinner,sun4i-a10-lradc-keys";
836 reg = <0x01c22800 0x100>;
841 codec: codec@1c22c00 {
842 #sound-dai-cells = <0>;
843 compatible = "allwinner,sun4i-a10-codec";
844 reg = <0x01c22c00 0x40>;
846 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
847 clock-names = "apb", "codec";
848 dmas = <&dma SUN4I_DMA_NORMAL 19>,
849 <&dma SUN4I_DMA_NORMAL 19>;
850 dma-names = "rx", "tx";
854 sid: eeprom@1c23800 {
855 compatible = "allwinner,sun4i-a10-sid";
856 reg = <0x01c23800 0x10>;
860 compatible = "allwinner,sun4i-a10-ts";
861 reg = <0x01c25000 0x100>;
863 #thermal-sensor-cells = <0>;
866 uart0: serial@1c28000 {
867 compatible = "snps,dw-apb-uart";
868 reg = <0x01c28000 0x400>;
872 clocks = <&ccu CLK_APB1_UART0>;
876 uart1: serial@1c28400 {
877 compatible = "snps,dw-apb-uart";
878 reg = <0x01c28400 0x400>;
882 clocks = <&ccu CLK_APB1_UART1>;
886 uart2: serial@1c28800 {
887 compatible = "snps,dw-apb-uart";
888 reg = <0x01c28800 0x400>;
892 clocks = <&ccu CLK_APB1_UART2>;
896 uart3: serial@1c28c00 {
897 compatible = "snps,dw-apb-uart";
898 reg = <0x01c28c00 0x400>;
902 clocks = <&ccu CLK_APB1_UART3>;
906 uart4: serial@1c29000 {
907 compatible = "snps,dw-apb-uart";
908 reg = <0x01c29000 0x400>;
912 clocks = <&ccu CLK_APB1_UART4>;
916 uart5: serial@1c29400 {
917 compatible = "snps,dw-apb-uart";
918 reg = <0x01c29400 0x400>;
922 clocks = <&ccu CLK_APB1_UART5>;
926 uart6: serial@1c29800 {
927 compatible = "snps,dw-apb-uart";
928 reg = <0x01c29800 0x400>;
932 clocks = <&ccu CLK_APB1_UART6>;
936 uart7: serial@1c29c00 {
937 compatible = "snps,dw-apb-uart";
938 reg = <0x01c29c00 0x400>;
942 clocks = <&ccu CLK_APB1_UART7>;
947 compatible = "allwinner,sun4i-a10-ps2";
948 reg = <0x01c2a000 0x400>;
950 clocks = <&ccu CLK_APB1_PS20>;
955 compatible = "allwinner,sun4i-a10-ps2";
956 reg = <0x01c2a400 0x400>;
958 clocks = <&ccu CLK_APB1_PS21>;
963 compatible = "allwinner,sun4i-a10-i2c";
964 reg = <0x01c2ac00 0x400>;
966 clocks = <&ccu CLK_APB1_I2C0>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&i2c0_pins>;
970 #address-cells = <1>;
975 compatible = "allwinner,sun4i-a10-i2c";
976 reg = <0x01c2b000 0x400>;
978 clocks = <&ccu CLK_APB1_I2C1>;
979 pinctrl-names = "default";
980 pinctrl-0 = <&i2c1_pins>;
982 #address-cells = <1>;
987 compatible = "allwinner,sun4i-a10-i2c";
988 reg = <0x01c2b400 0x400>;
990 clocks = <&ccu CLK_APB1_I2C2>;
991 pinctrl-names = "default";
992 pinctrl-0 = <&i2c2_pins>;
994 #address-cells = <1>;
999 compatible = "allwinner,sun4i-a10-can";
1000 reg = <0x01c2bc00 0x400>;
1002 clocks = <&ccu CLK_APB1_CAN>;
1003 status = "disabled";
1006 fe0: display-frontend@1e00000 {
1007 compatible = "allwinner,sun4i-a10-display-frontend";
1008 reg = <0x01e00000 0x20000>;
1010 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1011 <&ccu CLK_DRAM_DE_FE0>;
1012 clock-names = "ahb", "mod",
1014 resets = <&ccu RST_DE_FE0>;
1017 #address-cells = <1>;
1021 #address-cells = <1>;
1025 fe0_out_be0: endpoint@0 {
1027 remote-endpoint = <&be0_in_fe0>;
1030 fe0_out_be1: endpoint@1 {
1032 remote-endpoint = <&be1_in_fe0>;
1038 fe1: display-frontend@1e20000 {
1039 compatible = "allwinner,sun4i-a10-display-frontend";
1040 reg = <0x01e20000 0x20000>;
1042 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1043 <&ccu CLK_DRAM_DE_FE1>;
1044 clock-names = "ahb", "mod",
1046 resets = <&ccu RST_DE_FE1>;
1049 #address-cells = <1>;
1053 #address-cells = <1>;
1057 fe1_out_be0: endpoint@0 {
1059 remote-endpoint = <&be0_in_fe1>;
1062 fe1_out_be1: endpoint@1 {
1064 remote-endpoint = <&be1_in_fe1>;
1070 be1: display-backend@1e40000 {
1071 compatible = "allwinner,sun4i-a10-display-backend";
1072 reg = <0x01e40000 0x10000>;
1074 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1075 <&ccu CLK_DRAM_DE_BE1>;
1076 clock-names = "ahb", "mod",
1078 resets = <&ccu RST_DE_BE1>;
1081 #address-cells = <1>;
1085 #address-cells = <1>;
1089 be1_in_fe0: endpoint@0 {
1091 remote-endpoint = <&fe0_out_be1>;
1094 be1_in_fe1: endpoint@1 {
1096 remote-endpoint = <&fe1_out_be1>;
1101 #address-cells = <1>;
1105 be1_out_tcon0: endpoint@0 {
1107 remote-endpoint = <&tcon1_in_be0>;
1110 be1_out_tcon1: endpoint@1 {
1112 remote-endpoint = <&tcon1_in_be1>;
1118 be0: display-backend@1e60000 {
1119 compatible = "allwinner,sun4i-a10-display-backend";
1120 reg = <0x01e60000 0x10000>;
1122 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1123 <&ccu CLK_DRAM_DE_BE0>;
1124 clock-names = "ahb", "mod",
1126 resets = <&ccu RST_DE_BE0>;
1129 #address-cells = <1>;
1133 #address-cells = <1>;
1137 be0_in_fe0: endpoint@0 {
1139 remote-endpoint = <&fe0_out_be0>;
1142 be0_in_fe1: endpoint@1 {
1144 remote-endpoint = <&fe1_out_be0>;
1149 #address-cells = <1>;
1153 be0_out_tcon0: endpoint@0 {
1155 remote-endpoint = <&tcon0_in_be0>;
1158 be0_out_tcon1: endpoint@1 {
1160 remote-endpoint = <&tcon1_in_be0>;