2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include "skeleton.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
52 interrupt-parent = <&intc>;
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
68 <&ahb_gates 44>, <&de_be0_clk>,
69 <&tcon0_ch1_clk>, <&dram_gates 26>;
74 compatible = "allwinner,simple-framebuffer",
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
78 <&ahb_gates 44>, <&ahb_gates 46>,
79 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
80 <&dram_gates 25>, <&dram_gates 26>;
85 compatible = "allwinner,simple-framebuffer",
87 allwinner,pipeline = "de_fe0-de_be0-lcd0";
88 clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
89 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
90 <&dram_gates 25>, <&dram_gates 26>;
95 compatible = "allwinner,simple-framebuffer",
97 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
98 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
99 <&ahb_gates 44>, <&ahb_gates 46>,
100 <&de_be0_clk>, <&de_fe0_clk>,
101 <&tcon0_ch1_clk>, <&dram_gates 5>,
102 <&dram_gates 25>, <&dram_gates 26>;
108 #address-cells = <1>;
112 compatible = "arm,cortex-a8";
115 clock-latency = <244144>; /* 8 32k periods */
123 #cooling-cells = <2>;
124 cooling-min-level = <0>;
125 cooling-max-level = <3>;
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 cpu_alert0: cpu_alert0 {
146 temperature = <850000>;
153 temperature = <100000>;
162 reg = <0x40000000 0x80000000>;
166 #address-cells = <1>;
171 * This is a dummy clock, to be used as placeholder on
172 * other mux clocks when a specific parent clock is not
173 * yet implemented. It should be dropped when the driver
178 compatible = "fixed-clock";
179 clock-frequency = <0>;
182 osc24M: clk@01c20050 {
184 compatible = "allwinner,sun4i-a10-osc-clk";
185 reg = <0x01c20050 0x4>;
186 clock-frequency = <24000000>;
187 clock-output-names = "osc24M";
191 compatible = "fixed-factor-clock";
196 clock-output-names = "osc3M";
201 compatible = "fixed-clock";
202 clock-frequency = <32768>;
203 clock-output-names = "osc32k";
208 compatible = "allwinner,sun4i-a10-pll1-clk";
209 reg = <0x01c20000 0x4>;
211 clock-output-names = "pll1";
216 compatible = "allwinner,sun4i-a10-pll2-clk";
217 reg = <0x01c20008 0x8>;
219 clock-output-names = "pll2-1x", "pll2-2x",
220 "pll2-4x", "pll2-8x";
225 compatible = "allwinner,sun4i-a10-pll3-clk";
226 reg = <0x01c20010 0x4>;
228 clock-output-names = "pll3";
232 compatible = "fixed-factor-clock";
237 clock-output-names = "pll3-2x";
242 compatible = "allwinner,sun4i-a10-pll1-clk";
243 reg = <0x01c20018 0x4>;
245 clock-output-names = "pll4";
250 compatible = "allwinner,sun4i-a10-pll5-clk";
251 reg = <0x01c20020 0x4>;
253 clock-output-names = "pll5_ddr", "pll5_other";
258 compatible = "allwinner,sun4i-a10-pll6-clk";
259 reg = <0x01c20028 0x4>;
261 clock-output-names = "pll6_sata", "pll6_other", "pll6";
266 compatible = "allwinner,sun4i-a10-pll3-clk";
267 reg = <0x01c20030 0x4>;
269 clock-output-names = "pll7";
273 compatible = "fixed-factor-clock";
278 clock-output-names = "pll7-2x";
284 compatible = "allwinner,sun4i-a10-cpu-clk";
285 reg = <0x01c20054 0x4>;
286 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
287 clock-output-names = "cpu";
292 compatible = "allwinner,sun4i-a10-axi-clk";
293 reg = <0x01c20054 0x4>;
295 clock-output-names = "axi";
298 axi_gates: clk@01c2005c {
300 compatible = "allwinner,sun4i-a10-axi-gates-clk";
301 reg = <0x01c2005c 0x4>;
304 clock-output-names = "axi_dram";
309 compatible = "allwinner,sun4i-a10-ahb-clk";
310 reg = <0x01c20054 0x4>;
312 clock-output-names = "ahb";
315 ahb_gates: clk@01c20060 {
317 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
318 reg = <0x01c20060 0x8>;
320 clock-indices = <0>, <1>,
335 clock-output-names = "ahb_usb0", "ahb_ehci0",
336 "ahb_ohci0", "ahb_ehci1",
337 "ahb_ohci1", "ahb_ss", "ahb_dma",
338 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
339 "ahb_mmc2", "ahb_mmc3", "ahb_ms",
340 "ahb_nand", "ahb_sdram", "ahb_ace",
341 "ahb_emac", "ahb_ts", "ahb_spi0",
342 "ahb_spi1", "ahb_spi2", "ahb_spi3",
343 "ahb_pata", "ahb_sata", "ahb_gps",
344 "ahb_ve", "ahb_tvd", "ahb_tve0",
345 "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
346 "ahb_csi0", "ahb_csi1", "ahb_hdmi",
347 "ahb_de_be0", "ahb_de_be1",
348 "ahb_de_fe0", "ahb_de_fe1",
349 "ahb_mp", "ahb_mali400";
352 apb0: apb0@01c20054 {
354 compatible = "allwinner,sun4i-a10-apb0-clk";
355 reg = <0x01c20054 0x4>;
357 clock-output-names = "apb0";
360 apb0_gates: clk@01c20068 {
362 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
363 reg = <0x01c20068 0x4>;
365 clock-indices = <0>, <1>,
369 clock-output-names = "apb0_codec", "apb0_spdif",
370 "apb0_ac97", "apb0_iis",
371 "apb0_pio", "apb0_ir0",
372 "apb0_ir1", "apb0_keypad";
377 compatible = "allwinner,sun4i-a10-apb1-clk";
378 reg = <0x01c20058 0x4>;
379 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
380 clock-output-names = "apb1";
383 apb1_gates: clk@01c2006c {
385 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
386 reg = <0x01c2006c 0x4>;
388 clock-indices = <0>, <1>,
396 clock-output-names = "apb1_i2c0", "apb1_i2c1",
397 "apb1_i2c2", "apb1_can",
398 "apb1_scr", "apb1_ps20",
399 "apb1_ps21", "apb1_uart0",
400 "apb1_uart1", "apb1_uart2",
401 "apb1_uart3", "apb1_uart4",
402 "apb1_uart5", "apb1_uart6",
406 nand_clk: clk@01c20080 {
408 compatible = "allwinner,sun4i-a10-mod0-clk";
409 reg = <0x01c20080 0x4>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
411 clock-output-names = "nand";
414 ms_clk: clk@01c20084 {
416 compatible = "allwinner,sun4i-a10-mod0-clk";
417 reg = <0x01c20084 0x4>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clock-output-names = "ms";
422 mmc0_clk: clk@01c20088 {
424 compatible = "allwinner,sun4i-a10-mmc-clk";
425 reg = <0x01c20088 0x4>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clock-output-names = "mmc0",
432 mmc1_clk: clk@01c2008c {
434 compatible = "allwinner,sun4i-a10-mmc-clk";
435 reg = <0x01c2008c 0x4>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clock-output-names = "mmc1",
442 mmc2_clk: clk@01c20090 {
444 compatible = "allwinner,sun4i-a10-mmc-clk";
445 reg = <0x01c20090 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "mmc2",
452 mmc3_clk: clk@01c20094 {
454 compatible = "allwinner,sun4i-a10-mmc-clk";
455 reg = <0x01c20094 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "mmc3",
462 ts_clk: clk@01c20098 {
464 compatible = "allwinner,sun4i-a10-mod0-clk";
465 reg = <0x01c20098 0x4>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
467 clock-output-names = "ts";
470 ss_clk: clk@01c2009c {
472 compatible = "allwinner,sun4i-a10-mod0-clk";
473 reg = <0x01c2009c 0x4>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clock-output-names = "ss";
478 spi0_clk: clk@01c200a0 {
480 compatible = "allwinner,sun4i-a10-mod0-clk";
481 reg = <0x01c200a0 0x4>;
482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
483 clock-output-names = "spi0";
486 spi1_clk: clk@01c200a4 {
488 compatible = "allwinner,sun4i-a10-mod0-clk";
489 reg = <0x01c200a4 0x4>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
491 clock-output-names = "spi1";
494 spi2_clk: clk@01c200a8 {
496 compatible = "allwinner,sun4i-a10-mod0-clk";
497 reg = <0x01c200a8 0x4>;
498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
499 clock-output-names = "spi2";
502 pata_clk: clk@01c200ac {
504 compatible = "allwinner,sun4i-a10-mod0-clk";
505 reg = <0x01c200ac 0x4>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
507 clock-output-names = "pata";
510 ir0_clk: clk@01c200b0 {
512 compatible = "allwinner,sun4i-a10-mod0-clk";
513 reg = <0x01c200b0 0x4>;
514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
515 clock-output-names = "ir0";
518 ir1_clk: clk@01c200b4 {
520 compatible = "allwinner,sun4i-a10-mod0-clk";
521 reg = <0x01c200b4 0x4>;
522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
523 clock-output-names = "ir1";
526 spdif_clk: clk@01c200c0 {
528 compatible = "allwinner,sun4i-a10-mod1-clk";
529 reg = <0x01c200c0 0x4>;
530 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
531 <&pll2 SUN4I_A10_PLL2_4X>,
532 <&pll2 SUN4I_A10_PLL2_2X>,
533 <&pll2 SUN4I_A10_PLL2_1X>;
534 clock-output-names = "spdif";
537 usb_clk: clk@01c200cc {
540 compatible = "allwinner,sun4i-a10-usb-clk";
541 reg = <0x01c200cc 0x4>;
543 clock-output-names = "usb_ohci0", "usb_ohci1",
547 spi3_clk: clk@01c200d4 {
549 compatible = "allwinner,sun4i-a10-mod0-clk";
550 reg = <0x01c200d4 0x4>;
551 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
552 clock-output-names = "spi3";
555 dram_gates: clk@01c20100 {
557 compatible = "allwinner,sun4i-a10-dram-gates-clk";
558 reg = <0x01c20100 0x4>;
569 clock-output-names = "dram_ve",
570 "dram_csi0", "dram_csi1",
573 "dram_tve0", "dram_tve1",
575 "dram_de_fe1", "dram_de_fe0",
576 "dram_de_be0", "dram_de_be1",
577 "dram_de_mp", "dram_ace";
580 de_be0_clk: clk@01c20104 {
583 compatible = "allwinner,sun4i-a10-display-clk";
584 reg = <0x01c20104 0x4>;
585 clocks = <&pll3>, <&pll7>, <&pll5 1>;
586 clock-output-names = "de-be0";
589 de_be1_clk: clk@01c20108 {
592 compatible = "allwinner,sun4i-a10-display-clk";
593 reg = <0x01c20108 0x4>;
594 clocks = <&pll3>, <&pll7>, <&pll5 1>;
595 clock-output-names = "de-be1";
598 de_fe0_clk: clk@01c2010c {
601 compatible = "allwinner,sun4i-a10-display-clk";
602 reg = <0x01c2010c 0x4>;
603 clocks = <&pll3>, <&pll7>, <&pll5 1>;
604 clock-output-names = "de-fe0";
607 de_fe1_clk: clk@01c20110 {
610 compatible = "allwinner,sun4i-a10-display-clk";
611 reg = <0x01c20110 0x4>;
612 clocks = <&pll3>, <&pll7>, <&pll5 1>;
613 clock-output-names = "de-fe1";
617 tcon0_ch0_clk: clk@01c20118 {
620 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
621 reg = <0x01c20118 0x4>;
622 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
623 clock-output-names = "tcon0-ch0-sclk";
627 tcon1_ch0_clk: clk@01c2011c {
630 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
631 reg = <0x01c2011c 0x4>;
632 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
633 clock-output-names = "tcon1-ch0-sclk";
637 tcon0_ch1_clk: clk@01c2012c {
639 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
640 reg = <0x01c2012c 0x4>;
641 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
642 clock-output-names = "tcon0-ch1-sclk";
646 tcon1_ch1_clk: clk@01c20130 {
648 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
649 reg = <0x01c20130 0x4>;
650 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
651 clock-output-names = "tcon1-ch1-sclk";
655 ve_clk: clk@01c2013c {
658 compatible = "allwinner,sun4i-a10-ve-clk";
659 reg = <0x01c2013c 0x4>;
661 clock-output-names = "ve";
664 codec_clk: clk@01c20140 {
666 compatible = "allwinner,sun4i-a10-codec-clk";
667 reg = <0x01c20140 0x4>;
668 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
669 clock-output-names = "codec";
674 compatible = "simple-bus";
675 #address-cells = <1>;
679 sram-controller@01c00000 {
680 compatible = "allwinner,sun4i-a10-sram-controller";
681 reg = <0x01c00000 0x30>;
682 #address-cells = <1>;
686 sram_a: sram@00000000 {
687 compatible = "mmio-sram";
688 reg = <0x00000000 0xc000>;
689 #address-cells = <1>;
691 ranges = <0 0x00000000 0xc000>;
693 emac_sram: sram-section@8000 {
694 compatible = "allwinner,sun4i-a10-sram-a3-a4";
695 reg = <0x8000 0x4000>;
700 sram_d: sram@00010000 {
701 compatible = "mmio-sram";
702 reg = <0x00010000 0x1000>;
703 #address-cells = <1>;
705 ranges = <0 0x00010000 0x1000>;
707 otg_sram: sram-section@0000 {
708 compatible = "allwinner,sun4i-a10-sram-d";
709 reg = <0x0000 0x1000>;
715 dma: dma-controller@01c02000 {
716 compatible = "allwinner,sun4i-a10-dma";
717 reg = <0x01c02000 0x1000>;
719 clocks = <&ahb_gates 6>;
724 compatible = "allwinner,sun4i-a10-nand";
725 reg = <0x01c03000 0x1000>;
727 clocks = <&ahb_gates 13>, <&nand_clk>;
728 clock-names = "ahb", "mod";
729 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
732 #address-cells = <1>;
737 compatible = "allwinner,sun4i-a10-spi";
738 reg = <0x01c05000 0x1000>;
740 clocks = <&ahb_gates 20>, <&spi0_clk>;
741 clock-names = "ahb", "mod";
742 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
743 <&dma SUN4I_DMA_DEDICATED 26>;
744 dma-names = "rx", "tx";
746 #address-cells = <1>;
751 compatible = "allwinner,sun4i-a10-spi";
752 reg = <0x01c06000 0x1000>;
754 clocks = <&ahb_gates 21>, <&spi1_clk>;
755 clock-names = "ahb", "mod";
756 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
757 <&dma SUN4I_DMA_DEDICATED 8>;
758 dma-names = "rx", "tx";
760 #address-cells = <1>;
764 emac: ethernet@01c0b000 {
765 compatible = "allwinner,sun4i-a10-emac";
766 reg = <0x01c0b000 0x1000>;
768 clocks = <&ahb_gates 17>;
769 allwinner,sram = <&emac_sram 1>;
773 mdio: mdio@01c0b080 {
774 compatible = "allwinner,sun4i-a10-mdio";
775 reg = <0x01c0b080 0x14>;
777 #address-cells = <1>;
782 compatible = "allwinner,sun4i-a10-mmc";
783 reg = <0x01c0f000 0x1000>;
784 clocks = <&ahb_gates 8>,
794 #address-cells = <1>;
799 compatible = "allwinner,sun4i-a10-mmc";
800 reg = <0x01c10000 0x1000>;
801 clocks = <&ahb_gates 9>,
811 #address-cells = <1>;
816 compatible = "allwinner,sun4i-a10-mmc";
817 reg = <0x01c11000 0x1000>;
818 clocks = <&ahb_gates 10>,
828 #address-cells = <1>;
833 compatible = "allwinner,sun4i-a10-mmc";
834 reg = <0x01c12000 0x1000>;
835 clocks = <&ahb_gates 11>,
845 #address-cells = <1>;
849 usb_otg: usb@01c13000 {
850 compatible = "allwinner,sun4i-a10-musb";
851 reg = <0x01c13000 0x0400>;
852 clocks = <&ahb_gates 0>;
854 interrupt-names = "mc";
857 extcon = <&usbphy 0>;
858 allwinner,sram = <&otg_sram 1>;
862 usbphy: phy@01c13400 {
864 compatible = "allwinner,sun4i-a10-usb-phy";
865 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
866 reg-names = "phy_ctrl", "pmu1", "pmu2";
867 clocks = <&usb_clk 8>;
868 clock-names = "usb_phy";
869 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
870 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
874 ehci0: usb@01c14000 {
875 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
876 reg = <0x01c14000 0x100>;
878 clocks = <&ahb_gates 1>;
884 ohci0: usb@01c14400 {
885 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
886 reg = <0x01c14400 0x100>;
888 clocks = <&usb_clk 6>, <&ahb_gates 2>;
894 crypto: crypto-engine@01c15000 {
895 compatible = "allwinner,sun4i-a10-crypto";
896 reg = <0x01c15000 0x1000>;
898 clocks = <&ahb_gates 5>, <&ss_clk>;
899 clock-names = "ahb", "mod";
903 compatible = "allwinner,sun4i-a10-spi";
904 reg = <0x01c17000 0x1000>;
906 clocks = <&ahb_gates 22>, <&spi2_clk>;
907 clock-names = "ahb", "mod";
908 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
909 <&dma SUN4I_DMA_DEDICATED 28>;
910 dma-names = "rx", "tx";
912 #address-cells = <1>;
916 ahci: sata@01c18000 {
917 compatible = "allwinner,sun4i-a10-ahci";
918 reg = <0x01c18000 0x1000>;
920 clocks = <&pll6 0>, <&ahb_gates 25>;
924 ehci1: usb@01c1c000 {
925 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
926 reg = <0x01c1c000 0x100>;
928 clocks = <&ahb_gates 3>;
934 ohci1: usb@01c1c400 {
935 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
936 reg = <0x01c1c400 0x100>;
938 clocks = <&usb_clk 7>, <&ahb_gates 4>;
945 compatible = "allwinner,sun4i-a10-spi";
946 reg = <0x01c1f000 0x1000>;
948 clocks = <&ahb_gates 23>, <&spi3_clk>;
949 clock-names = "ahb", "mod";
950 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
951 <&dma SUN4I_DMA_DEDICATED 30>;
952 dma-names = "rx", "tx";
954 #address-cells = <1>;
958 intc: interrupt-controller@01c20400 {
959 compatible = "allwinner,sun4i-a10-ic";
960 reg = <0x01c20400 0x400>;
961 interrupt-controller;
962 #interrupt-cells = <1>;
965 pio: pinctrl@01c20800 {
966 compatible = "allwinner,sun4i-a10-pinctrl";
967 reg = <0x01c20800 0x400>;
969 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
970 clock-names = "apb", "hosc", "losc";
972 interrupt-controller;
973 #interrupt-cells = <3>;
976 can0_pins_a: can0@0 {
977 pins = "PH20", "PH21";
981 emac_pins_a: emac0@0 {
982 pins = "PA0", "PA1", "PA2",
983 "PA3", "PA4", "PA5", "PA6",
984 "PA7", "PA8", "PA9", "PA10",
985 "PA11", "PA12", "PA13", "PA14",
990 i2c0_pins_a: i2c0@0 {
995 i2c1_pins_a: i2c1@0 {
996 pins = "PB18", "PB19";
1000 i2c2_pins_a: i2c2@0 {
1001 pins = "PB20", "PB21";
1005 ir0_rx_pins_a: ir0@0 {
1010 ir0_tx_pins_a: ir0@1 {
1015 ir1_rx_pins_a: ir1@0 {
1020 ir1_tx_pins_a: ir1@1 {
1025 mmc0_pins_a: mmc0@0 {
1026 pins = "PF0", "PF1", "PF2",
1027 "PF3", "PF4", "PF5";
1029 drive-strength = <30>;
1033 ps20_pins_a: ps20@0 {
1034 pins = "PI20", "PI21";
1038 ps21_pins_a: ps21@0 {
1039 pins = "PH12", "PH13";
1043 pwm0_pins_a: pwm0@0 {
1048 pwm1_pins_a: pwm1@0 {
1053 spdif_tx_pins_a: spdif@0 {
1059 spi0_pins_a: spi0@0 {
1060 pins = "PI11", "PI12", "PI13";
1064 spi0_cs0_pins_a: spi0_cs0@0 {
1069 spi1_pins_a: spi1@0 {
1070 pins = "PI17", "PI18", "PI19";
1074 spi1_cs0_pins_a: spi1_cs0@0 {
1079 spi2_pins_a: spi2@0 {
1080 pins = "PC20", "PC21", "PC22";
1084 spi2_pins_b: spi2@1 {
1085 pins = "PB15", "PB16", "PB17";
1089 spi2_cs0_pins_a: spi2_cs0@0 {
1094 spi2_cs0_pins_b: spi2_cs0@1 {
1099 uart0_pins_a: uart0@0 {
1100 pins = "PB22", "PB23";
1104 uart0_pins_b: uart0@1 {
1105 pins = "PF2", "PF4";
1109 uart1_pins_a: uart1@0 {
1110 pins = "PA10", "PA11";
1116 compatible = "allwinner,sun4i-a10-timer";
1117 reg = <0x01c20c00 0x90>;
1122 wdt: watchdog@01c20c90 {
1123 compatible = "allwinner,sun4i-a10-wdt";
1124 reg = <0x01c20c90 0x10>;
1128 compatible = "allwinner,sun4i-a10-rtc";
1129 reg = <0x01c20d00 0x20>;
1134 compatible = "allwinner,sun4i-a10-pwm";
1135 reg = <0x01c20e00 0xc>;
1138 status = "disabled";
1141 spdif: spdif@01c21000 {
1142 #sound-dai-cells = <0>;
1143 compatible = "allwinner,sun4i-a10-spdif";
1144 reg = <0x01c21000 0x400>;
1146 clocks = <&apb0_gates 1>, <&spdif_clk>;
1147 clock-names = "apb", "spdif";
1148 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1149 <&dma SUN4I_DMA_NORMAL 2>;
1150 dma-names = "rx", "tx";
1151 status = "disabled";
1155 compatible = "allwinner,sun4i-a10-ir";
1156 clocks = <&apb0_gates 6>, <&ir0_clk>;
1157 clock-names = "apb", "ir";
1159 reg = <0x01c21800 0x40>;
1160 status = "disabled";
1164 compatible = "allwinner,sun4i-a10-ir";
1165 clocks = <&apb0_gates 7>, <&ir1_clk>;
1166 clock-names = "apb", "ir";
1168 reg = <0x01c21c00 0x40>;
1169 status = "disabled";
1172 lradc: lradc@01c22800 {
1173 compatible = "allwinner,sun4i-a10-lradc-keys";
1174 reg = <0x01c22800 0x100>;
1176 status = "disabled";
1179 codec: codec@01c22c00 {
1180 #sound-dai-cells = <0>;
1181 compatible = "allwinner,sun4i-a10-codec";
1182 reg = <0x01c22c00 0x40>;
1184 clocks = <&apb0_gates 0>, <&codec_clk>;
1185 clock-names = "apb", "codec";
1186 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1187 <&dma SUN4I_DMA_NORMAL 19>;
1188 dma-names = "rx", "tx";
1189 status = "disabled";
1192 sid: eeprom@01c23800 {
1193 compatible = "allwinner,sun4i-a10-sid";
1194 reg = <0x01c23800 0x10>;
1198 compatible = "allwinner,sun4i-a10-ts";
1199 reg = <0x01c25000 0x100>;
1201 #thermal-sensor-cells = <0>;
1204 uart0: serial@01c28000 {
1205 compatible = "snps,dw-apb-uart";
1206 reg = <0x01c28000 0x400>;
1210 clocks = <&apb1_gates 16>;
1211 status = "disabled";
1214 uart1: serial@01c28400 {
1215 compatible = "snps,dw-apb-uart";
1216 reg = <0x01c28400 0x400>;
1220 clocks = <&apb1_gates 17>;
1221 status = "disabled";
1224 uart2: serial@01c28800 {
1225 compatible = "snps,dw-apb-uart";
1226 reg = <0x01c28800 0x400>;
1230 clocks = <&apb1_gates 18>;
1231 status = "disabled";
1234 uart3: serial@01c28c00 {
1235 compatible = "snps,dw-apb-uart";
1236 reg = <0x01c28c00 0x400>;
1240 clocks = <&apb1_gates 19>;
1241 status = "disabled";
1244 uart4: serial@01c29000 {
1245 compatible = "snps,dw-apb-uart";
1246 reg = <0x01c29000 0x400>;
1250 clocks = <&apb1_gates 20>;
1251 status = "disabled";
1254 uart5: serial@01c29400 {
1255 compatible = "snps,dw-apb-uart";
1256 reg = <0x01c29400 0x400>;
1260 clocks = <&apb1_gates 21>;
1261 status = "disabled";
1264 uart6: serial@01c29800 {
1265 compatible = "snps,dw-apb-uart";
1266 reg = <0x01c29800 0x400>;
1270 clocks = <&apb1_gates 22>;
1271 status = "disabled";
1274 uart7: serial@01c29c00 {
1275 compatible = "snps,dw-apb-uart";
1276 reg = <0x01c29c00 0x400>;
1280 clocks = <&apb1_gates 23>;
1281 status = "disabled";
1284 ps20: ps2@01c2a000 {
1285 compatible = "allwinner,sun4i-a10-ps2";
1286 reg = <0x01c2a000 0x400>;
1288 clocks = <&apb1_gates 6>;
1289 status = "disabled";
1292 ps21: ps2@01c2a400 {
1293 compatible = "allwinner,sun4i-a10-ps2";
1294 reg = <0x01c2a400 0x400>;
1296 clocks = <&apb1_gates 7>;
1297 status = "disabled";
1300 i2c0: i2c@01c2ac00 {
1301 compatible = "allwinner,sun4i-a10-i2c";
1302 reg = <0x01c2ac00 0x400>;
1304 clocks = <&apb1_gates 0>;
1305 status = "disabled";
1306 #address-cells = <1>;
1310 i2c1: i2c@01c2b000 {
1311 compatible = "allwinner,sun4i-a10-i2c";
1312 reg = <0x01c2b000 0x400>;
1314 clocks = <&apb1_gates 1>;
1315 status = "disabled";
1316 #address-cells = <1>;
1320 i2c2: i2c@01c2b400 {
1321 compatible = "allwinner,sun4i-a10-i2c";
1322 reg = <0x01c2b400 0x400>;
1324 clocks = <&apb1_gates 2>;
1325 status = "disabled";
1326 #address-cells = <1>;
1330 can0: can@01c2bc00 {
1331 compatible = "allwinner,sun4i-a10-can";
1332 reg = <0x01c2bc00 0x400>;
1334 clocks = <&apb1_gates 4>;
1335 status = "disabled";