1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
25 compatible = "arm,cortex-a7";
32 compatible = "arm,psci";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
42 reg = <0xa0021000 0x1000>,
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
88 compatible = "simple-bus";
91 interrupt-parent = <&intc>;
94 timers2: timer@40000000 {
97 compatible = "st,stm32-timers";
98 reg = <0x40000000 0x400>;
99 clocks = <&rcc TIM2_K>;
104 compatible = "st,stm32-pwm";
109 compatible = "st,stm32h7-timer-trigger";
115 timers3: timer@40001000 {
116 #address-cells = <1>;
118 compatible = "st,stm32-timers";
119 reg = <0x40001000 0x400>;
120 clocks = <&rcc TIM3_K>;
125 compatible = "st,stm32-pwm";
130 compatible = "st,stm32h7-timer-trigger";
136 timers4: timer@40002000 {
137 #address-cells = <1>;
139 compatible = "st,stm32-timers";
140 reg = <0x40002000 0x400>;
141 clocks = <&rcc TIM4_K>;
146 compatible = "st,stm32-pwm";
151 compatible = "st,stm32h7-timer-trigger";
157 timers5: timer@40003000 {
158 #address-cells = <1>;
160 compatible = "st,stm32-timers";
161 reg = <0x40003000 0x400>;
162 clocks = <&rcc TIM5_K>;
167 compatible = "st,stm32-pwm";
172 compatible = "st,stm32h7-timer-trigger";
178 timers6: timer@40004000 {
179 #address-cells = <1>;
181 compatible = "st,stm32-timers";
182 reg = <0x40004000 0x400>;
183 clocks = <&rcc TIM6_K>;
188 compatible = "st,stm32h7-timer-trigger";
194 timers7: timer@40005000 {
195 #address-cells = <1>;
197 compatible = "st,stm32-timers";
198 reg = <0x40005000 0x400>;
199 clocks = <&rcc TIM7_K>;
204 compatible = "st,stm32h7-timer-trigger";
210 timers12: timer@40006000 {
211 #address-cells = <1>;
213 compatible = "st,stm32-timers";
214 reg = <0x40006000 0x400>;
215 clocks = <&rcc TIM12_K>;
220 compatible = "st,stm32-pwm";
225 compatible = "st,stm32h7-timer-trigger";
231 timers13: timer@40007000 {
232 #address-cells = <1>;
234 compatible = "st,stm32-timers";
235 reg = <0x40007000 0x400>;
236 clocks = <&rcc TIM13_K>;
241 compatible = "st,stm32-pwm";
246 compatible = "st,stm32h7-timer-trigger";
252 timers14: timer@40008000 {
253 #address-cells = <1>;
255 compatible = "st,stm32-timers";
256 reg = <0x40008000 0x400>;
257 clocks = <&rcc TIM14_K>;
262 compatible = "st,stm32-pwm";
267 compatible = "st,stm32h7-timer-trigger";
273 lptimer1: timer@40009000 {
274 #address-cells = <1>;
276 compatible = "st,stm32-lptimer";
277 reg = <0x40009000 0x400>;
278 clocks = <&rcc LPTIM1_K>;
283 compatible = "st,stm32-pwm-lp";
289 compatible = "st,stm32-lptimer-trigger";
295 compatible = "st,stm32-lptimer-counter";
301 #address-cells = <1>;
303 compatible = "st,stm32h7-spi";
304 reg = <0x4000b000 0x400>;
305 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&rcc SPI2_K>;
307 resets = <&rcc SPI2_R>;
308 dmas = <&dmamux1 39 0x400 0x05>,
309 <&dmamux1 40 0x400 0x05>;
310 dma-names = "rx", "tx";
315 #address-cells = <1>;
317 compatible = "st,stm32h7-spi";
318 reg = <0x4000c000 0x400>;
319 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&rcc SPI3_K>;
321 resets = <&rcc SPI3_R>;
322 dmas = <&dmamux1 61 0x400 0x05>,
323 <&dmamux1 62 0x400 0x05>;
324 dma-names = "rx", "tx";
328 usart2: serial@4000e000 {
329 compatible = "st,stm32h7-uart";
330 reg = <0x4000e000 0x400>;
331 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&rcc USART2_K>;
336 usart3: serial@4000f000 {
337 compatible = "st,stm32h7-uart";
338 reg = <0x4000f000 0x400>;
339 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&rcc USART3_K>;
344 uart4: serial@40010000 {
345 compatible = "st,stm32h7-uart";
346 reg = <0x40010000 0x400>;
347 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&rcc UART4_K>;
352 uart5: serial@40011000 {
353 compatible = "st,stm32h7-uart";
354 reg = <0x40011000 0x400>;
355 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&rcc UART5_K>;
361 compatible = "st,stm32f7-i2c";
362 reg = <0x40012000 0x400>;
363 interrupt-names = "event", "error";
364 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&rcc I2C1_K>;
367 resets = <&rcc I2C1_R>;
368 #address-cells = <1>;
374 compatible = "st,stm32f7-i2c";
375 reg = <0x40013000 0x400>;
376 interrupt-names = "event", "error";
377 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&rcc I2C2_K>;
380 resets = <&rcc I2C2_R>;
381 #address-cells = <1>;
387 compatible = "st,stm32f7-i2c";
388 reg = <0x40014000 0x400>;
389 interrupt-names = "event", "error";
390 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&rcc I2C3_K>;
393 resets = <&rcc I2C3_R>;
394 #address-cells = <1>;
400 compatible = "st,stm32f7-i2c";
401 reg = <0x40015000 0x400>;
402 interrupt-names = "event", "error";
403 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&rcc I2C5_K>;
406 resets = <&rcc I2C5_R>;
407 #address-cells = <1>;
413 compatible = "st,stm32-cec";
414 reg = <0x40016000 0x400>;
415 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&rcc CEC_K>, <&clk_lse>;
417 clock-names = "cec", "hdmi-cec";
422 compatible = "st,stm32h7-dac-core";
423 reg = <0x40017000 0x400>;
424 clocks = <&rcc DAC12>;
425 clock-names = "pclk";
426 #address-cells = <1>;
431 compatible = "st,stm32-dac";
432 #io-channels-cells = <1>;
438 compatible = "st,stm32-dac";
439 #io-channels-cells = <1>;
445 uart7: serial@40018000 {
446 compatible = "st,stm32h7-uart";
447 reg = <0x40018000 0x400>;
448 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&rcc UART7_K>;
453 uart8: serial@40019000 {
454 compatible = "st,stm32h7-uart";
455 reg = <0x40019000 0x400>;
456 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&rcc UART8_K>;
461 timers1: timer@44000000 {
462 #address-cells = <1>;
464 compatible = "st,stm32-timers";
465 reg = <0x44000000 0x400>;
466 clocks = <&rcc TIM1_K>;
471 compatible = "st,stm32-pwm";
476 compatible = "st,stm32h7-timer-trigger";
482 timers8: timer@44001000 {
483 #address-cells = <1>;
485 compatible = "st,stm32-timers";
486 reg = <0x44001000 0x400>;
487 clocks = <&rcc TIM8_K>;
492 compatible = "st,stm32-pwm";
497 compatible = "st,stm32h7-timer-trigger";
503 usart6: serial@44003000 {
504 compatible = "st,stm32h7-uart";
505 reg = <0x44003000 0x400>;
506 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&rcc USART6_K>;
512 #address-cells = <1>;
514 compatible = "st,stm32h7-spi";
515 reg = <0x44004000 0x400>;
516 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&rcc SPI1_K>;
518 resets = <&rcc SPI1_R>;
519 dmas = <&dmamux1 37 0x400 0x05>,
520 <&dmamux1 38 0x400 0x05>;
521 dma-names = "rx", "tx";
526 #address-cells = <1>;
528 compatible = "st,stm32h7-spi";
529 reg = <0x44005000 0x400>;
530 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&rcc SPI4_K>;
532 resets = <&rcc SPI4_R>;
533 dmas = <&dmamux1 83 0x400 0x05>,
534 <&dmamux1 84 0x400 0x05>;
535 dma-names = "rx", "tx";
539 timers15: timer@44006000 {
540 #address-cells = <1>;
542 compatible = "st,stm32-timers";
543 reg = <0x44006000 0x400>;
544 clocks = <&rcc TIM15_K>;
549 compatible = "st,stm32-pwm";
554 compatible = "st,stm32h7-timer-trigger";
560 timers16: timer@44007000 {
561 #address-cells = <1>;
563 compatible = "st,stm32-timers";
564 reg = <0x44007000 0x400>;
565 clocks = <&rcc TIM16_K>;
570 compatible = "st,stm32-pwm";
574 compatible = "st,stm32h7-timer-trigger";
580 timers17: timer@44008000 {
581 #address-cells = <1>;
583 compatible = "st,stm32-timers";
584 reg = <0x44008000 0x400>;
585 clocks = <&rcc TIM17_K>;
590 compatible = "st,stm32-pwm";
595 compatible = "st,stm32h7-timer-trigger";
602 #address-cells = <1>;
604 compatible = "st,stm32h7-spi";
605 reg = <0x44009000 0x400>;
606 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&rcc SPI5_K>;
608 resets = <&rcc SPI5_R>;
609 dmas = <&dmamux1 85 0x400 0x05>,
610 <&dmamux1 86 0x400 0x05>;
611 dma-names = "rx", "tx";
615 dfsdm: dfsdm@4400d000 {
616 compatible = "st,stm32mp1-dfsdm";
617 reg = <0x4400d000 0x800>;
618 clocks = <&rcc DFSDM_K>;
619 clock-names = "dfsdm";
620 #address-cells = <1>;
625 compatible = "st,stm32-dfsdm-adc";
626 #io-channel-cells = <1>;
628 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
629 dmas = <&dmamux1 101 0x400 0x01>;
635 compatible = "st,stm32-dfsdm-adc";
636 #io-channel-cells = <1>;
638 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
639 dmas = <&dmamux1 102 0x400 0x01>;
645 compatible = "st,stm32-dfsdm-adc";
646 #io-channel-cells = <1>;
648 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
649 dmas = <&dmamux1 103 0x400 0x01>;
655 compatible = "st,stm32-dfsdm-adc";
656 #io-channel-cells = <1>;
658 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
659 dmas = <&dmamux1 104 0x400 0x01>;
665 compatible = "st,stm32-dfsdm-adc";
666 #io-channel-cells = <1>;
668 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
669 dmas = <&dmamux1 91 0x400 0x01>;
675 compatible = "st,stm32-dfsdm-adc";
676 #io-channel-cells = <1>;
678 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
679 dmas = <&dmamux1 92 0x400 0x01>;
685 m_can1: can@4400e000 {
686 compatible = "bosch,m_can";
687 reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
688 reg-names = "m_can", "message_ram";
689 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
691 interrupt-names = "int0", "int1";
692 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
693 clock-names = "hclk", "cclk";
694 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
698 m_can2: can@4400f000 {
699 compatible = "bosch,m_can";
700 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
701 reg-names = "m_can", "message_ram";
702 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
704 interrupt-names = "int0", "int1";
705 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
706 clock-names = "hclk", "cclk";
707 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
712 compatible = "st,stm32-dma";
713 reg = <0x48000000 0x400>;
714 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&rcc DMA1>;
729 compatible = "st,stm32-dma";
730 reg = <0x48001000 0x400>;
731 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&rcc DMA2>;
745 dmamux1: dma-router@48002000 {
746 compatible = "st,stm32h7-dmamux";
747 reg = <0x48002000 0x1c>;
749 dma-requests = <128>;
750 dma-masters = <&dma1 &dma2>;
752 clocks = <&rcc DMAMUX>;
756 compatible = "st,stm32mp1-adc-core";
757 reg = <0x48003000 0x400>;
758 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
761 clock-names = "bus", "adc";
762 interrupt-controller;
763 #interrupt-cells = <1>;
764 #address-cells = <1>;
769 compatible = "st,stm32mp1-adc";
770 #io-channel-cells = <1>;
772 interrupt-parent = <&adc>;
774 dmas = <&dmamux1 9 0x400 0x01>;
780 compatible = "st,stm32mp1-adc";
781 #io-channel-cells = <1>;
783 interrupt-parent = <&adc>;
785 dmas = <&dmamux1 10 0x400 0x01>;
791 usbotg_hs: usb-otg@49000000 {
792 compatible = "snps,dwc2";
793 reg = <0x49000000 0x10000>;
794 clocks = <&rcc USBO_K>;
796 resets = <&rcc USBO_R>;
797 reset-names = "dwc2";
798 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
799 g-rx-fifo-size = <256>;
800 g-np-tx-fifo-size = <32>;
801 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
807 compatible = "st,stm32mp1-rcc", "syscon";
808 reg = <0x50000000 0x1000>;
813 exti: interrupt-controller@5000d000 {
814 compatible = "st,stm32mp1-exti", "syscon";
815 interrupt-controller;
816 #interrupt-cells = <2>;
817 reg = <0x5000d000 0x400>;
820 syscfg: syscon@50020000 {
821 compatible = "st,stm32mp157-syscfg", "syscon";
822 reg = <0x50020000 0x400>;
825 lptimer2: timer@50021000 {
826 #address-cells = <1>;
828 compatible = "st,stm32-lptimer";
829 reg = <0x50021000 0x400>;
830 clocks = <&rcc LPTIM2_K>;
835 compatible = "st,stm32-pwm-lp";
841 compatible = "st,stm32-lptimer-trigger";
847 compatible = "st,stm32-lptimer-counter";
852 lptimer3: timer@50022000 {
853 #address-cells = <1>;
855 compatible = "st,stm32-lptimer";
856 reg = <0x50022000 0x400>;
857 clocks = <&rcc LPTIM3_K>;
862 compatible = "st,stm32-pwm-lp";
868 compatible = "st,stm32-lptimer-trigger";
874 lptimer4: timer@50023000 {
875 compatible = "st,stm32-lptimer";
876 reg = <0x50023000 0x400>;
877 clocks = <&rcc LPTIM4_K>;
882 compatible = "st,stm32-pwm-lp";
888 lptimer5: timer@50024000 {
889 compatible = "st,stm32-lptimer";
890 reg = <0x50024000 0x400>;
891 clocks = <&rcc LPTIM5_K>;
896 compatible = "st,stm32-pwm-lp";
902 vrefbuf: vrefbuf@50025000 {
903 compatible = "st,stm32-vrefbuf";
904 reg = <0x50025000 0x8>;
905 regulator-min-microvolt = <1500000>;
906 regulator-max-microvolt = <2500000>;
907 clocks = <&rcc VREF>;
911 cryp1: cryp@54001000 {
912 compatible = "st,stm32mp1-cryp";
913 reg = <0x54001000 0x400>;
914 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&rcc CRYP1>;
916 resets = <&rcc CRYP1_R>;
920 hash1: hash@54002000 {
921 compatible = "st,stm32f756-hash";
922 reg = <0x54002000 0x400>;
923 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&rcc HASH1>;
925 resets = <&rcc HASH1_R>;
926 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>;
933 compatible = "st,stm32-rng";
934 reg = <0x54003000 0x400>;
935 clocks = <&rcc RNG1_K>;
936 resets = <&rcc RNG1_R>;
940 mdma1: dma@58000000 {
941 compatible = "st,stm32h7-mdma";
942 reg = <0x58000000 0x1000>;
943 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&rcc MDMA>;
951 compatible = "st,stm32f469-qspi";
952 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
953 reg-names = "qspi", "qspi_mm";
954 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&rcc QSPI_K>;
956 resets = <&rcc QSPI_R>;
961 compatible = "st,stm32f7-crc";
962 reg = <0x58009000 0x400>;
963 clocks = <&rcc CRC1>;
967 stmmac_axi_config_0: stmmac-axi-config {
968 snps,wr_osr_lmt = <0x7>;
969 snps,rd_osr_lmt = <0x7>;
970 snps,blen = <0 0 0 0 16 8 4>;
973 ethernet0: ethernet@5800a000 {
974 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
975 reg = <0x5800a000 0x2000>;
976 reg-names = "stmmaceth";
977 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
978 interrupt-names = "macirq";
979 clock-names = "stmmaceth",
984 clocks = <&rcc ETHMAC>,
989 st,syscon = <&syscfg 0x4>;
992 snps,axi-config = <&stmmac_axi_config_0>;
997 usbh_ohci: usbh-ohci@5800c000 {
998 compatible = "generic-ohci";
999 reg = <0x5800c000 0x1000>;
1000 clocks = <&rcc USBH>;
1001 resets = <&rcc USBH_R>;
1002 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1003 status = "disabled";
1006 usbh_ehci: usbh-ehci@5800d000 {
1007 compatible = "generic-ehci";
1008 reg = <0x5800d000 0x1000>;
1009 clocks = <&rcc USBH>;
1010 resets = <&rcc USBH_R>;
1011 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1012 companion = <&usbh_ohci>;
1013 status = "disabled";
1017 compatible = "st,stm32-dsi";
1018 reg = <0x5a000000 0x800>;
1019 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1020 clock-names = "pclk", "ref", "px_clk";
1021 resets = <&rcc DSI_R>;
1022 reset-names = "apb";
1023 status = "disabled";
1026 ltdc: display-controller@5a001000 {
1027 compatible = "st,stm32-ltdc";
1028 reg = <0x5a001000 0x400>;
1029 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&rcc LTDC_PX>;
1032 clock-names = "lcd";
1033 resets = <&rcc LTDC_R>;
1034 status = "disabled";
1037 iwdg2: watchdog@5a002000 {
1038 compatible = "st,stm32mp1-iwdg";
1039 reg = <0x5a002000 0x400>;
1040 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1041 clock-names = "pclk", "lsi";
1042 status = "disabled";
1045 usbphyc: usbphyc@5a006000 {
1046 #address-cells = <1>;
1048 compatible = "st,stm32mp1-usbphyc";
1049 reg = <0x5a006000 0x1000>;
1050 clocks = <&rcc USBPHY_K>;
1051 resets = <&rcc USBPHY_R>;
1052 status = "disabled";
1054 usbphyc_port0: usb-phy@0 {
1059 usbphyc_port1: usb-phy@1 {
1065 usart1: serial@5c000000 {
1066 compatible = "st,stm32h7-uart";
1067 reg = <0x5c000000 0x400>;
1068 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&rcc USART1_K>;
1070 status = "disabled";
1073 spi6: spi@5c001000 {
1074 #address-cells = <1>;
1076 compatible = "st,stm32h7-spi";
1077 reg = <0x5c001000 0x400>;
1078 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&rcc SPI6_K>;
1080 resets = <&rcc SPI6_R>;
1081 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1082 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1083 dma-names = "rx", "tx";
1084 status = "disabled";
1087 i2c4: i2c@5c002000 {
1088 compatible = "st,stm32f7-i2c";
1089 reg = <0x5c002000 0x400>;
1090 interrupt-names = "event", "error";
1091 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&rcc I2C4_K>;
1094 resets = <&rcc I2C4_R>;
1095 #address-cells = <1>;
1097 status = "disabled";
1101 compatible = "st,stm32mp1-rtc";
1102 reg = <0x5c004000 0x400>;
1103 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1104 clock-names = "pclk", "rtc_ck";
1105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1106 status = "disabled";
1109 i2c6: i2c@5c009000 {
1110 compatible = "st,stm32f7-i2c";
1111 reg = <0x5c009000 0x400>;
1112 interrupt-names = "event", "error";
1113 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&rcc I2C6_K>;
1116 resets = <&rcc I2C6_R>;
1117 #address-cells = <1>;
1119 status = "disabled";