arch/arm/boot/dts/stm32mp157-pinctrl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
   7
   8 / {
   9         soc {
  10                 pinctrl: pin-controller@50002000 {
  11                         #address-cells = <1>;
  12                         #size-cells = <1>;
  13                         compatible = "st,stm32mp157-pinctrl";
  14                         ranges = <0 0x50002000 0xa400>;
  15                         pins-are-numbered;
  16
  17                         gpioa: gpio@50002000 {
  18                                 gpio-controller;
  19                                 #gpio-cells = <2>;
  20                                 interrupt-controller;
  21                                 #interrupt-cells = <2>;
  22                                 reg = <0x0 0x400>;
  23                                 clocks = <&rcc GPIOA>;
  24                                 st,bank-name = "GPIOA";
  25                                 ngpios = <16>;
  26                                 gpio-ranges = <&pinctrl 0 0 16>;
  27                         };
  28
  29                         gpiob: gpio@50003000 {
  30                                 gpio-controller;
  31                                 #gpio-cells = <2>;
  32                                 interrupt-controller;
  33                                 #interrupt-cells = <2>;
  34                                 reg = <0x1000 0x400>;
  35                                 clocks = <&rcc GPIOB>;
  36                                 st,bank-name = "GPIOB";
  37                                 ngpios = <16>;
  38                                 gpio-ranges = <&pinctrl 0 16 16>;
  39                         };
  40
  41                         gpioc: gpio@50004000 {
  42                                 gpio-controller;
  43                                 #gpio-cells = <2>;
  44                                 interrupt-controller;
  45                                 #interrupt-cells = <2>;
  46                                 reg = <0x2000 0x400>;
  47                                 clocks = <&rcc GPIOC>;
  48                                 st,bank-name = "GPIOC";
  49                                 ngpios = <16>;
  50                                 gpio-ranges = <&pinctrl 0 32 16>;
  51                         };
  52
  53                         gpiod: gpio@50005000 {
  54                                 gpio-controller;
  55                                 #gpio-cells = <2>;
  56                                 interrupt-controller;
  57                                 #interrupt-cells = <2>;
  58                                 reg = <0x3000 0x400>;
  59                                 clocks = <&rcc GPIOD>;
  60                                 st,bank-name = "GPIOD";
  61                                 ngpios = <16>;
  62                                 gpio-ranges = <&pinctrl 0 48 16>;
  63                         };
  64
  65                         gpioe: gpio@50006000 {
  66                                 gpio-controller;
  67                                 #gpio-cells = <2>;
  68                                 interrupt-controller;
  69                                 #interrupt-cells = <2>;
  70                                 reg = <0x4000 0x400>;
  71                                 clocks = <&rcc GPIOE>;
  72                                 st,bank-name = "GPIOE";
  73                                 ngpios = <16>;
  74                                 gpio-ranges = <&pinctrl 0 64 16>;
  75                         };
  76
  77                         gpiof: gpio@50007000 {
  78                                 gpio-controller;
  79                                 #gpio-cells = <2>;
  80                                 interrupt-controller;
  81                                 #interrupt-cells = <2>;
  82                                 reg = <0x5000 0x400>;
  83                                 clocks = <&rcc GPIOF>;
  84                                 st,bank-name = "GPIOF";
  85                                 ngpios = <16>;
  86                                 gpio-ranges = <&pinctrl 0 80 16>;
  87                         };
  88
  89                         gpiog: gpio@50008000 {
  90                                 gpio-controller;
  91                                 #gpio-cells = <2>;
  92                                 interrupt-controller;
  93                                 #interrupt-cells = <2>;
  94                                 reg = <0x6000 0x400>;
  95                                 clocks = <&rcc GPIOG>;
  96                                 st,bank-name = "GPIOG";
  97                                 ngpios = <16>;
  98                                 gpio-ranges = <&pinctrl 0 96 16>;
  99                         };
 100
 101                         gpioh: gpio@50009000 {
 102                                 gpio-controller;
 103                                 #gpio-cells = <2>;
 104                                 interrupt-controller;
 105                                 #interrupt-cells = <2>;
 106                                 reg = <0x7000 0x400>;
 107                                 clocks = <&rcc GPIOH>;
 108                                 st,bank-name = "GPIOH";
 109                                 ngpios = <16>;
 110                                 gpio-ranges = <&pinctrl 0 112 16>;
 111                         };
 112
 113                         gpioi: gpio@5000a000 {
 114                                 gpio-controller;
 115                                 #gpio-cells = <2>;
 116                                 interrupt-controller;
 117                                 #interrupt-cells = <2>;
 118                                 reg = <0x8000 0x400>;
 119                                 clocks = <&rcc GPIOI>;
 120                                 st,bank-name = "GPIOI";
 121                                 ngpios = <16>;
 122                                 gpio-ranges = <&pinctrl 0 128 16>;
 123                         };
 124
 125                         gpioj: gpio@5000b000 {
 126                                 gpio-controller;
 127                                 #gpio-cells = <2>;
 128                                 interrupt-controller;
 129                                 #interrupt-cells = <2>;
 130                                 reg = <0x9000 0x400>;
 131                                 clocks = <&rcc GPIOJ>;
 132                                 st,bank-name = "GPIOJ";
 133                                 ngpios = <16>;
 134                                 gpio-ranges = <&pinctrl 0 144 16>;
 135                         };
 136
 137                         gpiok: gpio@5000c000 {
 138                                 gpio-controller;
 139                                 #gpio-cells = <2>;
 140                                 interrupt-controller;
 141                                 #interrupt-cells = <2>;
 142                                 reg = <0xa000 0x400>;
 143                                 clocks = <&rcc GPIOK>;
 144                                 st,bank-name = "GPIOK";
 145                                 ngpios = <8>;
 146                                 gpio-ranges = <&pinctrl 0 160 8>;
 147                         };
 148
 149                         cec_pins_a: cec-0 {
 150                                 pins {
 151                                         pinmux = <STM32_PINMUX('A', 15, AF4)>;
 152                                         bias-disable;
 153                                         drive-open-drain;
 154                                         slew-rate = <0>;
 155                                 };
 156                         };
 157
 158                         i2c1_pins_a: i2c1-0 {
 159                                 pins {
 160                                         pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
 161                                                  <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
 162                                         bias-disable;
 163                                         drive-open-drain;
 164                                         slew-rate = <0>;
 165                                 };
 166                         };
 167
 168                         i2c2_pins_a: i2c2-0 {
 169                                 pins {
 170                                         pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
 171                                                  <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
 172                                         bias-disable;
 173                                         drive-open-drain;
 174                                         slew-rate = <0>;
 175                                 };
 176                         };
 177
 178                         i2c5_pins_a: i2c5-0 {
 179                                 pins {
 180                                         pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
 181                                                  <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
 182                                         bias-disable;
 183                                         drive-open-drain;
 184                                         slew-rate = <0>;
 185                                 };
 186                         };
 187
 188                         pwm2_pins_a: pwm2-0 {
 189                                 pins {
 190                                         pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
 191                                         bias-pull-down;
 192                                         drive-push-pull;
 193                                         slew-rate = <0>;
 194                                 };
 195                         };
 196
 197                         pwm8_pins_a: pwm8-0 {
 198                                 pins {
 199                                         pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
 200                                         bias-pull-down;
 201                                         drive-push-pull;
 202                                         slew-rate = <0>;
 203                                 };
 204                         };
 205
 206                         pwm12_pins_a: pwm12-0 {
 207                                 pins {
 208                                         pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
 209                                         bias-pull-down;
 210                                         drive-push-pull;
 211                                         slew-rate = <0>;
 212                                 };
 213                         };
 214
 215                         qspi_clk_pins_a: qspi-clk-0 {
 216                                 pins {
 217                                         pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
 218                                         bias-disable;
 219                                         drive-push-pull;
 220                                         slew-rate = <3>;
 221                                 };
 222                         };
 223
 224                         qspi_bk1_pins_a: qspi-bk1-0 {
 225                                 pins1 {
 226                                         pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
 227                                                  <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
 228                                                  <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
 229                                                  <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
 230                                         bias-disable;
 231                                         drive-push-pull;
 232                                         slew-rate = <3>;
 233                                 };
 234                                 pins2 {
 235                                         pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
 236                                         bias-pull-up;
 237                                         drive-push-pull;
 238                                         slew-rate = <3>;
 239                                 };
 240                         };
 241
 242                         qspi_bk2_pins_a: qspi-bk2-0 {
 243                                 pins1 {
 244                                         pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
 245                                                  <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
 246                                                  <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
 247                                                  <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
 248                                         bias-disable;
 249                                         drive-push-pull;
 250                                         slew-rate = <3>;
 251                                 };
 252                                 pins2 {
 253                                         pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
 254                                         bias-pull-up;
 255                                         drive-push-pull;
 256                                         slew-rate = <3>;
 257                                 };
 258                         };
 259
 260                         uart4_pins_a: uart4-0 {
 261                                 pins1 {
 262                                         pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
 263                                         bias-disable;
 264                                         drive-push-pull;
 265                                         slew-rate = <0>;
 266                                 };
 267                                 pins2 {
 268                                         pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
 269                                         bias-disable;
 270                                 };
 271                         };
 272                 };
 273
 274                 pinctrl_z: pin-controller-z@54004000 {
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277                         compatible = "st,stm32mp157-z-pinctrl";
 278                         ranges = <0 0x54004000 0x400>;
 279                         pins-are-numbered;
 280                         status = "disabled";
 281
 282                         gpioz: gpio@54004000 {
 283                                 gpio-controller;
 284                                 #gpio-cells = <2>;
 285                                 interrupt-controller;
 286                                 #interrupt-cells = <2>;
 287                                 reg = <0 0x400>;
 288                                 clocks = <&rcc GPIOZ>;
 289                                 st,bank-name = "GPIOZ";
 290                                 st,bank-ioport = <11>;
 291                                 ngpios = <8>;
 292                                 gpio-ranges = <&pinctrl_z 0 400 8>;
 293                         };
 294
 295                         i2c4_pins_a: i2c4-0 {
 296                                 pins {
 297                                         pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
 298                                                  <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
 299                                         bias-disable;
 300                                         drive-open-drain;
 301                                         slew-rate = <0>;
 302                                 };
 303                         };
 304                 };
 305         };
 306 };