arch/arm/boot/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                 };
  24         };
  25
  26         psci {
  27                 compatible = "arm,psci";
  28                 method = "smc";
  29                 cpu_off = <0x84000002>;
  30                 cpu_on = <0x84000003>;
  31         };
  32
  33         intc: interrupt-controller@a0021000 {
  34                 compatible = "arm,cortex-a7-gic";
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0xa0021000 0x1000>,
  38                       <0xa0022000 0x2000>;
  39         };
  40
  41         timer {
  42                 compatible = "arm,armv7-timer";
  43                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  44                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  45                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  46                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  47                 interrupt-parent = <&intc>;
  48         };
  49
  50         clocks {
  51                 clk_hse: clk-hse {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <24000000>;
  55                 };
  56
  57                 clk_hsi: clk-hsi {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <64000000>;
  61                 };
  62
  63                 clk_lse: clk-lse {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 clk_lsi: clk-lsi {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32000>;
  73                 };
  74
  75                 clk_csi: clk-csi {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <4000000>;
  79                 };
  80         };
  81
  82         thermal-zones {
  83                 cpu_thermal: cpu-thermal {
  84                         polling-delay-passive = <0>;
  85                         polling-delay = <0>;
  86                         thermal-sensors = <&dts>;
  87
  88                         trips {
  89                                 cpu_alert1: cpu-alert1 {
  90                                         temperature = <85000>;
  91                                         hysteresis = <0>;
  92                                         type = "passive";
  93                                 };
  94
  95                                 cpu-crit {
  96                                         temperature = <120000>;
  97                                         hysteresis = <0>;
  98                                         type = "critical";
  99                                 };
 100                         };
 101
 102                         cooling-maps {
 103                         };
 104                 };
 105         };
 106
 107         booster: regulator-booster {
 108                 compatible = "st,stm32mp1-booster";
 109                 st,syscfg = <&syscfg>;
 110                 status = "disabled";
 111         };
 112
 113         soc {
 114                 compatible = "simple-bus";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 interrupt-parent = <&intc>;
 118                 ranges;
 119
 120                 timers2: timer@40000000 {
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                         compatible = "st,stm32-timers";
 124                         reg = <0x40000000 0x400>;
 125                         clocks = <&rcc TIM2_K>;
 126                         clock-names = "int";
 127                         dmas = <&dmamux1 18 0x400 0x1>,
 128                                <&dmamux1 19 0x400 0x1>,
 129                                <&dmamux1 20 0x400 0x1>,
 130                                <&dmamux1 21 0x400 0x1>,
 131                                <&dmamux1 22 0x400 0x1>;
 132                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 133                         status = "disabled";
 134
 135                         pwm {
 136                                 compatible = "st,stm32-pwm";
 137                                 #pwm-cells = <3>;
 138                                 status = "disabled";
 139                         };
 140
 141                         timer@1 {
 142                                 compatible = "st,stm32h7-timer-trigger";
 143                                 reg = <1>;
 144                                 status = "disabled";
 145                         };
 146
 147                         counter {
 148                                 compatible = "st,stm32-timer-counter";
 149                                 status = "disabled";
 150                         };
 151                 };
 152
 153                 timers3: timer@40001000 {
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         compatible = "st,stm32-timers";
 157                         reg = <0x40001000 0x400>;
 158                         clocks = <&rcc TIM3_K>;
 159                         clock-names = "int";
 160                         dmas = <&dmamux1 23 0x400 0x1>,
 161                                <&dmamux1 24 0x400 0x1>,
 162                                <&dmamux1 25 0x400 0x1>,
 163                                <&dmamux1 26 0x400 0x1>,
 164                                <&dmamux1 27 0x400 0x1>,
 165                                <&dmamux1 28 0x400 0x1>;
 166                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 167                         status = "disabled";
 168
 169                         pwm {
 170                                 compatible = "st,stm32-pwm";
 171                                 #pwm-cells = <3>;
 172                                 status = "disabled";
 173                         };
 174
 175                         timer@2 {
 176                                 compatible = "st,stm32h7-timer-trigger";
 177                                 reg = <2>;
 178                                 status = "disabled";
 179                         };
 180
 181                         counter {
 182                                 compatible = "st,stm32-timer-counter";
 183                                 status = "disabled";
 184                         };
 185                 };
 186
 187                 timers4: timer@40002000 {
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         compatible = "st,stm32-timers";
 191                         reg = <0x40002000 0x400>;
 192                         clocks = <&rcc TIM4_K>;
 193                         clock-names = "int";
 194                         dmas = <&dmamux1 29 0x400 0x1>,
 195                                <&dmamux1 30 0x400 0x1>,
 196                                <&dmamux1 31 0x400 0x1>,
 197                                <&dmamux1 32 0x400 0x1>;
 198                         dma-names = "ch1", "ch2", "ch3", "ch4";
 199                         status = "disabled";
 200
 201                         pwm {
 202                                 compatible = "st,stm32-pwm";
 203                                 #pwm-cells = <3>;
 204                                 status = "disabled";
 205                         };
 206
 207                         timer@3 {
 208                                 compatible = "st,stm32h7-timer-trigger";
 209                                 reg = <3>;
 210                                 status = "disabled";
 211                         };
 212
 213                         counter {
 214                                 compatible = "st,stm32-timer-counter";
 215                                 status = "disabled";
 216                         };
 217                 };
 218
 219                 timers5: timer@40003000 {
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         compatible = "st,stm32-timers";
 223                         reg = <0x40003000 0x400>;
 224                         clocks = <&rcc TIM5_K>;
 225                         clock-names = "int";
 226                         dmas = <&dmamux1 55 0x400 0x1>,
 227                                <&dmamux1 56 0x400 0x1>,
 228                                <&dmamux1 57 0x400 0x1>,
 229                                <&dmamux1 58 0x400 0x1>,
 230                                <&dmamux1 59 0x400 0x1>,
 231                                <&dmamux1 60 0x400 0x1>;
 232                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 233                         status = "disabled";
 234
 235                         pwm {
 236                                 compatible = "st,stm32-pwm";
 237                                 #pwm-cells = <3>;
 238                                 status = "disabled";
 239                         };
 240
 241                         timer@4 {
 242                                 compatible = "st,stm32h7-timer-trigger";
 243                                 reg = <4>;
 244                                 status = "disabled";
 245                         };
 246
 247                         counter {
 248                                 compatible = "st,stm32-timer-counter";
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 timers6: timer@40004000 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         compatible = "st,stm32-timers";
 257                         reg = <0x40004000 0x400>;
 258                         clocks = <&rcc TIM6_K>;
 259                         clock-names = "int";
 260                         dmas = <&dmamux1 69 0x400 0x1>;
 261                         dma-names = "up";
 262                         status = "disabled";
 263
 264                         timer@5 {
 265                                 compatible = "st,stm32h7-timer-trigger";
 266                                 reg = <5>;
 267                                 status = "disabled";
 268                         };
 269                 };
 270
 271                 timers7: timer@40005000 {
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                         compatible = "st,stm32-timers";
 275                         reg = <0x40005000 0x400>;
 276                         clocks = <&rcc TIM7_K>;
 277                         clock-names = "int";
 278                         dmas = <&dmamux1 70 0x400 0x1>;
 279                         dma-names = "up";
 280                         status = "disabled";
 281
 282                         timer@6 {
 283                                 compatible = "st,stm32h7-timer-trigger";
 284                                 reg = <6>;
 285                                 status = "disabled";
 286                         };
 287                 };
 288
 289                 timers12: timer@40006000 {
 290                         #address-cells = <1>;
 291                         #size-cells = <0>;
 292                         compatible = "st,stm32-timers";
 293                         reg = <0x40006000 0x400>;
 294                         clocks = <&rcc TIM12_K>;
 295                         clock-names = "int";
 296                         status = "disabled";
 297
 298                         pwm {
 299                                 compatible = "st,stm32-pwm";
 300                                 #pwm-cells = <3>;
 301                                 status = "disabled";
 302                         };
 303
 304                         timer@11 {
 305                                 compatible = "st,stm32h7-timer-trigger";
 306                                 reg = <11>;
 307                                 status = "disabled";
 308                         };
 309                 };
 310
 311                 timers13: timer@40007000 {
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         compatible = "st,stm32-timers";
 315                         reg = <0x40007000 0x400>;
 316                         clocks = <&rcc TIM13_K>;
 317                         clock-names = "int";
 318                         status = "disabled";
 319
 320                         pwm {
 321                                 compatible = "st,stm32-pwm";
 322                                 #pwm-cells = <3>;
 323                                 status = "disabled";
 324                         };
 325
 326                         timer@12 {
 327                                 compatible = "st,stm32h7-timer-trigger";
 328                                 reg = <12>;
 329                                 status = "disabled";
 330                         };
 331                 };
 332
 333                 timers14: timer@40008000 {
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         compatible = "st,stm32-timers";
 337                         reg = <0x40008000 0x400>;
 338                         clocks = <&rcc TIM14_K>;
 339                         clock-names = "int";
 340                         status = "disabled";
 341
 342                         pwm {
 343                                 compatible = "st,stm32-pwm";
 344                                 #pwm-cells = <3>;
 345                                 status = "disabled";
 346                         };
 347
 348                         timer@13 {
 349                                 compatible = "st,stm32h7-timer-trigger";
 350                                 reg = <13>;
 351                                 status = "disabled";
 352                         };
 353                 };
 354
 355                 lptimer1: timer@40009000 {
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         compatible = "st,stm32-lptimer";
 359                         reg = <0x40009000 0x400>;
 360                         clocks = <&rcc LPTIM1_K>;
 361                         clock-names = "mux";
 362                         status = "disabled";
 363
 364                         pwm {
 365                                 compatible = "st,stm32-pwm-lp";
 366                                 #pwm-cells = <3>;
 367                                 status = "disabled";
 368                         };
 369
 370                         trigger@0 {
 371                                 compatible = "st,stm32-lptimer-trigger";
 372                                 reg = <0>;
 373                                 status = "disabled";
 374                         };
 375
 376                         counter {
 377                                 compatible = "st,stm32-lptimer-counter";
 378                                 status = "disabled";
 379                         };
 380                 };
 381
 382                 spi2: spi@4000b000 {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         compatible = "st,stm32h7-spi";
 386                         reg = <0x4000b000 0x400>;
 387                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&rcc SPI2_K>;
 389                         resets = <&rcc SPI2_R>;
 390                         dmas = <&dmamux1 39 0x400 0x05>,
 391                                <&dmamux1 40 0x400 0x05>;
 392                         dma-names = "rx", "tx";
 393                         status = "disabled";
 394                 };
 395
 396                 i2s2: audio-controller@4000b000 {
 397                         compatible = "st,stm32h7-i2s";
 398                         #sound-dai-cells = <0>;
 399                         reg = <0x4000b000 0x400>;
 400                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 401                         dmas = <&dmamux1 39 0x400 0x01>,
 402                                <&dmamux1 40 0x400 0x01>;
 403                         dma-names = "rx", "tx";
 404                         status = "disabled";
 405                 };
 406
 407                 spi3: spi@4000c000 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "st,stm32h7-spi";
 411                         reg = <0x4000c000 0x400>;
 412                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&rcc SPI3_K>;
 414                         resets = <&rcc SPI3_R>;
 415                         dmas = <&dmamux1 61 0x400 0x05>,
 416                                <&dmamux1 62 0x400 0x05>;
 417                         dma-names = "rx", "tx";
 418                         status = "disabled";
 419                 };
 420
 421                 i2s3: audio-controller@4000c000 {
 422                         compatible = "st,stm32h7-i2s";
 423                         #sound-dai-cells = <0>;
 424                         reg = <0x4000c000 0x400>;
 425                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 426                         dmas = <&dmamux1 61 0x400 0x01>,
 427                                <&dmamux1 62 0x400 0x01>;
 428                         dma-names = "rx", "tx";
 429                         status = "disabled";
 430                 };
 431
 432                 spdifrx: audio-controller@4000d000 {
 433                         compatible = "st,stm32h7-spdifrx";
 434                         #sound-dai-cells = <0>;
 435                         reg = <0x4000d000 0x400>;
 436                         clocks = <&rcc SPDIF_K>;
 437                         clock-names = "kclk";
 438                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 439                         dmas = <&dmamux1 93 0x400 0x01>,
 440                                <&dmamux1 94 0x400 0x01>;
 441                         dma-names = "rx", "rx-ctrl";
 442                         status = "disabled";
 443                 };
 444
 445                 usart2: serial@4000e000 {
 446                         compatible = "st,stm32h7-uart";
 447                         reg = <0x4000e000 0x400>;
 448                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&rcc USART2_K>;
 450                         status = "disabled";
 451                 };
 452
 453                 usart3: serial@4000f000 {
 454                         compatible = "st,stm32h7-uart";
 455                         reg = <0x4000f000 0x400>;
 456                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&rcc USART3_K>;
 458                         status = "disabled";
 459                 };
 460
 461                 uart4: serial@40010000 {
 462                         compatible = "st,stm32h7-uart";
 463                         reg = <0x40010000 0x400>;
 464                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 465                         clocks = <&rcc UART4_K>;
 466                         status = "disabled";
 467                 };
 468
 469                 uart5: serial@40011000 {
 470                         compatible = "st,stm32h7-uart";
 471                         reg = <0x40011000 0x400>;
 472                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&rcc UART5_K>;
 474                         status = "disabled";
 475                 };
 476
 477                 i2c1: i2c@40012000 {
 478                         compatible = "st,stm32f7-i2c";
 479                         reg = <0x40012000 0x400>;
 480                         interrupt-names = "event", "error";
 481                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 482                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 483                         clocks = <&rcc I2C1_K>;
 484                         resets = <&rcc I2C1_R>;
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                         wakeup-source;
 488                         status = "disabled";
 489                 };
 490
 491                 i2c2: i2c@40013000 {
 492                         compatible = "st,stm32f7-i2c";
 493                         reg = <0x40013000 0x400>;
 494                         interrupt-names = "event", "error";
 495                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&rcc I2C2_K>;
 498                         resets = <&rcc I2C2_R>;
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                         wakeup-source;
 502                         status = "disabled";
 503                 };
 504
 505                 i2c3: i2c@40014000 {
 506                         compatible = "st,stm32f7-i2c";
 507                         reg = <0x40014000 0x400>;
 508                         interrupt-names = "event", "error";
 509                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 510                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&rcc I2C3_K>;
 512                         resets = <&rcc I2C3_R>;
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         wakeup-source;
 516                         status = "disabled";
 517                 };
 518
 519                 i2c5: i2c@40015000 {
 520                         compatible = "st,stm32f7-i2c";
 521                         reg = <0x40015000 0x400>;
 522                         interrupt-names = "event", "error";
 523                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 524                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&rcc I2C5_K>;
 526                         resets = <&rcc I2C5_R>;
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         wakeup-source;
 530                         status = "disabled";
 531                 };
 532
 533                 cec: cec@40016000 {
 534                         compatible = "st,stm32-cec";
 535                         reg = <0x40016000 0x400>;
 536                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&rcc CEC_K>, <&clk_lse>;
 538                         clock-names = "cec", "hdmi-cec";
 539                         status = "disabled";
 540                 };
 541
 542                 dac: dac@40017000 {
 543                         compatible = "st,stm32h7-dac-core";
 544                         reg = <0x40017000 0x400>;
 545                         clocks = <&rcc DAC12>;
 546                         clock-names = "pclk";
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         status = "disabled";
 550
 551                         dac1: dac@1 {
 552                                 compatible = "st,stm32-dac";
 553                                 #io-channels-cells = <1>;
 554                                 reg = <1>;
 555                                 status = "disabled";
 556                         };
 557
 558                         dac2: dac@2 {
 559                                 compatible = "st,stm32-dac";
 560                                 #io-channels-cells = <1>;
 561                                 reg = <2>;
 562                                 status = "disabled";
 563                         };
 564                 };
 565
 566                 uart7: serial@40018000 {
 567                         compatible = "st,stm32h7-uart";
 568                         reg = <0x40018000 0x400>;
 569                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&rcc UART7_K>;
 571                         status = "disabled";
 572                 };
 573
 574                 uart8: serial@40019000 {
 575                         compatible = "st,stm32h7-uart";
 576                         reg = <0x40019000 0x400>;
 577                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&rcc UART8_K>;
 579                         status = "disabled";
 580                 };
 581
 582                 timers1: timer@44000000 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         compatible = "st,stm32-timers";
 586                         reg = <0x44000000 0x400>;
 587                         clocks = <&rcc TIM1_K>;
 588                         clock-names = "int";
 589                         dmas = <&dmamux1 11 0x400 0x1>,
 590                                <&dmamux1 12 0x400 0x1>,
 591                                <&dmamux1 13 0x400 0x1>,
 592                                <&dmamux1 14 0x400 0x1>,
 593                                <&dmamux1 15 0x400 0x1>,
 594                                <&dmamux1 16 0x400 0x1>,
 595                                <&dmamux1 17 0x400 0x1>;
 596                         dma-names = "ch1", "ch2", "ch3", "ch4",
 597                                     "up", "trig", "com";
 598                         status = "disabled";
 599
 600                         pwm {
 601                                 compatible = "st,stm32-pwm";
 602                                 #pwm-cells = <3>;
 603                                 status = "disabled";
 604                         };
 605
 606                         timer@0 {
 607                                 compatible = "st,stm32h7-timer-trigger";
 608                                 reg = <0>;
 609                                 status = "disabled";
 610                         };
 611
 612                         counter {
 613                                 compatible = "st,stm32-timer-counter";
 614                                 status = "disabled";
 615                         };
 616                 };
 617
 618                 timers8: timer@44001000 {
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         compatible = "st,stm32-timers";
 622                         reg = <0x44001000 0x400>;
 623                         clocks = <&rcc TIM8_K>;
 624                         clock-names = "int";
 625                         dmas = <&dmamux1 47 0x400 0x1>,
 626                                <&dmamux1 48 0x400 0x1>,
 627                                <&dmamux1 49 0x400 0x1>,
 628                                <&dmamux1 50 0x400 0x1>,
 629                                <&dmamux1 51 0x400 0x1>,
 630                                <&dmamux1 52 0x400 0x1>,
 631                                <&dmamux1 53 0x400 0x1>;
 632                         dma-names = "ch1", "ch2", "ch3", "ch4",
 633                                     "up", "trig", "com";
 634                         status = "disabled";
 635
 636                         pwm {
 637                                 compatible = "st,stm32-pwm";
 638                                 #pwm-cells = <3>;
 639                                 status = "disabled";
 640                         };
 641
 642                         timer@7 {
 643                                 compatible = "st,stm32h7-timer-trigger";
 644                                 reg = <7>;
 645                                 status = "disabled";
 646                         };
 647
 648                         counter {
 649                                 compatible = "st,stm32-timer-counter";
 650                                 status = "disabled";
 651                         };
 652                 };
 653
 654                 usart6: serial@44003000 {
 655                         compatible = "st,stm32h7-uart";
 656                         reg = <0x44003000 0x400>;
 657                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 658                         clocks = <&rcc USART6_K>;
 659                         status = "disabled";
 660                 };
 661
 662                 spi1: spi@44004000 {
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665                         compatible = "st,stm32h7-spi";
 666                         reg = <0x44004000 0x400>;
 667                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 668                         clocks = <&rcc SPI1_K>;
 669                         resets = <&rcc SPI1_R>;
 670                         dmas = <&dmamux1 37 0x400 0x05>,
 671                                <&dmamux1 38 0x400 0x05>;
 672                         dma-names = "rx", "tx";
 673                         status = "disabled";
 674                 };
 675
 676                 i2s1: audio-controller@44004000 {
 677                         compatible = "st,stm32h7-i2s";
 678                         #sound-dai-cells = <0>;
 679                         reg = <0x44004000 0x400>;
 680                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 681                         dmas = <&dmamux1 37 0x400 0x01>,
 682                                <&dmamux1 38 0x400 0x01>;
 683                         dma-names = "rx", "tx";
 684                         status = "disabled";
 685                 };
 686
 687                 spi4: spi@44005000 {
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                         compatible = "st,stm32h7-spi";
 691                         reg = <0x44005000 0x400>;
 692                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 693                         clocks = <&rcc SPI4_K>;
 694                         resets = <&rcc SPI4_R>;
 695                         dmas = <&dmamux1 83 0x400 0x05>,
 696                                <&dmamux1 84 0x400 0x05>;
 697                         dma-names = "rx", "tx";
 698                         status = "disabled";
 699                 };
 700
 701                 timers15: timer@44006000 {
 702                         #address-cells = <1>;
 703                         #size-cells = <0>;
 704                         compatible = "st,stm32-timers";
 705                         reg = <0x44006000 0x400>;
 706                         clocks = <&rcc TIM15_K>;
 707                         clock-names = "int";
 708                         dmas = <&dmamux1 105 0x400 0x1>,
 709                                <&dmamux1 106 0x400 0x1>,
 710                                <&dmamux1 107 0x400 0x1>,
 711                                <&dmamux1 108 0x400 0x1>;
 712                         dma-names = "ch1", "up", "trig", "com";
 713                         status = "disabled";
 714
 715                         pwm {
 716                                 compatible = "st,stm32-pwm";
 717                                 #pwm-cells = <3>;
 718                                 status = "disabled";
 719                         };
 720
 721                         timer@14 {
 722                                 compatible = "st,stm32h7-timer-trigger";
 723                                 reg = <14>;
 724                                 status = "disabled";
 725                         };
 726                 };
 727
 728                 timers16: timer@44007000 {
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                         compatible = "st,stm32-timers";
 732                         reg = <0x44007000 0x400>;
 733                         clocks = <&rcc TIM16_K>;
 734                         clock-names = "int";
 735                         dmas = <&dmamux1 109 0x400 0x1>,
 736                                <&dmamux1 110 0x400 0x1>;
 737                         dma-names = "ch1", "up";
 738                         status = "disabled";
 739
 740                         pwm {
 741                                 compatible = "st,stm32-pwm";
 742                                 #pwm-cells = <3>;
 743                                 status = "disabled";
 744                         };
 745                         timer@15 {
 746                                 compatible = "st,stm32h7-timer-trigger";
 747                                 reg = <15>;
 748                                 status = "disabled";
 749                         };
 750                 };
 751
 752                 timers17: timer@44008000 {
 753                         #address-cells = <1>;
 754                         #size-cells = <0>;
 755                         compatible = "st,stm32-timers";
 756                         reg = <0x44008000 0x400>;
 757                         clocks = <&rcc TIM17_K>;
 758                         clock-names = "int";
 759                         dmas = <&dmamux1 111 0x400 0x1>,
 760                                <&dmamux1 112 0x400 0x1>;
 761                         dma-names = "ch1", "up";
 762                         status = "disabled";
 763
 764                         pwm {
 765                                 compatible = "st,stm32-pwm";
 766                                 #pwm-cells = <3>;
 767                                 status = "disabled";
 768                         };
 769
 770                         timer@16 {
 771                                 compatible = "st,stm32h7-timer-trigger";
 772                                 reg = <16>;
 773                                 status = "disabled";
 774                         };
 775                 };
 776
 777                 spi5: spi@44009000 {
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                         compatible = "st,stm32h7-spi";
 781                         reg = <0x44009000 0x400>;
 782                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&rcc SPI5_K>;
 784                         resets = <&rcc SPI5_R>;
 785                         dmas = <&dmamux1 85 0x400 0x05>,
 786                                <&dmamux1 86 0x400 0x05>;
 787                         dma-names = "rx", "tx";
 788                         status = "disabled";
 789                 };
 790
 791                 sai1: sai@4400a000 {
 792                         compatible = "st,stm32h7-sai";
 793                         #address-cells = <1>;
 794                         #size-cells = <1>;
 795                         ranges = <0 0x4400a000 0x400>;
 796                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 797                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 798                         resets = <&rcc SAI1_R>;
 799                         status = "disabled";
 800
 801                         sai1a: audio-controller@4400a004 {
 802                                 #sound-dai-cells = <0>;
 803
 804                                 compatible = "st,stm32-sai-sub-a";
 805                                 reg = <0x4 0x1c>;
 806                                 clocks = <&rcc SAI1_K>;
 807                                 clock-names = "sai_ck";
 808                                 dmas = <&dmamux1 87 0x400 0x01>;
 809                                 status = "disabled";
 810                         };
 811
 812                         sai1b: audio-controller@4400a024 {
 813                                 #sound-dai-cells = <0>;
 814                                 compatible = "st,stm32-sai-sub-b";
 815                                 reg = <0x24 0x1c>;
 816                                 clocks = <&rcc SAI1_K>;
 817                                 clock-names = "sai_ck";
 818                                 dmas = <&dmamux1 88 0x400 0x01>;
 819                                 status = "disabled";
 820                         };
 821                 };
 822
 823                 sai2: sai@4400b000 {
 824                         compatible = "st,stm32h7-sai";
 825                         #address-cells = <1>;
 826                         #size-cells = <1>;
 827                         ranges = <0 0x4400b000 0x400>;
 828                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 829                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 830                         resets = <&rcc SAI2_R>;
 831                         status = "disabled";
 832
 833                         sai2a: audio-controller@4400b004 {
 834                                 #sound-dai-cells = <0>;
 835                                 compatible = "st,stm32-sai-sub-a";
 836                                 reg = <0x4 0x1c>;
 837                                 clocks = <&rcc SAI2_K>;
 838                                 clock-names = "sai_ck";
 839                                 dmas = <&dmamux1 89 0x400 0x01>;
 840                                 status = "disabled";
 841                         };
 842
 843                         sai2b: audio-controller@4400b024 {
 844                                 #sound-dai-cells = <0>;
 845                                 compatible = "st,stm32-sai-sub-b";
 846                                 reg = <0x24 0x1c>;
 847                                 clocks = <&rcc SAI2_K>;
 848                                 clock-names = "sai_ck";
 849                                 dmas = <&dmamux1 90 0x400 0x01>;
 850                                 status = "disabled";
 851                         };
 852                 };
 853
 854                 sai3: sai@4400c000 {
 855                         compatible = "st,stm32h7-sai";
 856                         #address-cells = <1>;
 857                         #size-cells = <1>;
 858                         ranges = <0 0x4400c000 0x400>;
 859                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 860                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 861                         resets = <&rcc SAI3_R>;
 862                         status = "disabled";
 863
 864                         sai3a: audio-controller@4400c004 {
 865                                 #sound-dai-cells = <0>;
 866                                 compatible = "st,stm32-sai-sub-a";
 867                                 reg = <0x04 0x1c>;
 868                                 clocks = <&rcc SAI3_K>;
 869                                 clock-names = "sai_ck";
 870                                 dmas = <&dmamux1 113 0x400 0x01>;
 871                                 status = "disabled";
 872                         };
 873
 874                         sai3b: audio-controller@4400c024 {
 875                                 #sound-dai-cells = <0>;
 876                                 compatible = "st,stm32-sai-sub-b";
 877                                 reg = <0x24 0x1c>;
 878                                 clocks = <&rcc SAI3_K>;
 879                                 clock-names = "sai_ck";
 880                                 dmas = <&dmamux1 114 0x400 0x01>;
 881                                 status = "disabled";
 882                         };
 883                 };
 884
 885                 dfsdm: dfsdm@4400d000 {
 886                         compatible = "st,stm32mp1-dfsdm";
 887                         reg = <0x4400d000 0x800>;
 888                         clocks = <&rcc DFSDM_K>;
 889                         clock-names = "dfsdm";
 890                         #address-cells = <1>;
 891                         #size-cells = <0>;
 892                         status = "disabled";
 893
 894                         dfsdm0: filter@0 {
 895                                 compatible = "st,stm32-dfsdm-adc";
 896                                 #io-channel-cells = <1>;
 897                                 reg = <0>;
 898                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 899                                 dmas = <&dmamux1 101 0x400 0x01>;
 900                                 dma-names = "rx";
 901                                 status = "disabled";
 902                         };
 903
 904                         dfsdm1: filter@1 {
 905                                 compatible = "st,stm32-dfsdm-adc";
 906                                 #io-channel-cells = <1>;
 907                                 reg = <1>;
 908                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 909                                 dmas = <&dmamux1 102 0x400 0x01>;
 910                                 dma-names = "rx";
 911                                 status = "disabled";
 912                         };
 913
 914                         dfsdm2: filter@2 {
 915                                 compatible = "st,stm32-dfsdm-adc";
 916                                 #io-channel-cells = <1>;
 917                                 reg = <2>;
 918                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 919                                 dmas = <&dmamux1 103 0x400 0x01>;
 920                                 dma-names = "rx";
 921                                 status = "disabled";
 922                         };
 923
 924                         dfsdm3: filter@3 {
 925                                 compatible = "st,stm32-dfsdm-adc";
 926                                 #io-channel-cells = <1>;
 927                                 reg = <3>;
 928                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 929                                 dmas = <&dmamux1 104 0x400 0x01>;
 930                                 dma-names = "rx";
 931                                 status = "disabled";
 932                         };
 933
 934                         dfsdm4: filter@4 {
 935                                 compatible = "st,stm32-dfsdm-adc";
 936                                 #io-channel-cells = <1>;
 937                                 reg = <4>;
 938                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 939                                 dmas = <&dmamux1 91 0x400 0x01>;
 940                                 dma-names = "rx";
 941                                 status = "disabled";
 942                         };
 943
 944                         dfsdm5: filter@5 {
 945                                 compatible = "st,stm32-dfsdm-adc";
 946                                 #io-channel-cells = <1>;
 947                                 reg = <5>;
 948                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 949                                 dmas = <&dmamux1 92 0x400 0x01>;
 950                                 dma-names = "rx";
 951                                 status = "disabled";
 952                         };
 953                 };
 954
 955                 dma1: dma-controller@48000000 {
 956                         compatible = "st,stm32-dma";
 957                         reg = <0x48000000 0x400>;
 958                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 959                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 960                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 961                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 962                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 963                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 964                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 965                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 966                         clocks = <&rcc DMA1>;
 967                         resets = <&rcc DMA1_R>;
 968                         #dma-cells = <4>;
 969                         st,mem2mem;
 970                         dma-requests = <8>;
 971                 };
 972
 973                 dma2: dma-controller@48001000 {
 974                         compatible = "st,stm32-dma";
 975                         reg = <0x48001000 0x400>;
 976                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 977                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 978                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 979                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 980                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 981                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 982                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 983                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 984                         clocks = <&rcc DMA2>;
 985                         resets = <&rcc DMA2_R>;
 986                         #dma-cells = <4>;
 987                         st,mem2mem;
 988                         dma-requests = <8>;
 989                 };
 990
 991                 dmamux1: dma-router@48002000 {
 992                         compatible = "st,stm32h7-dmamux";
 993                         reg = <0x48002000 0x1c>;
 994                         #dma-cells = <3>;
 995                         dma-requests = <128>;
 996                         dma-masters = <&dma1 &dma2>;
 997                         dma-channels = <16>;
 998                         clocks = <&rcc DMAMUX>;
 999                         resets = <&rcc DMAMUX_R>;
1000                 };
1001
1002                 adc: adc@48003000 {
1003                         compatible = "st,stm32mp1-adc-core";
1004                         reg = <0x48003000 0x400>;
1005                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1006                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1007                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1008                         clock-names = "bus", "adc";
1009                         interrupt-controller;
1010                         st,syscfg = <&syscfg>;
1011                         #interrupt-cells = <1>;
1012                         #address-cells = <1>;
1013                         #size-cells = <0>;
1014                         status = "disabled";
1015
1016                         adc1: adc@0 {
1017                                 compatible = "st,stm32mp1-adc";
1018                                 #io-channel-cells = <1>;
1019                                 reg = <0x0>;
1020                                 interrupt-parent = <&adc>;
1021                                 interrupts = <0>;
1022                                 dmas = <&dmamux1 9 0x400 0x01>;
1023                                 dma-names = "rx";
1024                                 status = "disabled";
1025                         };
1026
1027                         adc2: adc@100 {
1028                                 compatible = "st,stm32mp1-adc";
1029                                 #io-channel-cells = <1>;
1030                                 reg = <0x100>;
1031                                 interrupt-parent = <&adc>;
1032                                 interrupts = <1>;
1033                                 dmas = <&dmamux1 10 0x400 0x01>;
1034                                 dma-names = "rx";
1035                                 status = "disabled";
1036                         };
1037                 };
1038
1039                 sdmmc3: sdmmc@48004000 {
1040                         compatible = "arm,pl18x", "arm,primecell";
1041                         arm,primecell-periphid = <0x10153180>;
1042                         reg = <0x48004000 0x400>;
1043                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1044                         interrupt-names = "cmd_irq";
1045                         clocks = <&rcc SDMMC3_K>;
1046                         clock-names = "apb_pclk";
1047                         resets = <&rcc SDMMC3_R>;
1048                         cap-sd-highspeed;
1049                         cap-mmc-highspeed;
1050                         max-frequency = <120000000>;
1051                         status = "disabled";
1052                 };
1053
1054                 usbotg_hs: usb-otg@49000000 {
1055                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1056                         reg = <0x49000000 0x10000>;
1057                         clocks = <&rcc USBO_K>;
1058                         clock-names = "otg";
1059                         resets = <&rcc USBO_R>;
1060                         reset-names = "dwc2";
1061                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1062                         g-rx-fifo-size = <256>;
1063                         g-np-tx-fifo-size = <32>;
1064                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1065                         dr_mode = "otg";
1066                         usb33d-supply = <&usb33>;
1067                         status = "disabled";
1068                 };
1069
1070                 ipcc: mailbox@4c001000 {
1071                         compatible = "st,stm32mp1-ipcc";
1072                         #mbox-cells = <1>;
1073                         reg = <0x4c001000 0x400>;
1074                         st,proc-id = <0>;
1075                         interrupts-extended =
1076                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1077                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1078                                 <&exti 61 1>;
1079                         interrupt-names = "rx", "tx", "wakeup";
1080                         clocks = <&rcc IPCC>;
1081                         wakeup-source;
1082                         status = "disabled";
1083                 };
1084
1085                 dcmi: dcmi@4c006000 {
1086                         compatible = "st,stm32-dcmi";
1087                         reg = <0x4c006000 0x400>;
1088                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1089                         resets = <&rcc CAMITF_R>;
1090                         clocks = <&rcc DCMI>;
1091                         clock-names = "mclk";
1092                         dmas = <&dmamux1 75 0x400 0x0d>;
1093                         dma-names = "tx";
1094                         status = "disabled";
1095                 };
1096
1097                 rcc: rcc@50000000 {
1098                         compatible = "st,stm32mp1-rcc", "syscon";
1099                         reg = <0x50000000 0x1000>;
1100                         #clock-cells = <1>;
1101                         #reset-cells = <1>;
1102                 };
1103
1104                 pwr_regulators: pwr@50001000 {
1105                         compatible = "st,stm32mp1,pwr-reg";
1106                         reg = <0x50001000 0x10>;
1107
1108                         reg11: reg11 {
1109                                 regulator-name = "reg11";
1110                                 regulator-min-microvolt = <1100000>;
1111                                 regulator-max-microvolt = <1100000>;
1112                         };
1113
1114                         reg18: reg18 {
1115                                 regulator-name = "reg18";
1116                                 regulator-min-microvolt = <1800000>;
1117                                 regulator-max-microvolt = <1800000>;
1118                         };
1119
1120                         usb33: usb33 {
1121                                 regulator-name = "usb33";
1122                                 regulator-min-microvolt = <3300000>;
1123                                 regulator-max-microvolt = <3300000>;
1124                         };
1125                 };
1126
1127                 exti: interrupt-controller@5000d000 {
1128                         compatible = "st,stm32mp1-exti", "syscon";
1129                         interrupt-controller;
1130                         #interrupt-cells = <2>;
1131                         reg = <0x5000d000 0x400>;
1132                 };
1133
1134                 syscfg: syscon@50020000 {
1135                         compatible = "st,stm32mp157-syscfg", "syscon";
1136                         reg = <0x50020000 0x400>;
1137                         clocks = <&rcc SYSCFG>;
1138                 };
1139
1140                 lptimer2: timer@50021000 {
1141                         #address-cells = <1>;
1142                         #size-cells = <0>;
1143                         compatible = "st,stm32-lptimer";
1144                         reg = <0x50021000 0x400>;
1145                         clocks = <&rcc LPTIM2_K>;
1146                         clock-names = "mux";
1147                         status = "disabled";
1148
1149                         pwm {
1150                                 compatible = "st,stm32-pwm-lp";
1151                                 #pwm-cells = <3>;
1152                                 status = "disabled";
1153                         };
1154
1155                         trigger@1 {
1156                                 compatible = "st,stm32-lptimer-trigger";
1157                                 reg = <1>;
1158                                 status = "disabled";
1159                         };
1160
1161                         counter {
1162                                 compatible = "st,stm32-lptimer-counter";
1163                                 status = "disabled";
1164                         };
1165                 };
1166
1167                 lptimer3: timer@50022000 {
1168                         #address-cells = <1>;
1169                         #size-cells = <0>;
1170                         compatible = "st,stm32-lptimer";
1171                         reg = <0x50022000 0x400>;
1172                         clocks = <&rcc LPTIM3_K>;
1173                         clock-names = "mux";
1174                         status = "disabled";
1175
1176                         pwm {
1177                                 compatible = "st,stm32-pwm-lp";
1178                                 #pwm-cells = <3>;
1179                                 status = "disabled";
1180                         };
1181
1182                         trigger@2 {
1183                                 compatible = "st,stm32-lptimer-trigger";
1184                                 reg = <2>;
1185                                 status = "disabled";
1186                         };
1187                 };
1188
1189                 lptimer4: timer@50023000 {
1190                         compatible = "st,stm32-lptimer";
1191                         reg = <0x50023000 0x400>;
1192                         clocks = <&rcc LPTIM4_K>;
1193                         clock-names = "mux";
1194                         status = "disabled";
1195
1196                         pwm {
1197                                 compatible = "st,stm32-pwm-lp";
1198                                 #pwm-cells = <3>;
1199                                 status = "disabled";
1200                         };
1201                 };
1202
1203                 lptimer5: timer@50024000 {
1204                         compatible = "st,stm32-lptimer";
1205                         reg = <0x50024000 0x400>;
1206                         clocks = <&rcc LPTIM5_K>;
1207                         clock-names = "mux";
1208                         status = "disabled";
1209
1210                         pwm {
1211                                 compatible = "st,stm32-pwm-lp";
1212                                 #pwm-cells = <3>;
1213                                 status = "disabled";
1214                         };
1215                 };
1216
1217                 vrefbuf: vrefbuf@50025000 {
1218                         compatible = "st,stm32-vrefbuf";
1219                         reg = <0x50025000 0x8>;
1220                         regulator-min-microvolt = <1500000>;
1221                         regulator-max-microvolt = <2500000>;
1222                         clocks = <&rcc VREF>;
1223                         status = "disabled";
1224                 };
1225
1226                 sai4: sai@50027000 {
1227                         compatible = "st,stm32h7-sai";
1228                         #address-cells = <1>;
1229                         #size-cells = <1>;
1230                         ranges = <0 0x50027000 0x400>;
1231                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1232                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1233                         resets = <&rcc SAI4_R>;
1234                         status = "disabled";
1235
1236                         sai4a: audio-controller@50027004 {
1237                                 #sound-dai-cells = <0>;
1238                                 compatible = "st,stm32-sai-sub-a";
1239                                 reg = <0x04 0x1c>;
1240                                 clocks = <&rcc SAI4_K>;
1241                                 clock-names = "sai_ck";
1242                                 dmas = <&dmamux1 99 0x400 0x01>;
1243                                 status = "disabled";
1244                         };
1245
1246                         sai4b: audio-controller@50027024 {
1247                                 #sound-dai-cells = <0>;
1248                                 compatible = "st,stm32-sai-sub-b";
1249                                 reg = <0x24 0x1c>;
1250                                 clocks = <&rcc SAI4_K>;
1251                                 clock-names = "sai_ck";
1252                                 dmas = <&dmamux1 100 0x400 0x01>;
1253                                 status = "disabled";
1254                         };
1255                 };
1256
1257                 dts: thermal@50028000 {
1258                         compatible = "st,stm32-thermal";
1259                         reg = <0x50028000 0x100>;
1260                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1261                         clocks = <&rcc TMPSENS>;
1262                         clock-names = "pclk";
1263                         #thermal-sensor-cells = <0>;
1264                         status = "disabled";
1265                 };
1266
1267                 hash1: hash@54002000 {
1268                         compatible = "st,stm32f756-hash";
1269                         reg = <0x54002000 0x400>;
1270                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1271                         clocks = <&rcc HASH1>;
1272                         resets = <&rcc HASH1_R>;
1273                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1274                         dma-names = "in";
1275                         dma-maxburst = <2>;
1276                         status = "disabled";
1277                 };
1278
1279                 rng1: rng@54003000 {
1280                         compatible = "st,stm32-rng";
1281                         reg = <0x54003000 0x400>;
1282                         clocks = <&rcc RNG1_K>;
1283                         resets = <&rcc RNG1_R>;
1284                         status = "disabled";
1285                 };
1286
1287                 mdma1: dma-controller@58000000 {
1288                         compatible = "st,stm32h7-mdma";
1289                         reg = <0x58000000 0x1000>;
1290                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1291                         clocks = <&rcc MDMA>;
1292                         resets = <&rcc MDMA_R>;
1293                         #dma-cells = <5>;
1294                         dma-channels = <32>;
1295                         dma-requests = <48>;
1296                 };
1297
1298                 fmc: nand-controller@58002000 {
1299                         compatible = "st,stm32mp15-fmc2";
1300                         reg = <0x58002000 0x1000>,
1301                               <0x80000000 0x1000>,
1302                               <0x88010000 0x1000>,
1303                               <0x88020000 0x1000>,
1304                               <0x81000000 0x1000>,
1305                               <0x89010000 0x1000>,
1306                               <0x89020000 0x1000>;
1307                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1308                         dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1309                                <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1310                                <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1311                         dma-names = "tx", "rx", "ecc";
1312                         clocks = <&rcc FMC_K>;
1313                         resets = <&rcc FMC_R>;
1314                         status = "disabled";
1315                 };
1316
1317                 qspi: spi@58003000 {
1318                         compatible = "st,stm32f469-qspi";
1319                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1320                         reg-names = "qspi", "qspi_mm";
1321                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1322                         dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1323                                <&mdma1 22 0x10 0x100008 0x0 0x0>;
1324                         dma-names = "tx", "rx";
1325                         clocks = <&rcc QSPI_K>;
1326                         resets = <&rcc QSPI_R>;
1327                         status = "disabled";
1328                 };
1329
1330                 sdmmc1: sdmmc@58005000 {
1331                         compatible = "arm,pl18x", "arm,primecell";
1332                         arm,primecell-periphid = <0x10153180>;
1333                         reg = <0x58005000 0x1000>;
1334                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1335                         interrupt-names = "cmd_irq";
1336                         clocks = <&rcc SDMMC1_K>;
1337                         clock-names = "apb_pclk";
1338                         resets = <&rcc SDMMC1_R>;
1339                         cap-sd-highspeed;
1340                         cap-mmc-highspeed;
1341                         max-frequency = <120000000>;
1342                         status = "disabled";
1343                 };
1344
1345                 sdmmc2: sdmmc@58007000 {
1346                         compatible = "arm,pl18x", "arm,primecell";
1347                         arm,primecell-periphid = <0x10153180>;
1348                         reg = <0x58007000 0x1000>;
1349                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1350                         interrupt-names = "cmd_irq";
1351                         clocks = <&rcc SDMMC2_K>;
1352                         clock-names = "apb_pclk";
1353                         resets = <&rcc SDMMC2_R>;
1354                         cap-sd-highspeed;
1355                         cap-mmc-highspeed;
1356                         max-frequency = <120000000>;
1357                         status = "disabled";
1358                 };
1359
1360                 crc1: crc@58009000 {
1361                         compatible = "st,stm32f7-crc";
1362                         reg = <0x58009000 0x400>;
1363                         clocks = <&rcc CRC1>;
1364                         status = "disabled";
1365                 };
1366
1367                 stmmac_axi_config_0: stmmac-axi-config {
1368                         snps,wr_osr_lmt = <0x7>;
1369                         snps,rd_osr_lmt = <0x7>;
1370                         snps,blen = <0 0 0 0 16 8 4>;
1371                 };
1372
1373                 ethernet0: ethernet@5800a000 {
1374                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1375                         reg = <0x5800a000 0x2000>;
1376                         reg-names = "stmmaceth";
1377                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1378                         interrupt-names = "macirq";
1379                         clock-names = "stmmaceth",
1380                                       "mac-clk-tx",
1381                                       "mac-clk-rx",
1382                                       "eth-ck",
1383                                       "ethstp";
1384                         clocks = <&rcc ETHMAC>,
1385                                  <&rcc ETHTX>,
1386                                  <&rcc ETHRX>,
1387                                  <&rcc ETHCK_K>,
1388                                  <&rcc ETHSTP>;
1389                         st,syscon = <&syscfg 0x4>;
1390                         snps,mixed-burst;
1391                         snps,pbl = <2>;
1392                         snps,en-tx-lpi-clockgating;
1393                         snps,axi-config = <&stmmac_axi_config_0>;
1394                         snps,tso;
1395                         status = "disabled";
1396                 };
1397
1398                 usbh_ohci: usbh-ohci@5800c000 {
1399                         compatible = "generic-ohci";
1400                         reg = <0x5800c000 0x1000>;
1401                         clocks = <&rcc USBH>;
1402                         resets = <&rcc USBH_R>;
1403                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1404                         status = "disabled";
1405                 };
1406
1407                 usbh_ehci: usbh-ehci@5800d000 {
1408                         compatible = "generic-ehci";
1409                         reg = <0x5800d000 0x1000>;
1410                         clocks = <&rcc USBH>;
1411                         resets = <&rcc USBH_R>;
1412                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1413                         companion = <&usbh_ohci>;
1414                         status = "disabled";
1415                 };
1416
1417                 ltdc: display-controller@5a001000 {
1418                         compatible = "st,stm32-ltdc";
1419                         reg = <0x5a001000 0x400>;
1420                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1421                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1422                         clocks = <&rcc LTDC_PX>;
1423                         clock-names = "lcd";
1424                         resets = <&rcc LTDC_R>;
1425                         status = "disabled";
1426                 };
1427
1428                 iwdg2: watchdog@5a002000 {
1429                         compatible = "st,stm32mp1-iwdg";
1430                         reg = <0x5a002000 0x400>;
1431                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1432                         clock-names = "pclk", "lsi";
1433                         status = "disabled";
1434                 };
1435
1436                 usbphyc: usbphyc@5a006000 {
1437                         #address-cells = <1>;
1438                         #size-cells = <0>;
1439                         compatible = "st,stm32mp1-usbphyc";
1440                         reg = <0x5a006000 0x1000>;
1441                         clocks = <&rcc USBPHY_K>;
1442                         resets = <&rcc USBPHY_R>;
1443                         status = "disabled";
1444
1445                         usbphyc_port0: usb-phy@0 {
1446                                 #phy-cells = <0>;
1447                                 reg = <0>;
1448                         };
1449
1450                         usbphyc_port1: usb-phy@1 {
1451                                 #phy-cells = <1>;
1452                                 reg = <1>;
1453                         };
1454                 };
1455
1456                 usart1: serial@5c000000 {
1457                         compatible = "st,stm32h7-uart";
1458                         reg = <0x5c000000 0x400>;
1459                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1460                         clocks = <&rcc USART1_K>;
1461                         status = "disabled";
1462                 };
1463
1464                 spi6: spi@5c001000 {
1465                         #address-cells = <1>;
1466                         #size-cells = <0>;
1467                         compatible = "st,stm32h7-spi";
1468                         reg = <0x5c001000 0x400>;
1469                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1470                         clocks = <&rcc SPI6_K>;
1471                         resets = <&rcc SPI6_R>;
1472                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1473                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1474                         dma-names = "rx", "tx";
1475                         status = "disabled";
1476                 };
1477
1478                 i2c4: i2c@5c002000 {
1479                         compatible = "st,stm32f7-i2c";
1480                         reg = <0x5c002000 0x400>;
1481                         interrupt-names = "event", "error";
1482                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1483                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1484                         clocks = <&rcc I2C4_K>;
1485                         resets = <&rcc I2C4_R>;
1486                         #address-cells = <1>;
1487                         #size-cells = <0>;
1488                         wakeup-source;
1489                         status = "disabled";
1490                 };
1491
1492                 rtc: rtc@5c004000 {
1493                         compatible = "st,stm32mp1-rtc";
1494                         reg = <0x5c004000 0x400>;
1495                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1496                         clock-names = "pclk", "rtc_ck";
1497                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1498                         status = "disabled";
1499                 };
1500
1501                 bsec: efuse@5c005000 {
1502                         compatible = "st,stm32mp15-bsec";
1503                         reg = <0x5c005000 0x400>;
1504                         #address-cells = <1>;
1505                         #size-cells = <1>;
1506                         ts_cal1: calib@5c {
1507                                 reg = <0x5c 0x2>;
1508                         };
1509                         ts_cal2: calib@5e {
1510                                 reg = <0x5e 0x2>;
1511                         };
1512                 };
1513
1514                 i2c6: i2c@5c009000 {
1515                         compatible = "st,stm32f7-i2c";
1516                         reg = <0x5c009000 0x400>;
1517                         interrupt-names = "event", "error";
1518                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1519                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1520                         clocks = <&rcc I2C6_K>;
1521                         resets = <&rcc I2C6_R>;
1522                         #address-cells = <1>;
1523                         #size-cells = <0>;
1524                         wakeup-source;
1525                         status = "disabled";
1526                 };
1527
1528                 /*
1529                  * Break node order to solve dependency probe issue between
1530                  * pinctrl and exti.
1531                  */
1532                 pinctrl: pin-controller@50002000 {
1533                         #address-cells = <1>;
1534                         #size-cells = <1>;
1535                         compatible = "st,stm32mp157-pinctrl";
1536                         ranges = <0 0x50002000 0xa400>;
1537                         interrupt-parent = <&exti>;
1538                         st,syscfg = <&exti 0x60 0xff>;
1539                         pins-are-numbered;
1540
1541                         gpioa: gpio@50002000 {
1542                                 gpio-controller;
1543                                 #gpio-cells = <2>;
1544                                 interrupt-controller;
1545                                 #interrupt-cells = <2>;
1546                                 reg = <0x0 0x400>;
1547                                 clocks = <&rcc GPIOA>;
1548                                 st,bank-name = "GPIOA";
1549                                 status = "disabled";
1550                         };
1551
1552                         gpiob: gpio@50003000 {
1553                                 gpio-controller;
1554                                 #gpio-cells = <2>;
1555                                 interrupt-controller;
1556                                 #interrupt-cells = <2>;
1557                                 reg = <0x1000 0x400>;
1558                                 clocks = <&rcc GPIOB>;
1559                                 st,bank-name = "GPIOB";
1560                                 status = "disabled";
1561                         };
1562
1563                         gpioc: gpio@50004000 {
1564                                 gpio-controller;
1565                                 #gpio-cells = <2>;
1566                                 interrupt-controller;
1567                                 #interrupt-cells = <2>;
1568                                 reg = <0x2000 0x400>;
1569                                 clocks = <&rcc GPIOC>;
1570                                 st,bank-name = "GPIOC";
1571                                 status = "disabled";
1572                         };
1573
1574                         gpiod: gpio@50005000 {
1575                                 gpio-controller;
1576                                 #gpio-cells = <2>;
1577                                 interrupt-controller;
1578                                 #interrupt-cells = <2>;
1579                                 reg = <0x3000 0x400>;
1580                                 clocks = <&rcc GPIOD>;
1581                                 st,bank-name = "GPIOD";
1582                                 status = "disabled";
1583                         };
1584
1585                         gpioe: gpio@50006000 {
1586                                 gpio-controller;
1587                                 #gpio-cells = <2>;
1588                                 interrupt-controller;
1589                                 #interrupt-cells = <2>;
1590                                 reg = <0x4000 0x400>;
1591                                 clocks = <&rcc GPIOE>;
1592                                 st,bank-name = "GPIOE";
1593                                 status = "disabled";
1594                         };
1595
1596                         gpiof: gpio@50007000 {
1597                                 gpio-controller;
1598                                 #gpio-cells = <2>;
1599                                 interrupt-controller;
1600                                 #interrupt-cells = <2>;
1601                                 reg = <0x5000 0x400>;
1602                                 clocks = <&rcc GPIOF>;
1603                                 st,bank-name = "GPIOF";
1604                                 status = "disabled";
1605                         };
1606
1607                         gpiog: gpio@50008000 {
1608                                 gpio-controller;
1609                                 #gpio-cells = <2>;
1610                                 interrupt-controller;
1611                                 #interrupt-cells = <2>;
1612                                 reg = <0x6000 0x400>;
1613                                 clocks = <&rcc GPIOG>;
1614                                 st,bank-name = "GPIOG";
1615                                 status = "disabled";
1616                         };
1617
1618                         gpioh: gpio@50009000 {
1619                                 gpio-controller;
1620                                 #gpio-cells = <2>;
1621                                 interrupt-controller;
1622                                 #interrupt-cells = <2>;
1623                                 reg = <0x7000 0x400>;
1624                                 clocks = <&rcc GPIOH>;
1625                                 st,bank-name = "GPIOH";
1626                                 status = "disabled";
1627                         };
1628
1629                         gpioi: gpio@5000a000 {
1630                                 gpio-controller;
1631                                 #gpio-cells = <2>;
1632                                 interrupt-controller;
1633                                 #interrupt-cells = <2>;
1634                                 reg = <0x8000 0x400>;
1635                                 clocks = <&rcc GPIOI>;
1636                                 st,bank-name = "GPIOI";
1637                                 status = "disabled";
1638                         };
1639
1640                         gpioj: gpio@5000b000 {
1641                                 gpio-controller;
1642                                 #gpio-cells = <2>;
1643                                 interrupt-controller;
1644                                 #interrupt-cells = <2>;
1645                                 reg = <0x9000 0x400>;
1646                                 clocks = <&rcc GPIOJ>;
1647                                 st,bank-name = "GPIOJ";
1648                                 status = "disabled";
1649                         };
1650
1651                         gpiok: gpio@5000c000 {
1652                                 gpio-controller;
1653                                 #gpio-cells = <2>;
1654                                 interrupt-controller;
1655                                 #interrupt-cells = <2>;
1656                                 reg = <0xa000 0x400>;
1657                                 clocks = <&rcc GPIOK>;
1658                                 st,bank-name = "GPIOK";
1659                                 status = "disabled";
1660                         };
1661                 };
1662
1663                 pinctrl_z: pin-controller-z@54004000 {
1664                         #address-cells = <1>;
1665                         #size-cells = <1>;
1666                         compatible = "st,stm32mp157-z-pinctrl";
1667                         ranges = <0 0x54004000 0x400>;
1668                         pins-are-numbered;
1669                         interrupt-parent = <&exti>;
1670                         st,syscfg = <&exti 0x60 0xff>;
1671
1672                         gpioz: gpio@54004000 {
1673                                 gpio-controller;
1674                                 #gpio-cells = <2>;
1675                                 interrupt-controller;
1676                                 #interrupt-cells = <2>;
1677                                 reg = <0 0x400>;
1678                                 clocks = <&rcc GPIOZ>;
1679                                 st,bank-name = "GPIOZ";
1680                                 st,bank-ioport = <11>;
1681                                 status = "disabled";
1682                         };
1683                 };
1684         };
1685
1686         mlahb: ahb {
1687                 compatible = "st,mlahb", "simple-bus";
1688                 #address-cells = <1>;
1689                 #size-cells = <1>;
1690                 ranges;
1691                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1692                              <0x10000000 0x10000000 0x60000>,
1693                              <0x30000000 0x30000000 0x60000>;
1694
1695                 m4_rproc: m4@10000000 {
1696                         compatible = "st,stm32mp1-m4";
1697                         reg = <0x10000000 0x40000>,
1698                               <0x30000000 0x40000>,
1699                               <0x38000000 0x10000>;
1700                         resets = <&rcc MCU_R>;
1701                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1702                         st,syscfg-tz = <&rcc 0x000 0x1>;
1703                         status = "disabled";
1704                 };
1705         };
1706 };