1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
27 compatible = "arm,psci";
29 cpu_off = <0x84000002>;
30 cpu_on = <0x84000003>;
33 intc: interrupt-controller@a0021000 {
34 compatible = "arm,cortex-a7-gic";
35 #interrupt-cells = <3>;
37 reg = <0xa0021000 0x1000>,
42 compatible = "arm,armv7-timer";
43 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
47 interrupt-parent = <&intc>;
53 compatible = "fixed-clock";
54 clock-frequency = <24000000>;
59 compatible = "fixed-clock";
60 clock-frequency = <64000000>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
77 compatible = "fixed-clock";
78 clock-frequency = <4000000>;
83 cpu_thermal: cpu-thermal {
84 polling-delay-passive = <0>;
86 thermal-sensors = <&dts>;
89 cpu_alert1: cpu-alert1 {
90 temperature = <85000>;
96 temperature = <120000>;
107 booster: regulator-booster {
108 compatible = "st,stm32mp1-booster";
109 st,syscfg = <&syscfg>;
114 compatible = "simple-bus";
115 #address-cells = <1>;
117 interrupt-parent = <&intc>;
120 timers2: timer@40000000 {
121 #address-cells = <1>;
123 compatible = "st,stm32-timers";
124 reg = <0x40000000 0x400>;
125 clocks = <&rcc TIM2_K>;
127 dmas = <&dmamux1 18 0x400 0x1>,
128 <&dmamux1 19 0x400 0x1>,
129 <&dmamux1 20 0x400 0x1>,
130 <&dmamux1 21 0x400 0x1>,
131 <&dmamux1 22 0x400 0x1>;
132 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
136 compatible = "st,stm32-pwm";
142 compatible = "st,stm32h7-timer-trigger";
148 compatible = "st,stm32-timer-counter";
153 timers3: timer@40001000 {
154 #address-cells = <1>;
156 compatible = "st,stm32-timers";
157 reg = <0x40001000 0x400>;
158 clocks = <&rcc TIM3_K>;
160 dmas = <&dmamux1 23 0x400 0x1>,
161 <&dmamux1 24 0x400 0x1>,
162 <&dmamux1 25 0x400 0x1>,
163 <&dmamux1 26 0x400 0x1>,
164 <&dmamux1 27 0x400 0x1>,
165 <&dmamux1 28 0x400 0x1>;
166 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
170 compatible = "st,stm32-pwm";
176 compatible = "st,stm32h7-timer-trigger";
182 compatible = "st,stm32-timer-counter";
187 timers4: timer@40002000 {
188 #address-cells = <1>;
190 compatible = "st,stm32-timers";
191 reg = <0x40002000 0x400>;
192 clocks = <&rcc TIM4_K>;
194 dmas = <&dmamux1 29 0x400 0x1>,
195 <&dmamux1 30 0x400 0x1>,
196 <&dmamux1 31 0x400 0x1>,
197 <&dmamux1 32 0x400 0x1>;
198 dma-names = "ch1", "ch2", "ch3", "ch4";
202 compatible = "st,stm32-pwm";
208 compatible = "st,stm32h7-timer-trigger";
214 compatible = "st,stm32-timer-counter";
219 timers5: timer@40003000 {
220 #address-cells = <1>;
222 compatible = "st,stm32-timers";
223 reg = <0x40003000 0x400>;
224 clocks = <&rcc TIM5_K>;
226 dmas = <&dmamux1 55 0x400 0x1>,
227 <&dmamux1 56 0x400 0x1>,
228 <&dmamux1 57 0x400 0x1>,
229 <&dmamux1 58 0x400 0x1>,
230 <&dmamux1 59 0x400 0x1>,
231 <&dmamux1 60 0x400 0x1>;
232 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
236 compatible = "st,stm32-pwm";
242 compatible = "st,stm32h7-timer-trigger";
248 compatible = "st,stm32-timer-counter";
253 timers6: timer@40004000 {
254 #address-cells = <1>;
256 compatible = "st,stm32-timers";
257 reg = <0x40004000 0x400>;
258 clocks = <&rcc TIM6_K>;
260 dmas = <&dmamux1 69 0x400 0x1>;
265 compatible = "st,stm32h7-timer-trigger";
271 timers7: timer@40005000 {
272 #address-cells = <1>;
274 compatible = "st,stm32-timers";
275 reg = <0x40005000 0x400>;
276 clocks = <&rcc TIM7_K>;
278 dmas = <&dmamux1 70 0x400 0x1>;
283 compatible = "st,stm32h7-timer-trigger";
289 timers12: timer@40006000 {
290 #address-cells = <1>;
292 compatible = "st,stm32-timers";
293 reg = <0x40006000 0x400>;
294 clocks = <&rcc TIM12_K>;
299 compatible = "st,stm32-pwm";
305 compatible = "st,stm32h7-timer-trigger";
311 timers13: timer@40007000 {
312 #address-cells = <1>;
314 compatible = "st,stm32-timers";
315 reg = <0x40007000 0x400>;
316 clocks = <&rcc TIM13_K>;
321 compatible = "st,stm32-pwm";
327 compatible = "st,stm32h7-timer-trigger";
333 timers14: timer@40008000 {
334 #address-cells = <1>;
336 compatible = "st,stm32-timers";
337 reg = <0x40008000 0x400>;
338 clocks = <&rcc TIM14_K>;
343 compatible = "st,stm32-pwm";
349 compatible = "st,stm32h7-timer-trigger";
355 lptimer1: timer@40009000 {
356 #address-cells = <1>;
358 compatible = "st,stm32-lptimer";
359 reg = <0x40009000 0x400>;
360 clocks = <&rcc LPTIM1_K>;
365 compatible = "st,stm32-pwm-lp";
371 compatible = "st,stm32-lptimer-trigger";
377 compatible = "st,stm32-lptimer-counter";
383 #address-cells = <1>;
385 compatible = "st,stm32h7-spi";
386 reg = <0x4000b000 0x400>;
387 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&rcc SPI2_K>;
389 resets = <&rcc SPI2_R>;
390 dmas = <&dmamux1 39 0x400 0x05>,
391 <&dmamux1 40 0x400 0x05>;
392 dma-names = "rx", "tx";
396 i2s2: audio-controller@4000b000 {
397 compatible = "st,stm32h7-i2s";
398 #sound-dai-cells = <0>;
399 reg = <0x4000b000 0x400>;
400 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
401 dmas = <&dmamux1 39 0x400 0x01>,
402 <&dmamux1 40 0x400 0x01>;
403 dma-names = "rx", "tx";
408 #address-cells = <1>;
410 compatible = "st,stm32h7-spi";
411 reg = <0x4000c000 0x400>;
412 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&rcc SPI3_K>;
414 resets = <&rcc SPI3_R>;
415 dmas = <&dmamux1 61 0x400 0x05>,
416 <&dmamux1 62 0x400 0x05>;
417 dma-names = "rx", "tx";
421 i2s3: audio-controller@4000c000 {
422 compatible = "st,stm32h7-i2s";
423 #sound-dai-cells = <0>;
424 reg = <0x4000c000 0x400>;
425 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&dmamux1 61 0x400 0x01>,
427 <&dmamux1 62 0x400 0x01>;
428 dma-names = "rx", "tx";
432 spdifrx: audio-controller@4000d000 {
433 compatible = "st,stm32h7-spdifrx";
434 #sound-dai-cells = <0>;
435 reg = <0x4000d000 0x400>;
436 clocks = <&rcc SPDIF_K>;
437 clock-names = "kclk";
438 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
439 dmas = <&dmamux1 93 0x400 0x01>,
440 <&dmamux1 94 0x400 0x01>;
441 dma-names = "rx", "rx-ctrl";
445 usart2: serial@4000e000 {
446 compatible = "st,stm32h7-uart";
447 reg = <0x4000e000 0x400>;
448 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&rcc USART2_K>;
453 usart3: serial@4000f000 {
454 compatible = "st,stm32h7-uart";
455 reg = <0x4000f000 0x400>;
456 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&rcc USART3_K>;
461 uart4: serial@40010000 {
462 compatible = "st,stm32h7-uart";
463 reg = <0x40010000 0x400>;
464 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&rcc UART4_K>;
469 uart5: serial@40011000 {
470 compatible = "st,stm32h7-uart";
471 reg = <0x40011000 0x400>;
472 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&rcc UART5_K>;
478 compatible = "st,stm32f7-i2c";
479 reg = <0x40012000 0x400>;
480 interrupt-names = "event", "error";
481 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&rcc I2C1_K>;
484 resets = <&rcc I2C1_R>;
485 #address-cells = <1>;
492 compatible = "st,stm32f7-i2c";
493 reg = <0x40013000 0x400>;
494 interrupt-names = "event", "error";
495 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&rcc I2C2_K>;
498 resets = <&rcc I2C2_R>;
499 #address-cells = <1>;
506 compatible = "st,stm32f7-i2c";
507 reg = <0x40014000 0x400>;
508 interrupt-names = "event", "error";
509 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&rcc I2C3_K>;
512 resets = <&rcc I2C3_R>;
513 #address-cells = <1>;
520 compatible = "st,stm32f7-i2c";
521 reg = <0x40015000 0x400>;
522 interrupt-names = "event", "error";
523 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&rcc I2C5_K>;
526 resets = <&rcc I2C5_R>;
527 #address-cells = <1>;
534 compatible = "st,stm32-cec";
535 reg = <0x40016000 0x400>;
536 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&rcc CEC_K>, <&clk_lse>;
538 clock-names = "cec", "hdmi-cec";
543 compatible = "st,stm32h7-dac-core";
544 reg = <0x40017000 0x400>;
545 clocks = <&rcc DAC12>;
546 clock-names = "pclk";
547 #address-cells = <1>;
552 compatible = "st,stm32-dac";
553 #io-channels-cells = <1>;
559 compatible = "st,stm32-dac";
560 #io-channels-cells = <1>;
566 uart7: serial@40018000 {
567 compatible = "st,stm32h7-uart";
568 reg = <0x40018000 0x400>;
569 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&rcc UART7_K>;
574 uart8: serial@40019000 {
575 compatible = "st,stm32h7-uart";
576 reg = <0x40019000 0x400>;
577 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&rcc UART8_K>;
582 timers1: timer@44000000 {
583 #address-cells = <1>;
585 compatible = "st,stm32-timers";
586 reg = <0x44000000 0x400>;
587 clocks = <&rcc TIM1_K>;
589 dmas = <&dmamux1 11 0x400 0x1>,
590 <&dmamux1 12 0x400 0x1>,
591 <&dmamux1 13 0x400 0x1>,
592 <&dmamux1 14 0x400 0x1>,
593 <&dmamux1 15 0x400 0x1>,
594 <&dmamux1 16 0x400 0x1>,
595 <&dmamux1 17 0x400 0x1>;
596 dma-names = "ch1", "ch2", "ch3", "ch4",
601 compatible = "st,stm32-pwm";
607 compatible = "st,stm32h7-timer-trigger";
613 compatible = "st,stm32-timer-counter";
618 timers8: timer@44001000 {
619 #address-cells = <1>;
621 compatible = "st,stm32-timers";
622 reg = <0x44001000 0x400>;
623 clocks = <&rcc TIM8_K>;
625 dmas = <&dmamux1 47 0x400 0x1>,
626 <&dmamux1 48 0x400 0x1>,
627 <&dmamux1 49 0x400 0x1>,
628 <&dmamux1 50 0x400 0x1>,
629 <&dmamux1 51 0x400 0x1>,
630 <&dmamux1 52 0x400 0x1>,
631 <&dmamux1 53 0x400 0x1>;
632 dma-names = "ch1", "ch2", "ch3", "ch4",
637 compatible = "st,stm32-pwm";
643 compatible = "st,stm32h7-timer-trigger";
649 compatible = "st,stm32-timer-counter";
654 usart6: serial@44003000 {
655 compatible = "st,stm32h7-uart";
656 reg = <0x44003000 0x400>;
657 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&rcc USART6_K>;
663 #address-cells = <1>;
665 compatible = "st,stm32h7-spi";
666 reg = <0x44004000 0x400>;
667 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&rcc SPI1_K>;
669 resets = <&rcc SPI1_R>;
670 dmas = <&dmamux1 37 0x400 0x05>,
671 <&dmamux1 38 0x400 0x05>;
672 dma-names = "rx", "tx";
676 i2s1: audio-controller@44004000 {
677 compatible = "st,stm32h7-i2s";
678 #sound-dai-cells = <0>;
679 reg = <0x44004000 0x400>;
680 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
681 dmas = <&dmamux1 37 0x400 0x01>,
682 <&dmamux1 38 0x400 0x01>;
683 dma-names = "rx", "tx";
688 #address-cells = <1>;
690 compatible = "st,stm32h7-spi";
691 reg = <0x44005000 0x400>;
692 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&rcc SPI4_K>;
694 resets = <&rcc SPI4_R>;
695 dmas = <&dmamux1 83 0x400 0x05>,
696 <&dmamux1 84 0x400 0x05>;
697 dma-names = "rx", "tx";
701 timers15: timer@44006000 {
702 #address-cells = <1>;
704 compatible = "st,stm32-timers";
705 reg = <0x44006000 0x400>;
706 clocks = <&rcc TIM15_K>;
708 dmas = <&dmamux1 105 0x400 0x1>,
709 <&dmamux1 106 0x400 0x1>,
710 <&dmamux1 107 0x400 0x1>,
711 <&dmamux1 108 0x400 0x1>;
712 dma-names = "ch1", "up", "trig", "com";
716 compatible = "st,stm32-pwm";
722 compatible = "st,stm32h7-timer-trigger";
728 timers16: timer@44007000 {
729 #address-cells = <1>;
731 compatible = "st,stm32-timers";
732 reg = <0x44007000 0x400>;
733 clocks = <&rcc TIM16_K>;
735 dmas = <&dmamux1 109 0x400 0x1>,
736 <&dmamux1 110 0x400 0x1>;
737 dma-names = "ch1", "up";
741 compatible = "st,stm32-pwm";
746 compatible = "st,stm32h7-timer-trigger";
752 timers17: timer@44008000 {
753 #address-cells = <1>;
755 compatible = "st,stm32-timers";
756 reg = <0x44008000 0x400>;
757 clocks = <&rcc TIM17_K>;
759 dmas = <&dmamux1 111 0x400 0x1>,
760 <&dmamux1 112 0x400 0x1>;
761 dma-names = "ch1", "up";
765 compatible = "st,stm32-pwm";
771 compatible = "st,stm32h7-timer-trigger";
778 #address-cells = <1>;
780 compatible = "st,stm32h7-spi";
781 reg = <0x44009000 0x400>;
782 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&rcc SPI5_K>;
784 resets = <&rcc SPI5_R>;
785 dmas = <&dmamux1 85 0x400 0x05>,
786 <&dmamux1 86 0x400 0x05>;
787 dma-names = "rx", "tx";
792 compatible = "st,stm32h7-sai";
793 #address-cells = <1>;
795 ranges = <0 0x4400a000 0x400>;
796 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
797 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
798 resets = <&rcc SAI1_R>;
801 sai1a: audio-controller@4400a004 {
802 #sound-dai-cells = <0>;
804 compatible = "st,stm32-sai-sub-a";
806 clocks = <&rcc SAI1_K>;
807 clock-names = "sai_ck";
808 dmas = <&dmamux1 87 0x400 0x01>;
812 sai1b: audio-controller@4400a024 {
813 #sound-dai-cells = <0>;
814 compatible = "st,stm32-sai-sub-b";
816 clocks = <&rcc SAI1_K>;
817 clock-names = "sai_ck";
818 dmas = <&dmamux1 88 0x400 0x01>;
824 compatible = "st,stm32h7-sai";
825 #address-cells = <1>;
827 ranges = <0 0x4400b000 0x400>;
828 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
829 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
830 resets = <&rcc SAI2_R>;
833 sai2a: audio-controller@4400b004 {
834 #sound-dai-cells = <0>;
835 compatible = "st,stm32-sai-sub-a";
837 clocks = <&rcc SAI2_K>;
838 clock-names = "sai_ck";
839 dmas = <&dmamux1 89 0x400 0x01>;
843 sai2b: audio-controller@4400b024 {
844 #sound-dai-cells = <0>;
845 compatible = "st,stm32-sai-sub-b";
847 clocks = <&rcc SAI2_K>;
848 clock-names = "sai_ck";
849 dmas = <&dmamux1 90 0x400 0x01>;
855 compatible = "st,stm32h7-sai";
856 #address-cells = <1>;
858 ranges = <0 0x4400c000 0x400>;
859 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
860 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
861 resets = <&rcc SAI3_R>;
864 sai3a: audio-controller@4400c004 {
865 #sound-dai-cells = <0>;
866 compatible = "st,stm32-sai-sub-a";
868 clocks = <&rcc SAI3_K>;
869 clock-names = "sai_ck";
870 dmas = <&dmamux1 113 0x400 0x01>;
874 sai3b: audio-controller@4400c024 {
875 #sound-dai-cells = <0>;
876 compatible = "st,stm32-sai-sub-b";
878 clocks = <&rcc SAI3_K>;
879 clock-names = "sai_ck";
880 dmas = <&dmamux1 114 0x400 0x01>;
885 dfsdm: dfsdm@4400d000 {
886 compatible = "st,stm32mp1-dfsdm";
887 reg = <0x4400d000 0x800>;
888 clocks = <&rcc DFSDM_K>;
889 clock-names = "dfsdm";
890 #address-cells = <1>;
895 compatible = "st,stm32-dfsdm-adc";
896 #io-channel-cells = <1>;
898 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
899 dmas = <&dmamux1 101 0x400 0x01>;
905 compatible = "st,stm32-dfsdm-adc";
906 #io-channel-cells = <1>;
908 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
909 dmas = <&dmamux1 102 0x400 0x01>;
915 compatible = "st,stm32-dfsdm-adc";
916 #io-channel-cells = <1>;
918 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
919 dmas = <&dmamux1 103 0x400 0x01>;
925 compatible = "st,stm32-dfsdm-adc";
926 #io-channel-cells = <1>;
928 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
929 dmas = <&dmamux1 104 0x400 0x01>;
935 compatible = "st,stm32-dfsdm-adc";
936 #io-channel-cells = <1>;
938 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
939 dmas = <&dmamux1 91 0x400 0x01>;
945 compatible = "st,stm32-dfsdm-adc";
946 #io-channel-cells = <1>;
948 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
949 dmas = <&dmamux1 92 0x400 0x01>;
955 dma1: dma-controller@48000000 {
956 compatible = "st,stm32-dma";
957 reg = <0x48000000 0x400>;
958 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&rcc DMA1>;
967 resets = <&rcc DMA1_R>;
973 dma2: dma-controller@48001000 {
974 compatible = "st,stm32-dma";
975 reg = <0x48001000 0x400>;
976 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&rcc DMA2>;
985 resets = <&rcc DMA2_R>;
991 dmamux1: dma-router@48002000 {
992 compatible = "st,stm32h7-dmamux";
993 reg = <0x48002000 0x1c>;
995 dma-requests = <128>;
996 dma-masters = <&dma1 &dma2>;
998 clocks = <&rcc DMAMUX>;
999 resets = <&rcc DMAMUX_R>;
1003 compatible = "st,stm32mp1-adc-core";
1004 reg = <0x48003000 0x400>;
1005 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1008 clock-names = "bus", "adc";
1009 interrupt-controller;
1010 st,syscfg = <&syscfg>;
1011 #interrupt-cells = <1>;
1012 #address-cells = <1>;
1014 status = "disabled";
1017 compatible = "st,stm32mp1-adc";
1018 #io-channel-cells = <1>;
1020 interrupt-parent = <&adc>;
1022 dmas = <&dmamux1 9 0x400 0x01>;
1024 status = "disabled";
1028 compatible = "st,stm32mp1-adc";
1029 #io-channel-cells = <1>;
1031 interrupt-parent = <&adc>;
1033 dmas = <&dmamux1 10 0x400 0x01>;
1035 status = "disabled";
1039 sdmmc3: sdmmc@48004000 {
1040 compatible = "arm,pl18x", "arm,primecell";
1041 arm,primecell-periphid = <0x10153180>;
1042 reg = <0x48004000 0x400>;
1043 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1044 interrupt-names = "cmd_irq";
1045 clocks = <&rcc SDMMC3_K>;
1046 clock-names = "apb_pclk";
1047 resets = <&rcc SDMMC3_R>;
1050 max-frequency = <120000000>;
1051 status = "disabled";
1054 usbotg_hs: usb-otg@49000000 {
1055 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1056 reg = <0x49000000 0x10000>;
1057 clocks = <&rcc USBO_K>;
1058 clock-names = "otg";
1059 resets = <&rcc USBO_R>;
1060 reset-names = "dwc2";
1061 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1062 g-rx-fifo-size = <256>;
1063 g-np-tx-fifo-size = <32>;
1064 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1066 usb33d-supply = <&usb33>;
1067 status = "disabled";
1070 ipcc: mailbox@4c001000 {
1071 compatible = "st,stm32mp1-ipcc";
1073 reg = <0x4c001000 0x400>;
1075 interrupts-extended =
1076 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1077 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1079 interrupt-names = "rx", "tx", "wakeup";
1080 clocks = <&rcc IPCC>;
1082 status = "disabled";
1085 dcmi: dcmi@4c006000 {
1086 compatible = "st,stm32-dcmi";
1087 reg = <0x4c006000 0x400>;
1088 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1089 resets = <&rcc CAMITF_R>;
1090 clocks = <&rcc DCMI>;
1091 clock-names = "mclk";
1092 dmas = <&dmamux1 75 0x400 0x0d>;
1094 status = "disabled";
1098 compatible = "st,stm32mp1-rcc", "syscon";
1099 reg = <0x50000000 0x1000>;
1104 pwr_regulators: pwr@50001000 {
1105 compatible = "st,stm32mp1,pwr-reg";
1106 reg = <0x50001000 0x10>;
1109 regulator-name = "reg11";
1110 regulator-min-microvolt = <1100000>;
1111 regulator-max-microvolt = <1100000>;
1115 regulator-name = "reg18";
1116 regulator-min-microvolt = <1800000>;
1117 regulator-max-microvolt = <1800000>;
1121 regulator-name = "usb33";
1122 regulator-min-microvolt = <3300000>;
1123 regulator-max-microvolt = <3300000>;
1127 exti: interrupt-controller@5000d000 {
1128 compatible = "st,stm32mp1-exti", "syscon";
1129 interrupt-controller;
1130 #interrupt-cells = <2>;
1131 reg = <0x5000d000 0x400>;
1134 syscfg: syscon@50020000 {
1135 compatible = "st,stm32mp157-syscfg", "syscon";
1136 reg = <0x50020000 0x400>;
1137 clocks = <&rcc SYSCFG>;
1140 lptimer2: timer@50021000 {
1141 #address-cells = <1>;
1143 compatible = "st,stm32-lptimer";
1144 reg = <0x50021000 0x400>;
1145 clocks = <&rcc LPTIM2_K>;
1146 clock-names = "mux";
1147 status = "disabled";
1150 compatible = "st,stm32-pwm-lp";
1152 status = "disabled";
1156 compatible = "st,stm32-lptimer-trigger";
1158 status = "disabled";
1162 compatible = "st,stm32-lptimer-counter";
1163 status = "disabled";
1167 lptimer3: timer@50022000 {
1168 #address-cells = <1>;
1170 compatible = "st,stm32-lptimer";
1171 reg = <0x50022000 0x400>;
1172 clocks = <&rcc LPTIM3_K>;
1173 clock-names = "mux";
1174 status = "disabled";
1177 compatible = "st,stm32-pwm-lp";
1179 status = "disabled";
1183 compatible = "st,stm32-lptimer-trigger";
1185 status = "disabled";
1189 lptimer4: timer@50023000 {
1190 compatible = "st,stm32-lptimer";
1191 reg = <0x50023000 0x400>;
1192 clocks = <&rcc LPTIM4_K>;
1193 clock-names = "mux";
1194 status = "disabled";
1197 compatible = "st,stm32-pwm-lp";
1199 status = "disabled";
1203 lptimer5: timer@50024000 {
1204 compatible = "st,stm32-lptimer";
1205 reg = <0x50024000 0x400>;
1206 clocks = <&rcc LPTIM5_K>;
1207 clock-names = "mux";
1208 status = "disabled";
1211 compatible = "st,stm32-pwm-lp";
1213 status = "disabled";
1217 vrefbuf: vrefbuf@50025000 {
1218 compatible = "st,stm32-vrefbuf";
1219 reg = <0x50025000 0x8>;
1220 regulator-min-microvolt = <1500000>;
1221 regulator-max-microvolt = <2500000>;
1222 clocks = <&rcc VREF>;
1223 status = "disabled";
1226 sai4: sai@50027000 {
1227 compatible = "st,stm32h7-sai";
1228 #address-cells = <1>;
1230 ranges = <0 0x50027000 0x400>;
1231 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1232 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1233 resets = <&rcc SAI4_R>;
1234 status = "disabled";
1236 sai4a: audio-controller@50027004 {
1237 #sound-dai-cells = <0>;
1238 compatible = "st,stm32-sai-sub-a";
1240 clocks = <&rcc SAI4_K>;
1241 clock-names = "sai_ck";
1242 dmas = <&dmamux1 99 0x400 0x01>;
1243 status = "disabled";
1246 sai4b: audio-controller@50027024 {
1247 #sound-dai-cells = <0>;
1248 compatible = "st,stm32-sai-sub-b";
1250 clocks = <&rcc SAI4_K>;
1251 clock-names = "sai_ck";
1252 dmas = <&dmamux1 100 0x400 0x01>;
1253 status = "disabled";
1257 dts: thermal@50028000 {
1258 compatible = "st,stm32-thermal";
1259 reg = <0x50028000 0x100>;
1260 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&rcc TMPSENS>;
1262 clock-names = "pclk";
1263 #thermal-sensor-cells = <0>;
1264 status = "disabled";
1267 hash1: hash@54002000 {
1268 compatible = "st,stm32f756-hash";
1269 reg = <0x54002000 0x400>;
1270 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&rcc HASH1>;
1272 resets = <&rcc HASH1_R>;
1273 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1276 status = "disabled";
1279 rng1: rng@54003000 {
1280 compatible = "st,stm32-rng";
1281 reg = <0x54003000 0x400>;
1282 clocks = <&rcc RNG1_K>;
1283 resets = <&rcc RNG1_R>;
1284 status = "disabled";
1287 mdma1: dma-controller@58000000 {
1288 compatible = "st,stm32h7-mdma";
1289 reg = <0x58000000 0x1000>;
1290 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1291 clocks = <&rcc MDMA>;
1292 resets = <&rcc MDMA_R>;
1294 dma-channels = <32>;
1295 dma-requests = <48>;
1298 fmc: nand-controller@58002000 {
1299 compatible = "st,stm32mp15-fmc2";
1300 reg = <0x58002000 0x1000>,
1301 <0x80000000 0x1000>,
1302 <0x88010000 0x1000>,
1303 <0x88020000 0x1000>,
1304 <0x81000000 0x1000>,
1305 <0x89010000 0x1000>,
1306 <0x89020000 0x1000>;
1307 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1308 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1309 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1310 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1311 dma-names = "tx", "rx", "ecc";
1312 clocks = <&rcc FMC_K>;
1313 resets = <&rcc FMC_R>;
1314 status = "disabled";
1317 qspi: spi@58003000 {
1318 compatible = "st,stm32f469-qspi";
1319 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1320 reg-names = "qspi", "qspi_mm";
1321 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1322 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1323 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1324 dma-names = "tx", "rx";
1325 clocks = <&rcc QSPI_K>;
1326 resets = <&rcc QSPI_R>;
1327 status = "disabled";
1330 sdmmc1: sdmmc@58005000 {
1331 compatible = "arm,pl18x", "arm,primecell";
1332 arm,primecell-periphid = <0x10153180>;
1333 reg = <0x58005000 0x1000>;
1334 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1335 interrupt-names = "cmd_irq";
1336 clocks = <&rcc SDMMC1_K>;
1337 clock-names = "apb_pclk";
1338 resets = <&rcc SDMMC1_R>;
1341 max-frequency = <120000000>;
1342 status = "disabled";
1345 sdmmc2: sdmmc@58007000 {
1346 compatible = "arm,pl18x", "arm,primecell";
1347 arm,primecell-periphid = <0x10153180>;
1348 reg = <0x58007000 0x1000>;
1349 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-names = "cmd_irq";
1351 clocks = <&rcc SDMMC2_K>;
1352 clock-names = "apb_pclk";
1353 resets = <&rcc SDMMC2_R>;
1356 max-frequency = <120000000>;
1357 status = "disabled";
1360 crc1: crc@58009000 {
1361 compatible = "st,stm32f7-crc";
1362 reg = <0x58009000 0x400>;
1363 clocks = <&rcc CRC1>;
1364 status = "disabled";
1367 stmmac_axi_config_0: stmmac-axi-config {
1368 snps,wr_osr_lmt = <0x7>;
1369 snps,rd_osr_lmt = <0x7>;
1370 snps,blen = <0 0 0 0 16 8 4>;
1373 ethernet0: ethernet@5800a000 {
1374 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1375 reg = <0x5800a000 0x2000>;
1376 reg-names = "stmmaceth";
1377 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1378 interrupt-names = "macirq";
1379 clock-names = "stmmaceth",
1384 clocks = <&rcc ETHMAC>,
1389 st,syscon = <&syscfg 0x4>;
1392 snps,en-tx-lpi-clockgating;
1393 snps,axi-config = <&stmmac_axi_config_0>;
1395 status = "disabled";
1398 usbh_ohci: usbh-ohci@5800c000 {
1399 compatible = "generic-ohci";
1400 reg = <0x5800c000 0x1000>;
1401 clocks = <&rcc USBH>;
1402 resets = <&rcc USBH_R>;
1403 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1404 status = "disabled";
1407 usbh_ehci: usbh-ehci@5800d000 {
1408 compatible = "generic-ehci";
1409 reg = <0x5800d000 0x1000>;
1410 clocks = <&rcc USBH>;
1411 resets = <&rcc USBH_R>;
1412 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1413 companion = <&usbh_ohci>;
1414 status = "disabled";
1417 ltdc: display-controller@5a001000 {
1418 compatible = "st,stm32-ltdc";
1419 reg = <0x5a001000 0x400>;
1420 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&rcc LTDC_PX>;
1423 clock-names = "lcd";
1424 resets = <&rcc LTDC_R>;
1425 status = "disabled";
1428 iwdg2: watchdog@5a002000 {
1429 compatible = "st,stm32mp1-iwdg";
1430 reg = <0x5a002000 0x400>;
1431 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1432 clock-names = "pclk", "lsi";
1433 status = "disabled";
1436 usbphyc: usbphyc@5a006000 {
1437 #address-cells = <1>;
1439 compatible = "st,stm32mp1-usbphyc";
1440 reg = <0x5a006000 0x1000>;
1441 clocks = <&rcc USBPHY_K>;
1442 resets = <&rcc USBPHY_R>;
1443 status = "disabled";
1445 usbphyc_port0: usb-phy@0 {
1450 usbphyc_port1: usb-phy@1 {
1456 usart1: serial@5c000000 {
1457 compatible = "st,stm32h7-uart";
1458 reg = <0x5c000000 0x400>;
1459 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1460 clocks = <&rcc USART1_K>;
1461 status = "disabled";
1464 spi6: spi@5c001000 {
1465 #address-cells = <1>;
1467 compatible = "st,stm32h7-spi";
1468 reg = <0x5c001000 0x400>;
1469 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&rcc SPI6_K>;
1471 resets = <&rcc SPI6_R>;
1472 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1473 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1474 dma-names = "rx", "tx";
1475 status = "disabled";
1478 i2c4: i2c@5c002000 {
1479 compatible = "st,stm32f7-i2c";
1480 reg = <0x5c002000 0x400>;
1481 interrupt-names = "event", "error";
1482 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&rcc I2C4_K>;
1485 resets = <&rcc I2C4_R>;
1486 #address-cells = <1>;
1489 status = "disabled";
1493 compatible = "st,stm32mp1-rtc";
1494 reg = <0x5c004000 0x400>;
1495 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1496 clock-names = "pclk", "rtc_ck";
1497 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1498 status = "disabled";
1501 bsec: efuse@5c005000 {
1502 compatible = "st,stm32mp15-bsec";
1503 reg = <0x5c005000 0x400>;
1504 #address-cells = <1>;
1514 i2c6: i2c@5c009000 {
1515 compatible = "st,stm32f7-i2c";
1516 reg = <0x5c009000 0x400>;
1517 interrupt-names = "event", "error";
1518 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1520 clocks = <&rcc I2C6_K>;
1521 resets = <&rcc I2C6_R>;
1522 #address-cells = <1>;
1525 status = "disabled";
1529 * Break node order to solve dependency probe issue between
1532 pinctrl: pin-controller@50002000 {
1533 #address-cells = <1>;
1535 compatible = "st,stm32mp157-pinctrl";
1536 ranges = <0 0x50002000 0xa400>;
1537 interrupt-parent = <&exti>;
1538 st,syscfg = <&exti 0x60 0xff>;
1541 gpioa: gpio@50002000 {
1544 interrupt-controller;
1545 #interrupt-cells = <2>;
1547 clocks = <&rcc GPIOA>;
1548 st,bank-name = "GPIOA";
1549 status = "disabled";
1552 gpiob: gpio@50003000 {
1555 interrupt-controller;
1556 #interrupt-cells = <2>;
1557 reg = <0x1000 0x400>;
1558 clocks = <&rcc GPIOB>;
1559 st,bank-name = "GPIOB";
1560 status = "disabled";
1563 gpioc: gpio@50004000 {
1566 interrupt-controller;
1567 #interrupt-cells = <2>;
1568 reg = <0x2000 0x400>;
1569 clocks = <&rcc GPIOC>;
1570 st,bank-name = "GPIOC";
1571 status = "disabled";
1574 gpiod: gpio@50005000 {
1577 interrupt-controller;
1578 #interrupt-cells = <2>;
1579 reg = <0x3000 0x400>;
1580 clocks = <&rcc GPIOD>;
1581 st,bank-name = "GPIOD";
1582 status = "disabled";
1585 gpioe: gpio@50006000 {
1588 interrupt-controller;
1589 #interrupt-cells = <2>;
1590 reg = <0x4000 0x400>;
1591 clocks = <&rcc GPIOE>;
1592 st,bank-name = "GPIOE";
1593 status = "disabled";
1596 gpiof: gpio@50007000 {
1599 interrupt-controller;
1600 #interrupt-cells = <2>;
1601 reg = <0x5000 0x400>;
1602 clocks = <&rcc GPIOF>;
1603 st,bank-name = "GPIOF";
1604 status = "disabled";
1607 gpiog: gpio@50008000 {
1610 interrupt-controller;
1611 #interrupt-cells = <2>;
1612 reg = <0x6000 0x400>;
1613 clocks = <&rcc GPIOG>;
1614 st,bank-name = "GPIOG";
1615 status = "disabled";
1618 gpioh: gpio@50009000 {
1621 interrupt-controller;
1622 #interrupt-cells = <2>;
1623 reg = <0x7000 0x400>;
1624 clocks = <&rcc GPIOH>;
1625 st,bank-name = "GPIOH";
1626 status = "disabled";
1629 gpioi: gpio@5000a000 {
1632 interrupt-controller;
1633 #interrupt-cells = <2>;
1634 reg = <0x8000 0x400>;
1635 clocks = <&rcc GPIOI>;
1636 st,bank-name = "GPIOI";
1637 status = "disabled";
1640 gpioj: gpio@5000b000 {
1643 interrupt-controller;
1644 #interrupt-cells = <2>;
1645 reg = <0x9000 0x400>;
1646 clocks = <&rcc GPIOJ>;
1647 st,bank-name = "GPIOJ";
1648 status = "disabled";
1651 gpiok: gpio@5000c000 {
1654 interrupt-controller;
1655 #interrupt-cells = <2>;
1656 reg = <0xa000 0x400>;
1657 clocks = <&rcc GPIOK>;
1658 st,bank-name = "GPIOK";
1659 status = "disabled";
1663 pinctrl_z: pin-controller-z@54004000 {
1664 #address-cells = <1>;
1666 compatible = "st,stm32mp157-z-pinctrl";
1667 ranges = <0 0x54004000 0x400>;
1669 interrupt-parent = <&exti>;
1670 st,syscfg = <&exti 0x60 0xff>;
1672 gpioz: gpio@54004000 {
1675 interrupt-controller;
1676 #interrupt-cells = <2>;
1678 clocks = <&rcc GPIOZ>;
1679 st,bank-name = "GPIOZ";
1680 st,bank-ioport = <11>;
1681 status = "disabled";
1687 compatible = "st,mlahb", "simple-bus";
1688 #address-cells = <1>;
1691 dma-ranges = <0x00000000 0x38000000 0x10000>,
1692 <0x10000000 0x10000000 0x60000>,
1693 <0x30000000 0x30000000 0x60000>;
1695 m4_rproc: m4@10000000 {
1696 compatible = "st,stm32mp1-m4";
1697 reg = <0x10000000 0x40000>,
1698 <0x30000000 0x40000>,
1699 <0x38000000 0x10000>;
1700 resets = <&rcc MCU_R>;
1701 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1702 st,syscfg-tz = <&rcc 0x000 0x1>;
1703 status = "disabled";