2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
78 timer2: timer@40000000 {
79 compatible = "st,stm32-timer";
80 reg = <0x40000000 0x400>;
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
86 timers2: timers@40000000 {
89 compatible = "st,stm32-timers";
90 reg = <0x40000000 0x400>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
96 compatible = "st,stm32-pwm";
102 compatible = "st,stm32-timer-trigger";
108 timer3: timer@40000400 {
109 compatible = "st,stm32-timer";
110 reg = <0x40000400 0x400>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
116 timers3: timers@40000400 {
117 #address-cells = <1>;
119 compatible = "st,stm32-timers";
120 reg = <0x40000400 0x400>;
121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
126 compatible = "st,stm32-pwm";
132 compatible = "st,stm32-timer-trigger";
138 timer4: timer@40000800 {
139 compatible = "st,stm32-timer";
140 reg = <0x40000800 0x400>;
142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
146 timers4: timers@40000800 {
147 #address-cells = <1>;
149 compatible = "st,stm32-timers";
150 reg = <0x40000800 0x400>;
151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
156 compatible = "st,stm32-pwm";
162 compatible = "st,stm32-timer-trigger";
168 timer5: timer@40000c00 {
169 compatible = "st,stm32-timer";
170 reg = <0x40000c00 0x400>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
175 timers5: timers@40000c00 {
176 #address-cells = <1>;
178 compatible = "st,stm32-timers";
179 reg = <0x40000C00 0x400>;
180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
185 compatible = "st,stm32-pwm";
191 compatible = "st,stm32-timer-trigger";
197 timer6: timer@40001000 {
198 compatible = "st,stm32-timer";
199 reg = <0x40001000 0x400>;
201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
205 timers6: timers@40001000 {
206 #address-cells = <1>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
210 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
215 compatible = "st,stm32-timer-trigger";
221 timer7: timer@40001400 {
222 compatible = "st,stm32-timer";
223 reg = <0x40001400 0x400>;
225 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
229 timers7: timers@40001400 {
230 #address-cells = <1>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
234 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
239 compatible = "st,stm32-timer-trigger";
245 timers12: timers@40001800 {
246 #address-cells = <1>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
250 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
255 compatible = "st,stm32-pwm";
261 compatible = "st,stm32-timer-trigger";
267 timers13: timers@40001c00 {
268 compatible = "st,stm32-timers";
269 reg = <0x40001C00 0x400>;
270 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
275 compatible = "st,stm32-pwm";
281 timers14: timers@40002000 {
282 compatible = "st,stm32-timers";
283 reg = <0x40002000 0x400>;
284 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
289 compatible = "st,stm32-pwm";
296 compatible = "st,stm32-rtc";
297 reg = <0x40002800 0x400>;
298 clocks = <&rcc 1 CLK_RTC>;
299 assigned-clocks = <&rcc 1 CLK_RTC>;
300 assigned-clock-parents = <&rcc 1 CLK_LSE>;
301 interrupt-parent = <&exti>;
303 st,syscfg = <&pwrcfg 0x00 0x100>;
307 usart2: serial@40004400 {
308 compatible = "st,stm32f7-uart";
309 reg = <0x40004400 0x400>;
311 clocks = <&rcc 1 CLK_USART2>;
315 usart3: serial@40004800 {
316 compatible = "st,stm32f7-uart";
317 reg = <0x40004800 0x400>;
319 clocks = <&rcc 1 CLK_USART3>;
323 usart4: serial@40004c00 {
324 compatible = "st,stm32f7-uart";
325 reg = <0x40004c00 0x400>;
327 clocks = <&rcc 1 CLK_UART4>;
331 usart5: serial@40005000 {
332 compatible = "st,stm32f7-uart";
333 reg = <0x40005000 0x400>;
335 clocks = <&rcc 1 CLK_UART5>;
340 compatible = "st,stm32f7-i2c";
341 reg = <0x40005400 0x400>;
344 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
345 clocks = <&rcc 1 CLK_I2C1>;
346 #address-cells = <1>;
352 compatible = "st,stm32f7-i2c";
353 reg = <0x40005800 0x400>;
356 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
357 clocks = <&rcc 1 CLK_I2C2>;
358 #address-cells = <1>;
364 compatible = "st,stm32f7-i2c";
365 reg = <0x40005c00 0x400>;
368 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
369 clocks = <&rcc 1 CLK_I2C3>;
370 #address-cells = <1>;
376 compatible = "st,stm32f7-i2c";
377 reg = <0x40006000 0x400>;
380 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
381 clocks = <&rcc 1 CLK_I2C4>;
382 #address-cells = <1>;
388 compatible = "st,stm32-cec";
389 reg = <0x40006C00 0x400>;
391 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
392 clock-names = "cec", "hdmi-cec";
396 usart7: serial@40007800 {
397 compatible = "st,stm32f7-uart";
398 reg = <0x40007800 0x400>;
400 clocks = <&rcc 1 CLK_UART7>;
404 usart8: serial@40007c00 {
405 compatible = "st,stm32f7-uart";
406 reg = <0x40007c00 0x400>;
408 clocks = <&rcc 1 CLK_UART8>;
412 timers1: timers@40010000 {
413 #address-cells = <1>;
415 compatible = "st,stm32-timers";
416 reg = <0x40010000 0x400>;
417 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
422 compatible = "st,stm32-pwm";
428 compatible = "st,stm32-timer-trigger";
434 timers8: timers@40010400 {
435 #address-cells = <1>;
437 compatible = "st,stm32-timers";
438 reg = <0x40010400 0x400>;
439 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
444 compatible = "st,stm32-pwm";
450 compatible = "st,stm32-timer-trigger";
456 usart1: serial@40011000 {
457 compatible = "st,stm32f7-uart";
458 reg = <0x40011000 0x400>;
460 clocks = <&rcc 1 CLK_USART1>;
464 usart6: serial@40011400 {
465 compatible = "st,stm32f7-uart";
466 reg = <0x40011400 0x400>;
468 clocks = <&rcc 1 CLK_USART6>;
472 sdio2: mmc@40011c00 {
473 compatible = "arm,pl180", "arm,primecell";
474 arm,primecell-periphid = <0x00880180>;
475 reg = <0x40011c00 0x400>;
476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
477 clock-names = "apb_pclk";
479 max-frequency = <48000000>;
483 sdio1: mmc@40012c00 {
484 compatible = "arm,pl180", "arm,primecell";
485 arm,primecell-periphid = <0x00880180>;
486 reg = <0x40012c00 0x400>;
487 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
488 clock-names = "apb_pclk";
490 max-frequency = <48000000>;
494 syscfg: syscon@40013800 {
495 compatible = "st,stm32-syscfg", "syscon";
496 reg = <0x40013800 0x400>;
499 exti: interrupt-controller@40013c00 {
500 compatible = "st,stm32-exti";
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 reg = <0x40013C00 0x400>;
504 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
507 timers9: timers@40014000 {
508 #address-cells = <1>;
510 compatible = "st,stm32-timers";
511 reg = <0x40014000 0x400>;
512 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
517 compatible = "st,stm32-pwm";
523 compatible = "st,stm32-timer-trigger";
529 timers10: timers@40014400 {
530 compatible = "st,stm32-timers";
531 reg = <0x40014400 0x400>;
532 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
537 compatible = "st,stm32-pwm";
543 timers11: timers@40014800 {
544 compatible = "st,stm32-timers";
545 reg = <0x40014800 0x400>;
546 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
551 compatible = "st,stm32-pwm";
557 pwrcfg: power-config@40007000 {
558 compatible = "st,stm32-power-config", "syscon";
559 reg = <0x40007000 0x400>;
563 compatible = "st,stm32f7-crc";
564 reg = <0x40023000 0x400>;
565 clocks = <&rcc 0 12>;
572 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
573 reg = <0x40023800 0x400>;
574 clocks = <&clk_hse>, <&clk_i2s_ckin>;
575 st,syscfg = <&pwrcfg>;
576 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
577 assigned-clock-rates = <1000000>;
580 dma1: dma-controller@40026000 {
581 compatible = "st,stm32-dma";
582 reg = <0x40026000 0x400>;
591 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
596 dma2: dma-controller@40026400 {
597 compatible = "st,stm32-dma";
598 reg = <0x40026400 0x400>;
607 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
613 usbotg_hs: usb@40040000 {
614 compatible = "st,stm32f7-hsotg";
615 reg = <0x40040000 0x40000>;
617 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
619 g-rx-fifo-size = <256>;
620 g-np-tx-fifo-size = <32>;
621 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
625 usbotg_fs: usb@50000000 {
626 compatible = "st,stm32f4x9-fsotg";
627 reg = <0x50000000 0x40000>;
629 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;