arch/arm/boot/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "armv7-m.dtsi"
  44 #include <dt-bindings/clock/stm32fx-clock.h>
  45 #include <dt-bindings/mfd/stm32f7-rcc.h>
  46
  47 / {
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         clocks {
  52                 clk_hse: clk-hse {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <0>;
  56                 };
  57
  58                 clk-lse {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <32768>;
  62                 };
  63
  64                 clk-lsi {
  65                         #clock-cells = <0>;
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32000>;
  68                 };
  69
  70                 clk_i2s_ckin: clk-i2s-ckin {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-clock";
  73                         clock-frequency = <48000000>;
  74                 };
  75         };
  76
  77         soc {
  78                 timer2: timer@40000000 {
  79                         compatible = "st,stm32-timer";
  80                         reg = <0x40000000 0x400>;
  81                         interrupts = <28>;
  82                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  83                         status = "disabled";
  84                 };
  85
  86                 timers2: timers@40000000 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         compatible = "st,stm32-timers";
  90                         reg = <0x40000000 0x400>;
  91                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  92                         clock-names = "int";
  93                         status = "disabled";
  94
  95                         pwm {
  96                                 compatible = "st,stm32-pwm";
  97                                 #pwm-cells = <3>;
  98                                 status = "disabled";
  99                         };
 100
 101                         timer@1 {
 102                                 compatible = "st,stm32-timer-trigger";
 103                                 reg = <1>;
 104                                 status = "disabled";
 105                         };
 106                 };
 107
 108                 timer3: timer@40000400 {
 109                         compatible = "st,stm32-timer";
 110                         reg = <0x40000400 0x400>;
 111                         interrupts = <29>;
 112                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 113                         status = "disabled";
 114                 };
 115
 116                 timers3: timers@40000400 {
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                         compatible = "st,stm32-timers";
 120                         reg = <0x40000400 0x400>;
 121                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 122                         clock-names = "int";
 123                         status = "disabled";
 124
 125                         pwm {
 126                                 compatible = "st,stm32-pwm";
 127                                 #pwm-cells = <3>;
 128                                 status = "disabled";
 129                         };
 130
 131                         timer@2 {
 132                                 compatible = "st,stm32-timer-trigger";
 133                                 reg = <2>;
 134                                 status = "disabled";
 135                         };
 136                 };
 137
 138                 timer4: timer@40000800 {
 139                         compatible = "st,stm32-timer";
 140                         reg = <0x40000800 0x400>;
 141                         interrupts = <30>;
 142                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 143                         status = "disabled";
 144                 };
 145
 146                 timers4: timers@40000800 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         compatible = "st,stm32-timers";
 150                         reg = <0x40000800 0x400>;
 151                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 152                         clock-names = "int";
 153                         status = "disabled";
 154
 155                         pwm {
 156                                 compatible = "st,stm32-pwm";
 157                                 #pwm-cells = <3>;
 158                                 status = "disabled";
 159                         };
 160
 161                         timer@3 {
 162                                 compatible = "st,stm32-timer-trigger";
 163                                 reg = <3>;
 164                                 status = "disabled";
 165                         };
 166                 };
 167
 168                 timer5: timer@40000c00 {
 169                         compatible = "st,stm32-timer";
 170                         reg = <0x40000c00 0x400>;
 171                         interrupts = <50>;
 172                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 173                 };
 174
 175                 timers5: timers@40000c00 {
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         compatible = "st,stm32-timers";
 179                         reg = <0x40000C00 0x400>;
 180                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 181                         clock-names = "int";
 182                         status = "disabled";
 183
 184                         pwm {
 185                                 compatible = "st,stm32-pwm";
 186                                 #pwm-cells = <3>;
 187                                 status = "disabled";
 188                         };
 189
 190                         timer@4 {
 191                                 compatible = "st,stm32-timer-trigger";
 192                                 reg = <4>;
 193                                 status = "disabled";
 194                         };
 195                 };
 196
 197                 timer6: timer@40001000 {
 198                         compatible = "st,stm32-timer";
 199                         reg = <0x40001000 0x400>;
 200                         interrupts = <54>;
 201                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 202                         status = "disabled";
 203                 };
 204
 205                 timers6: timers@40001000 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         compatible = "st,stm32-timers";
 209                         reg = <0x40001000 0x400>;
 210                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 211                         clock-names = "int";
 212                         status = "disabled";
 213
 214                         timer@5 {
 215                                 compatible = "st,stm32-timer-trigger";
 216                                 reg = <5>;
 217                                 status = "disabled";
 218                         };
 219                 };
 220
 221                 timer7: timer@40001400 {
 222                         compatible = "st,stm32-timer";
 223                         reg = <0x40001400 0x400>;
 224                         interrupts = <55>;
 225                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 226                         status = "disabled";
 227                 };
 228
 229                 timers7: timers@40001400 {
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         compatible = "st,stm32-timers";
 233                         reg = <0x40001400 0x400>;
 234                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 235                         clock-names = "int";
 236                         status = "disabled";
 237
 238                         timer@6 {
 239                                 compatible = "st,stm32-timer-trigger";
 240                                 reg = <6>;
 241                                 status = "disabled";
 242                         };
 243                 };
 244
 245                 timers12: timers@40001800 {
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         compatible = "st,stm32-timers";
 249                         reg = <0x40001800 0x400>;
 250                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 251                         clock-names = "int";
 252                         status = "disabled";
 253
 254                         pwm {
 255                                 compatible = "st,stm32-pwm";
 256                                 #pwm-cells = <3>;
 257                                 status = "disabled";
 258                         };
 259
 260                         timer@11 {
 261                                 compatible = "st,stm32-timer-trigger";
 262                                 reg = <11>;
 263                                 status = "disabled";
 264                         };
 265                 };
 266
 267                 timers13: timers@40001c00 {
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         compatible = "st,stm32-timers";
 271                         reg = <0x40001C00 0x400>;
 272                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 273                         clock-names = "int";
 274                         status = "disabled";
 275
 276                         pwm {
 277                                 compatible = "st,stm32-pwm";
 278                                 #pwm-cells = <3>;
 279                                 status = "disabled";
 280                         };
 281                 };
 282
 283                 timers14: timers@40002000 {
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         compatible = "st,stm32-timers";
 287                         reg = <0x40002000 0x400>;
 288                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 289                         clock-names = "int";
 290                         status = "disabled";
 291
 292                         pwm {
 293                                 compatible = "st,stm32-pwm";
 294                                 #pwm-cells = <3>;
 295                                 status = "disabled";
 296                         };
 297                 };
 298
 299                 rtc: rtc@40002800 {
 300                         compatible = "st,stm32-rtc";
 301                         reg = <0x40002800 0x400>;
 302                         clocks = <&rcc 1 CLK_RTC>;
 303                         assigned-clocks = <&rcc 1 CLK_RTC>;
 304                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 305                         interrupt-parent = <&exti>;
 306                         interrupts = <17 1>;
 307                         interrupt-names = "alarm";
 308                         st,syscfg = <&pwrcfg 0x00 0x100>;
 309                         status = "disabled";
 310                 };
 311
 312                 usart2: serial@40004400 {
 313                         compatible = "st,stm32f7-uart";
 314                         reg = <0x40004400 0x400>;
 315                         interrupts = <38>;
 316                         clocks = <&rcc 1 CLK_USART2>;
 317                         status = "disabled";
 318                 };
 319
 320                 usart3: serial@40004800 {
 321                         compatible = "st,stm32f7-uart";
 322                         reg = <0x40004800 0x400>;
 323                         interrupts = <39>;
 324                         clocks = <&rcc 1 CLK_USART3>;
 325                         status = "disabled";
 326                 };
 327
 328                 usart4: serial@40004c00 {
 329                         compatible = "st,stm32f7-uart";
 330                         reg = <0x40004c00 0x400>;
 331                         interrupts = <52>;
 332                         clocks = <&rcc 1 CLK_UART4>;
 333                         status = "disabled";
 334                 };
 335
 336                 usart5: serial@40005000 {
 337                         compatible = "st,stm32f7-uart";
 338                         reg = <0x40005000 0x400>;
 339                         interrupts = <53>;
 340                         clocks = <&rcc 1 CLK_UART5>;
 341                         status = "disabled";
 342                 };
 343
 344                 i2c1: i2c@40005400 {
 345                         compatible = "st,stm32f7-i2c";
 346                         reg = <0x40005400 0x400>;
 347                         interrupts = <31>,
 348                                      <32>;
 349                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 350                         clocks = <&rcc 1 CLK_I2C1>;
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         status = "disabled";
 354                 };
 355
 356                 i2c2: i2c@40005800 {
 357                         compatible = "st,stm32f7-i2c";
 358                         reg = <0x40005800 0x400>;
 359                         interrupts = <33>,
 360                                      <34>;
 361                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 362                         clocks = <&rcc 1 CLK_I2C2>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         status = "disabled";
 366                 };
 367
 368                 i2c3: i2c@40005C00 {
 369                         compatible = "st,stm32f7-i2c";
 370                         reg = <0x40005C00 0x400>;
 371                         interrupts = <72>,
 372                                      <73>;
 373                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 374                         clocks = <&rcc 1 CLK_I2C3>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         status = "disabled";
 378                 };
 379
 380                 i2c4: i2c@40006000 {
 381                         compatible = "st,stm32f7-i2c";
 382                         reg = <0x40006000 0x400>;
 383                         interrupts = <95>,
 384                                      <96>;
 385                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 386                         clocks = <&rcc 1 CLK_I2C4>;
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         status = "disabled";
 390                 };
 391
 392                 cec: cec@40006c00 {
 393                         compatible = "st,stm32-cec";
 394                         reg = <0x40006C00 0x400>;
 395                         interrupts = <94>;
 396                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 397                         clock-names = "cec", "hdmi-cec";
 398                         status = "disabled";
 399                 };
 400
 401                 usart7: serial@40007800 {
 402                         compatible = "st,stm32f7-uart";
 403                         reg = <0x40007800 0x400>;
 404                         interrupts = <82>;
 405                         clocks = <&rcc 1 CLK_UART7>;
 406                         status = "disabled";
 407                 };
 408
 409                 usart8: serial@40007c00 {
 410                         compatible = "st,stm32f7-uart";
 411                         reg = <0x40007c00 0x400>;
 412                         interrupts = <83>;
 413                         clocks = <&rcc 1 CLK_UART8>;
 414                         status = "disabled";
 415                 };
 416
 417                 timers1: timers@40010000 {
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         compatible = "st,stm32-timers";
 421                         reg = <0x40010000 0x400>;
 422                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 423                         clock-names = "int";
 424                         status = "disabled";
 425
 426                         pwm {
 427                                 compatible = "st,stm32-pwm";
 428                                 #pwm-cells = <3>;
 429                                 status = "disabled";
 430                         };
 431
 432                         timer@0 {
 433                                 compatible = "st,stm32-timer-trigger";
 434                                 reg = <0>;
 435                                 status = "disabled";
 436                         };
 437                 };
 438
 439                 timers8: timers@40010400 {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         compatible = "st,stm32-timers";
 443                         reg = <0x40010400 0x400>;
 444                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 445                         clock-names = "int";
 446                         status = "disabled";
 447
 448                         pwm {
 449                                 compatible = "st,stm32-pwm";
 450                                 #pwm-cells = <3>;
 451                                 status = "disabled";
 452                         };
 453
 454                         timer@7 {
 455                                 compatible = "st,stm32-timer-trigger";
 456                                 reg = <7>;
 457                                 status = "disabled";
 458                         };
 459                 };
 460
 461                 usart1: serial@40011000 {
 462                         compatible = "st,stm32f7-uart";
 463                         reg = <0x40011000 0x400>;
 464                         interrupts = <37>;
 465                         clocks = <&rcc 1 CLK_USART1>;
 466                         status = "disabled";
 467                 };
 468
 469                 usart6: serial@40011400 {
 470                         compatible = "st,stm32f7-uart";
 471                         reg = <0x40011400 0x400>;
 472                         interrupts = <71>;
 473                         clocks = <&rcc 1 CLK_USART6>;
 474                         status = "disabled";
 475                 };
 476
 477                 sdio2: sdio2@40011c00 {
 478                         compatible = "arm,pl180", "arm,primecell";
 479                         arm,primecell-periphid = <0x00880180>;
 480                         reg = <0x40011c00 0x400>;
 481                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 482                         clock-names = "apb_pclk";
 483                         interrupts = <103>;
 484                         max-frequency = <48000000>;
 485                         status = "disabled";
 486                 };
 487
 488                 sdio1: sdio1@40012c00 {
 489                         compatible = "arm,pl180", "arm,primecell";
 490                         arm,primecell-periphid = <0x00880180>;
 491                         reg = <0x40012c00 0x400>;
 492                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 493                         clock-names = "apb_pclk";
 494                         interrupts = <49>;
 495                         max-frequency = <48000000>;
 496                         status = "disabled";
 497                 };
 498
 499                 syscfg: system-config@40013800 {
 500                         compatible = "syscon";
 501                         reg = <0x40013800 0x400>;
 502                 };
 503
 504                 exti: interrupt-controller@40013c00 {
 505                         compatible = "st,stm32-exti";
 506                         interrupt-controller;
 507                         #interrupt-cells = <2>;
 508                         reg = <0x40013C00 0x400>;
 509                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 510                 };
 511
 512                 timers9: timers@40014000 {
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         compatible = "st,stm32-timers";
 516                         reg = <0x40014000 0x400>;
 517                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 518                         clock-names = "int";
 519                         status = "disabled";
 520
 521                         pwm {
 522                                 compatible = "st,stm32-pwm";
 523                                 #pwm-cells = <3>;
 524                                 status = "disabled";
 525                         };
 526
 527                         timer@8 {
 528                                 compatible = "st,stm32-timer-trigger";
 529                                 reg = <8>;
 530                                 status = "disabled";
 531                         };
 532                 };
 533
 534                 timers10: timers@40014400 {
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         compatible = "st,stm32-timers";
 538                         reg = <0x40014400 0x400>;
 539                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 540                         clock-names = "int";
 541                         status = "disabled";
 542
 543                         pwm {
 544                                 compatible = "st,stm32-pwm";
 545                                 #pwm-cells = <3>;
 546                                 status = "disabled";
 547                         };
 548                 };
 549
 550                 timers11: timers@40014800 {
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                         compatible = "st,stm32-timers";
 554                         reg = <0x40014800 0x400>;
 555                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 556                         clock-names = "int";
 557                         status = "disabled";
 558
 559                         pwm {
 560                                 compatible = "st,stm32-pwm";
 561                                 #pwm-cells = <3>;
 562                                 status = "disabled";
 563                         };
 564                 };
 565
 566                 pwrcfg: power-config@40007000 {
 567                         compatible = "syscon";
 568                         reg = <0x40007000 0x400>;
 569                 };
 570
 571                 crc: crc@40023000 {
 572                         compatible = "st,stm32f7-crc";
 573                         reg = <0x40023000 0x400>;
 574                         clocks = <&rcc 0 12>;
 575                         status = "disabled";
 576                 };
 577
 578                 rcc: rcc@40023800 {
 579                         #reset-cells = <1>;
 580                         #clock-cells = <2>;
 581                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 582                         reg = <0x40023800 0x400>;
 583                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 584                         st,syscfg = <&pwrcfg>;
 585                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 586                         assigned-clock-rates = <1000000>;
 587                 };
 588
 589                 dma1: dma-controller@40026000 {
 590                         compatible = "st,stm32-dma";
 591                         reg = <0x40026000 0x400>;
 592                         interrupts = <11>,
 593                                      <12>,
 594                                      <13>,
 595                                      <14>,
 596                                      <15>,
 597                                      <16>,
 598                                      <17>,
 599                                      <47>;
 600                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 601                         #dma-cells = <4>;
 602                         status = "disabled";
 603                 };
 604
 605                 dma2: dma-controller@40026400 {
 606                         compatible = "st,stm32-dma";
 607                         reg = <0x40026400 0x400>;
 608                         interrupts = <56>,
 609                                      <57>,
 610                                      <58>,
 611                                      <59>,
 612                                      <60>,
 613                                      <68>,
 614                                      <69>,
 615                                      <70>;
 616                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 617                         #dma-cells = <4>;
 618                         st,mem2mem;
 619                         status = "disabled";
 620                 };
 621
 622                 usbotg_hs: usb@40040000 {
 623                         compatible = "st,stm32f7-hsotg";
 624                         reg = <0x40040000 0x40000>;
 625                         interrupts = <77>;
 626                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 627                         clock-names = "otg";
 628                         g-rx-fifo-size = <256>;
 629                         g-np-tx-fifo-size = <32>;
 630                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 631                         status = "disabled";
 632                 };
 633
 634                 usbotg_fs: usb@50000000 {
 635                         compatible = "st,stm32f4x9-fsotg";
 636                         reg = <0x50000000 0x40000>;
 637                         interrupts = <67>;
 638                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 639                         clock-names = "otg";
 640                         status = "disabled";
 641                 };
 642         };
 643 };
 644
 645 &systick {
 646         clocks = <&rcc 1 0>;
 647         status = "okay";
 648 };