2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
83 romem: efuse@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
96 timer2: timer@40000000 {
97 compatible = "st,stm32-timer";
98 reg = <0x40000000 0x400>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
104 timers2: timers@40000000 {
105 #address-cells = <1>;
107 compatible = "st,stm32-timers";
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
114 compatible = "st,stm32-pwm";
120 compatible = "st,stm32-timer-trigger";
126 timer3: timer@40000400 {
127 compatible = "st,stm32-timer";
128 reg = <0x40000400 0x400>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
134 timers3: timers@40000400 {
135 #address-cells = <1>;
137 compatible = "st,stm32-timers";
138 reg = <0x40000400 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
144 compatible = "st,stm32-pwm";
150 compatible = "st,stm32-timer-trigger";
156 timer4: timer@40000800 {
157 compatible = "st,stm32-timer";
158 reg = <0x40000800 0x400>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
164 timers4: timers@40000800 {
165 #address-cells = <1>;
167 compatible = "st,stm32-timers";
168 reg = <0x40000800 0x400>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
174 compatible = "st,stm32-pwm";
180 compatible = "st,stm32-timer-trigger";
186 timer5: timer@40000c00 {
187 compatible = "st,stm32-timer";
188 reg = <0x40000c00 0x400>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
193 timers5: timers@40000c00 {
194 #address-cells = <1>;
196 compatible = "st,stm32-timers";
197 reg = <0x40000C00 0x400>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
203 compatible = "st,stm32-pwm";
209 compatible = "st,stm32-timer-trigger";
215 timer6: timer@40001000 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001000 0x400>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
223 timers6: timers@40001000 {
224 #address-cells = <1>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001000 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
233 compatible = "st,stm32-timer-trigger";
239 timer7: timer@40001400 {
240 compatible = "st,stm32-timer";
241 reg = <0x40001400 0x400>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
247 timers7: timers@40001400 {
248 #address-cells = <1>;
250 compatible = "st,stm32-timers";
251 reg = <0x40001400 0x400>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
257 compatible = "st,stm32-timer-trigger";
263 timers12: timers@40001800 {
264 #address-cells = <1>;
266 compatible = "st,stm32-timers";
267 reg = <0x40001800 0x400>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
273 compatible = "st,stm32-pwm";
279 compatible = "st,stm32-timer-trigger";
285 timers13: timers@40001c00 {
286 #address-cells = <1>;
288 compatible = "st,stm32-timers";
289 reg = <0x40001C00 0x400>;
290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
295 compatible = "st,stm32-pwm";
301 timers14: timers@40002000 {
302 #address-cells = <1>;
304 compatible = "st,stm32-timers";
305 reg = <0x40002000 0x400>;
306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
311 compatible = "st,stm32-pwm";
318 compatible = "st,stm32-rtc";
319 reg = <0x40002800 0x400>;
320 clocks = <&rcc 1 CLK_RTC>;
321 assigned-clocks = <&rcc 1 CLK_RTC>;
322 assigned-clock-parents = <&rcc 1 CLK_LSE>;
323 interrupt-parent = <&exti>;
325 interrupt-names = "alarm";
326 st,syscfg = <&pwrcfg 0x00 0x100>;
330 iwdg: watchdog@40003000 {
331 compatible = "st,stm32-iwdg";
332 reg = <0x40003000 0x400>;
339 #address-cells = <1>;
341 compatible = "st,stm32f4-spi";
342 reg = <0x40003800 0x400>;
344 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
349 #address-cells = <1>;
351 compatible = "st,stm32f4-spi";
352 reg = <0x40003c00 0x400>;
354 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
358 usart2: serial@40004400 {
359 compatible = "st,stm32-uart";
360 reg = <0x40004400 0x400>;
362 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
366 usart3: serial@40004800 {
367 compatible = "st,stm32-uart";
368 reg = <0x40004800 0x400>;
370 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
372 dmas = <&dma1 1 4 0x400 0x0>,
373 <&dma1 3 4 0x400 0x0>;
374 dma-names = "rx", "tx";
377 usart4: serial@40004c00 {
378 compatible = "st,stm32-uart";
379 reg = <0x40004c00 0x400>;
381 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
385 usart5: serial@40005000 {
386 compatible = "st,stm32-uart";
387 reg = <0x40005000 0x400>;
389 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
394 compatible = "st,stm32f4-i2c";
395 reg = <0x40005400 0x400>;
398 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
399 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
400 #address-cells = <1>;
406 compatible = "st,stm32f4-dac-core";
407 reg = <0x40007400 0x400>;
408 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
409 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
410 clock-names = "pclk";
411 #address-cells = <1>;
416 compatible = "st,stm32-dac";
417 #io-channel-cells = <1>;
423 compatible = "st,stm32-dac";
424 #io-channel-cells = <1>;
430 usart7: serial@40007800 {
431 compatible = "st,stm32-uart";
432 reg = <0x40007800 0x400>;
434 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
438 usart8: serial@40007c00 {
439 compatible = "st,stm32-uart";
440 reg = <0x40007c00 0x400>;
442 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
446 timers1: timers@40010000 {
447 #address-cells = <1>;
449 compatible = "st,stm32-timers";
450 reg = <0x40010000 0x400>;
451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
456 compatible = "st,stm32-pwm";
462 compatible = "st,stm32-timer-trigger";
468 timers8: timers@40010400 {
469 #address-cells = <1>;
471 compatible = "st,stm32-timers";
472 reg = <0x40010400 0x400>;
473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
478 compatible = "st,stm32-pwm";
484 compatible = "st,stm32-timer-trigger";
490 usart1: serial@40011000 {
491 compatible = "st,stm32-uart";
492 reg = <0x40011000 0x400>;
494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
496 dmas = <&dma2 2 4 0x400 0x0>,
497 <&dma2 7 4 0x400 0x0>;
498 dma-names = "rx", "tx";
501 usart6: serial@40011400 {
502 compatible = "st,stm32-uart";
503 reg = <0x40011400 0x400>;
505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
510 compatible = "st,stm32f4-adc-core";
511 reg = <0x40012000 0x400>;
513 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
515 interrupt-controller;
516 #interrupt-cells = <1>;
517 #address-cells = <1>;
522 compatible = "st,stm32f4-adc";
523 #io-channel-cells = <1>;
525 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
526 interrupt-parent = <&adc>;
528 dmas = <&dma2 0 0 0x400 0x0>;
534 compatible = "st,stm32f4-adc";
535 #io-channel-cells = <1>;
537 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
538 interrupt-parent = <&adc>;
540 dmas = <&dma2 3 1 0x400 0x0>;
546 compatible = "st,stm32f4-adc";
547 #io-channel-cells = <1>;
549 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
550 interrupt-parent = <&adc>;
552 dmas = <&dma2 1 2 0x400 0x0>;
558 sdio: sdio@40012c00 {
559 compatible = "arm,pl180", "arm,primecell";
560 arm,primecell-periphid = <0x00880180>;
561 reg = <0x40012c00 0x400>;
562 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
563 clock-names = "apb_pclk";
565 max-frequency = <48000000>;
570 #address-cells = <1>;
572 compatible = "st,stm32f4-spi";
573 reg = <0x40013000 0x400>;
575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
580 #address-cells = <1>;
582 compatible = "st,stm32f4-spi";
583 reg = <0x40013400 0x400>;
585 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
589 syscfg: system-config@40013800 {
590 compatible = "syscon";
591 reg = <0x40013800 0x400>;
594 exti: interrupt-controller@40013c00 {
595 compatible = "st,stm32-exti";
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 reg = <0x40013C00 0x400>;
599 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
602 timers9: timers@40014000 {
603 #address-cells = <1>;
605 compatible = "st,stm32-timers";
606 reg = <0x40014000 0x400>;
607 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
612 compatible = "st,stm32-pwm";
618 compatible = "st,stm32-timer-trigger";
624 timers10: timers@40014400 {
625 #address-cells = <1>;
627 compatible = "st,stm32-timers";
628 reg = <0x40014400 0x400>;
629 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
634 compatible = "st,stm32-pwm";
640 timers11: timers@40014800 {
641 #address-cells = <1>;
643 compatible = "st,stm32-timers";
644 reg = <0x40014800 0x400>;
645 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
650 compatible = "st,stm32-pwm";
657 #address-cells = <1>;
659 compatible = "st,stm32f4-spi";
660 reg = <0x40015000 0x400>;
662 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
663 dmas = <&dma2 3 2 0x400 0x0>,
664 <&dma2 4 2 0x400 0x0>;
665 dma-names = "rx", "tx";
670 #address-cells = <1>;
672 compatible = "st,stm32f4-spi";
673 reg = <0x40015400 0x400>;
675 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
679 pwrcfg: power-config@40007000 {
680 compatible = "syscon";
681 reg = <0x40007000 0x400>;
684 ltdc: display-controller@40016800 {
685 compatible = "st,stm32-ltdc";
686 reg = <0x40016800 0x200>;
687 interrupts = <88>, <89>;
688 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
689 clocks = <&rcc 1 CLK_LCD>;
695 compatible = "st,stm32f4-crc";
696 reg = <0x40023000 0x400>;
697 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
704 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
705 reg = <0x40023800 0x400>;
706 clocks = <&clk_hse>, <&clk_i2s_ckin>;
707 st,syscfg = <&pwrcfg>;
708 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
709 assigned-clock-rates = <1000000>;
712 dma1: dma-controller@40026000 {
713 compatible = "st,stm32-dma";
714 reg = <0x40026000 0x400>;
723 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
727 dma2: dma-controller@40026400 {
728 compatible = "st,stm32-dma";
729 reg = <0x40026400 0x400>;
738 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
743 mac: ethernet@40028000 {
744 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
745 reg = <0x40028000 0x8000>;
746 reg-names = "stmmaceth";
748 interrupt-names = "macirq";
749 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
750 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
751 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
752 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
753 st,syscon = <&syscfg 0x4>;
759 usbotg_hs: usb@40040000 {
760 compatible = "snps,dwc2";
761 reg = <0x40040000 0x40000>;
763 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
768 usbotg_fs: usb@50000000 {
769 compatible = "st,stm32f4x9-fsotg";
770 reg = <0x50000000 0x40000>;
772 clocks = <&rcc 0 39>;
777 dcmi: dcmi@50050000 {
778 compatible = "st,stm32-dcmi";
779 reg = <0x50050000 0x400>;
781 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
782 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
783 clock-names = "mclk";
784 pinctrl-names = "default";
785 pinctrl-0 = <&dcmi_pins>;
786 dmas = <&dma2 1 1 0x414 0x3>;
792 compatible = "st,stm32-rng";
793 reg = <0x50060800 0x400>;
794 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
801 clocks = <&rcc 1 SYSTICK>;