1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 STMicroelectronics R&D Limited
5 #include <dt-bindings/clock/stih410-clks.h>
8 * Fixed 30MHz oscillator inputs to SoC
10 clk_sysin: clk-sysin {
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
28 compatible = "st,stih410-clk", "simple-bus";
34 compatible = "st,clkgen-c32";
35 reg = <0x92b0000 0x10000>;
37 clockgen_a9_pll: clockgen-a9-pll {
39 compatible = "st,stih407-clkgen-plla9";
41 clocks = <&clk_sysin>;
45 * ARM CPU related clocks.
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
51 clocks = <&clockgen_a9_pll 0>,
53 <&clk_s_c0_flexgen 13>,
54 <&clk_m_a9_ext2f_div2>;
57 * ARM Peripheral clock for timers
59 arm_periph_clk: clk-m-a9-periphs {
61 compatible = "fixed-factor-clock";
70 compatible = "st,clkgen-c32";
71 reg = <0x90ff000 0x1000>;
73 clk_s_a0_pll: clk-s-a0-pll {
75 compatible = "st,clkgen-pll0-a0";
77 clocks = <&clk_sysin>;
80 clk_s_a0_flexgen: clk-s-a0-flexgen {
81 compatible = "st,flexgen", "st,flexgen-stih410-a0";
85 clocks = <&clk_s_a0_pll 0>,
90 clk_s_c0: clockgen-c@9103000 {
91 compatible = "st,clkgen-c32";
92 reg = <0x9103000 0x1000>;
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
98 clocks = <&clk_sysin>;
101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
105 clocks = <&clk_sysin>;
108 clk_s_c0_quadfs: clk-s-c0-quadfs {
110 compatible = "st,quadfs-pll";
112 clocks = <&clk_sysin>;
115 clk_s_c0_flexgen: clk-s-c0-flexgen {
117 compatible = "st,flexgen", "st,flexgen-stih410-c0";
119 clocks = <&clk_s_c0_pll0 0>,
121 <&clk_s_c0_quadfs 0>,
122 <&clk_s_c0_quadfs 1>,
123 <&clk_s_c0_quadfs 2>,
124 <&clk_s_c0_quadfs 3>,
128 * ARM Peripheral clock for timers
130 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
132 compatible = "fixed-factor-clock";
134 clocks = <&clk_s_c0_flexgen 13>;
136 clock-output-names = "clk-m-a9-ext2f-div2";
144 clockgen-d0@9104000 {
145 compatible = "st,clkgen-c32";
146 reg = <0x9104000 0x1000>;
148 clk_s_d0_quadfs: clk-s-d0-quadfs {
150 compatible = "st,quadfs-d0";
152 clocks = <&clk_sysin>;
155 clk_s_d0_flexgen: clk-s-d0-flexgen {
157 compatible = "st,flexgen", "st,flexgen-stih410-d0";
159 clocks = <&clk_s_d0_quadfs 0>,
160 <&clk_s_d0_quadfs 1>,
161 <&clk_s_d0_quadfs 2>,
162 <&clk_s_d0_quadfs 3>,
167 clockgen-d2@9106000 {
168 compatible = "st,clkgen-c32";
169 reg = <0x9106000 0x1000>;
171 clk_s_d2_quadfs: clk-s-d2-quadfs {
173 compatible = "st,quadfs-d2";
175 clocks = <&clk_sysin>;
178 clk_s_d2_flexgen: clk-s-d2-flexgen {
180 compatible = "st,flexgen", "st,flexgen-stih407-d2";
182 clocks = <&clk_s_d2_quadfs 0>,
183 <&clk_s_d2_quadfs 1>,
184 <&clk_s_d2_quadfs 2>,
185 <&clk_s_d2_quadfs 3>,
192 clockgen-d3@9107000 {
193 compatible = "st,clkgen-c32";
194 reg = <0x9107000 0x1000>;
196 clk_s_d3_quadfs: clk-s-d3-quadfs {
198 compatible = "st,quadfs-d3";
200 clocks = <&clk_sysin>;
203 clk_s_d3_flexgen: clk-s-d3-flexgen {
205 compatible = "st,flexgen", "st,flexgen-stih407-d3";
207 clocks = <&clk_s_d3_quadfs 0>,
208 <&clk_s_d3_quadfs 1>,
209 <&clk_s_d3_quadfs 2>,
210 <&clk_s_d3_quadfs 3>,