1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 STMicroelectronics R&D Limited
5 #include <dt-bindings/clock/stih407-clks.h>
8 * Fixed 30MHz oscillator inputs to SoC
10 clk_sysin: clk-sysin {
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
31 compatible = "st,clkgen-c32";
32 reg = <0x92b0000 0xffff>;
34 clockgen_a9_pll: clockgen-a9-pll {
36 compatible = "st,stih407-clkgen-plla9";
38 clocks = <&clk_sysin>;
40 clock-output-names = "clockgen-a9-pll-odf";
45 * ARM CPU related clocks.
47 clk_m_a9: clk-m-a9@92b0000 {
49 compatible = "st,stih407-clkgen-a9-mux";
50 reg = <0x92b0000 0x10000>;
52 clocks = <&clockgen_a9_pll 0>,
54 <&clk_s_c0_flexgen 13>,
55 <&clk_m_a9_ext2f_div2>;
59 * ARM Peripheral clock for timers
61 arm_periph_clk: clk-m-a9-periphs {
63 compatible = "fixed-factor-clock";
72 compatible = "st,clkgen-c32";
73 reg = <0x90ff000 0x1000>;
75 clk_s_a0_pll: clk-s-a0-pll {
77 compatible = "st,clkgen-pll0";
79 clocks = <&clk_sysin>;
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
86 compatible = "st,flexgen";
90 clocks = <&clk_s_a0_pll 0>,
93 clock-output-names = "clk-ic-lmi0";
94 clock-critical = <CLK_IC_LMI0>;
98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
100 compatible = "st,quadfs-pll";
101 reg = <0x9103000 0x1000>;
103 clocks = <&clk_sysin>;
105 clock-output-names = "clk-s-c0-fs0-ch0",
109 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
112 clk_s_c0: clockgen-c@9103000 {
113 compatible = "st,clkgen-c32";
114 reg = <0x9103000 0x1000>;
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
120 clocks = <&clk_sysin>;
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
126 clk_s_c0_pll1: clk-s-c0-pll1 {
128 compatible = "st,clkgen-pll1";
130 clocks = <&clk_sysin>;
132 clock-output-names = "clk-s-c0-pll1-odf-0";
135 clk_s_c0_flexgen: clk-s-c0-flexgen {
137 compatible = "st,flexgen";
139 clocks = <&clk_s_c0_pll0 0>,
141 <&clk_s_c0_quadfs 0>,
142 <&clk_s_c0_quadfs 1>,
143 <&clk_s_c0_quadfs 2>,
144 <&clk_s_c0_quadfs 3>,
147 clock-output-names = "clk-icn-gpu",
174 "clk-eth-ref-phyclk",
179 clock-critical = <CLK_PROC_STFE>,
187 * ARM Peripheral clock for timers
189 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
191 compatible = "fixed-factor-clock";
193 clocks = <&clk_s_c0_flexgen 13>;
195 clock-output-names = "clk-m-a9-ext2f-div2";
203 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
205 compatible = "st,quadfs";
206 reg = <0x9104000 0x1000>;
208 clocks = <&clk_sysin>;
210 clock-output-names = "clk-s-d0-fs0-ch0",
216 clockgen-d0@9104000 {
217 compatible = "st,clkgen-c32";
218 reg = <0x9104000 0x1000>;
220 clk_s_d0_flexgen: clk-s-d0-flexgen {
222 compatible = "st,flexgen-audio", "st,flexgen";
224 clocks = <&clk_s_d0_quadfs 0>,
225 <&clk_s_d0_quadfs 1>,
226 <&clk_s_d0_quadfs 2>,
227 <&clk_s_d0_quadfs 3>,
230 clock-output-names = "clk-pcm-0",
237 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
239 compatible = "st,quadfs";
240 reg = <0x9106000 0x1000>;
242 clocks = <&clk_sysin>;
244 clock-output-names = "clk-s-d2-fs0-ch0",
250 clockgen-d2@9106000 {
251 compatible = "st,clkgen-c32";
252 reg = <0x9106000 0x1000>;
254 clk_s_d2_flexgen: clk-s-d2-flexgen {
256 compatible = "st,flexgen-video", "st,flexgen";
258 clocks = <&clk_s_d2_quadfs 0>,
259 <&clk_s_d2_quadfs 1>,
260 <&clk_s_d2_quadfs 2>,
261 <&clk_s_d2_quadfs 3>,
266 clock-output-names = "clk-pix-main-disp",
285 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
287 compatible = "st,quadfs";
288 reg = <0x9107000 0x1000>;
290 clocks = <&clk_sysin>;
292 clock-output-names = "clk-s-d3-fs0-ch0",
298 clockgen-d3@9107000 {
299 compatible = "st,clkgen-c32";
300 reg = <0x9107000 0x1000>;
302 clk_s_d3_flexgen: clk-s-d3-flexgen {
304 compatible = "st,flexgen";
306 clocks = <&clk_s_d3_quadfs 0>,
307 <&clk_s_d3_quadfs 1>,
308 <&clk_s_d3_quadfs 2>,
309 <&clk_s_d3_quadfs 3>,
312 clock-output-names = "clk-stfe-frc1",