1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Linaro Ltd
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/mfd/dbx500-prcmu.h>
9 #include <dt-bindings/arm/ux500_pm_domains.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/ste-ab8500.h>
23 enable-method = "ste,dbx500-smp";
37 compatible = "arm,cortex-a9";
39 /* cpufreq controls */
40 operating-points = <998400 0
44 clocks = <&prcmu_clk PRCMU_ARMSS>;
46 clock-latency = <20000>;
50 compatible = "arm,cortex-a9";
58 compatible = "stericsson,db8500";
59 interrupt-parent = <&intc>;
63 compatible = "arm,coresight-etm3x", "arm,primecell";
64 reg = <0x801ae000 0x1000>;
66 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
67 clock-names = "apb_pclk", "atclk";
71 ptm0_out_port: endpoint {
72 remote-endpoint = <&funnel_in_port0>;
79 compatible = "arm,coresight-etm3x", "arm,primecell";
80 reg = <0x801af000 0x1000>;
82 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
83 clock-names = "apb_pclk", "atclk";
87 ptm1_out_port: endpoint {
88 remote-endpoint = <&funnel_in_port1>;
95 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
96 reg = <0x801a6000 0x1000>;
98 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
99 clock-names = "apb_pclk", "atclk";
102 funnel_out_port: endpoint {
104 <&replicator_in_port0>;
110 #address-cells = <1>;
115 funnel_in_port0: endpoint {
116 remote-endpoint = <&ptm0_out_port>;
122 funnel_in_port1: endpoint {
123 remote-endpoint = <&ptm1_out_port>;
130 compatible = "arm,coresight-static-replicator";
131 clocks = <&prcmu_clk PRCMU_APEATCLK>;
132 clock-names = "atclk";
135 #address-cells = <1>;
140 replicator_out_port0: endpoint {
141 remote-endpoint = <&tpiu_in_port>;
146 replicator_out_port1: endpoint {
147 remote-endpoint = <&etb_in_port>;
154 replicator_in_port0: endpoint {
155 remote-endpoint = <&funnel_out_port>;
162 compatible = "arm,coresight-tpiu", "arm,primecell";
163 reg = <0x80190000 0x1000>;
165 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
166 clock-names = "apb_pclk", "atclk";
169 tpiu_in_port: endpoint {
170 remote-endpoint = <&replicator_out_port0>;
177 compatible = "arm,coresight-etb10", "arm,primecell";
178 reg = <0x801a4000 0x1000>;
180 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
181 clock-names = "apb_pclk", "atclk";
184 etb_in_port: endpoint {
185 remote-endpoint = <&replicator_out_port1>;
191 intc: interrupt-controller@a0411000 {
192 compatible = "arm,cortex-a9-gic";
193 #interrupt-cells = <3>;
194 #address-cells = <1>;
195 interrupt-controller;
196 reg = <0xa0411000 0x1000>,
201 compatible = "arm,cortex-a9-scu";
202 reg = <0xa0410000 0x100>;
206 * The backup RAM is used for retention during sleep
207 * and various things like spin tables
210 compatible = "ste,dbx500-backupram";
211 reg = <0x80150000 0x2000>;
215 compatible = "arm,pl310-cache";
216 reg = <0xa0412000 0x1000>;
217 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
223 compatible = "arm,cortex-a9-pmu";
224 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
227 pm_domains: pm_domains0 {
228 compatible = "stericsson,ux500-pm-domains";
229 #power-domain-cells = <1>;
233 compatible = "stericsson,u8500-clks";
235 * Registers for the CLKRST block on peripheral
236 * groups 1, 2, 3, 5, 6,
238 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
239 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
242 prcmu_clk: prcmu-clock {
246 prcc_pclk: prcc-periph-clock {
250 prcc_kclk: prcc-kernel-clock {
254 rtc_clk: rtc32k-clock {
258 smp_twd_clk: smp-twd-clock {
264 /* Nomadik System Timer */
265 compatible = "st,nomadik-mtu";
266 reg = <0xa03c6000 0x1000>;
267 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
270 clock-names = "timclk", "apb_pclk";
274 compatible = "arm,cortex-a9-twd-timer";
275 reg = <0xa0410600 0x20>;
276 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
278 clocks = <&smp_twd_clk>;
282 compatible = "arm,cortex-a9-twd-wdt";
283 reg = <0xa0410620 0x20>;
284 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
285 clocks = <&smp_twd_clk>;
289 compatible = "arm,rtc-pl031", "arm,primecell";
290 reg = <0x80154000 0x1000>;
291 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
294 clock-names = "apb_pclk";
297 gpio0: gpio@8012e000 {
298 compatible = "stericsson,db8500-gpio",
300 reg = <0x8012e000 0x80>;
301 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 st,supports-sleepmode;
308 gpio-ranges = <&pinctrl 0 0 32>;
309 clocks = <&prcc_pclk 1 9>;
312 gpio1: gpio@8012e080 {
313 compatible = "stericsson,db8500-gpio",
315 reg = <0x8012e080 0x80>;
316 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 st,supports-sleepmode;
323 gpio-ranges = <&pinctrl 0 32 5>;
324 clocks = <&prcc_pclk 1 9>;
327 gpio2: gpio@8000e000 {
328 compatible = "stericsson,db8500-gpio",
330 reg = <0x8000e000 0x80>;
331 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 st,supports-sleepmode;
338 gpio-ranges = <&pinctrl 0 64 32>;
339 clocks = <&prcc_pclk 3 8>;
342 gpio3: gpio@8000e080 {
343 compatible = "stericsson,db8500-gpio",
345 reg = <0x8000e080 0x80>;
346 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 st,supports-sleepmode;
353 gpio-ranges = <&pinctrl 0 96 2>;
354 clocks = <&prcc_pclk 3 8>;
357 gpio4: gpio@8000e100 {
358 compatible = "stericsson,db8500-gpio",
360 reg = <0x8000e100 0x80>;
361 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 st,supports-sleepmode;
368 gpio-ranges = <&pinctrl 0 128 32>;
369 clocks = <&prcc_pclk 3 8>;
372 gpio5: gpio@8000e180 {
373 compatible = "stericsson,db8500-gpio",
375 reg = <0x8000e180 0x80>;
376 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 st,supports-sleepmode;
383 gpio-ranges = <&pinctrl 0 160 12>;
384 clocks = <&prcc_pclk 3 8>;
387 gpio6: gpio@8011e000 {
388 compatible = "stericsson,db8500-gpio",
390 reg = <0x8011e000 0x80>;
391 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 st,supports-sleepmode;
398 gpio-ranges = <&pinctrl 0 192 32>;
399 clocks = <&prcc_pclk 2 11>;
402 gpio7: gpio@8011e080 {
403 compatible = "stericsson,db8500-gpio",
405 reg = <0x8011e080 0x80>;
406 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 st,supports-sleepmode;
413 gpio-ranges = <&pinctrl 0 224 7>;
414 clocks = <&prcc_pclk 2 11>;
417 gpio8: gpio@a03fe000 {
418 compatible = "stericsson,db8500-gpio",
420 reg = <0xa03fe000 0x80>;
421 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 st,supports-sleepmode;
428 gpio-ranges = <&pinctrl 0 256 12>;
429 clocks = <&prcc_pclk 5 1>;
433 compatible = "stericsson,db8500-pinctrl";
434 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
435 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
441 compatible = "stericsson,db8500-musb";
442 reg = <0xa03e0000 0x10000>;
443 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "mc";
448 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
449 <&dma 38 0 0x0>, /* Logical - MemToDev */
450 <&dma 37 0 0x2>, /* Logical - DevToMem */
451 <&dma 37 0 0x0>, /* Logical - MemToDev */
452 <&dma 36 0 0x2>, /* Logical - DevToMem */
453 <&dma 36 0 0x0>, /* Logical - MemToDev */
454 <&dma 19 0 0x2>, /* Logical - DevToMem */
455 <&dma 19 0 0x0>, /* Logical - MemToDev */
456 <&dma 18 0 0x2>, /* Logical - DevToMem */
457 <&dma 18 0 0x0>, /* Logical - MemToDev */
458 <&dma 17 0 0x2>, /* Logical - DevToMem */
459 <&dma 17 0 0x0>, /* Logical - MemToDev */
460 <&dma 16 0 0x2>, /* Logical - DevToMem */
461 <&dma 16 0 0x0>, /* Logical - MemToDev */
462 <&dma 39 0 0x2>, /* Logical - DevToMem */
463 <&dma 39 0 0x0>; /* Logical - MemToDev */
465 dma-names = "iep_1_9", "oep_1_9",
466 "iep_2_10", "oep_2_10",
467 "iep_3_11", "oep_3_11",
468 "iep_4_12", "oep_4_12",
469 "iep_5_13", "oep_5_13",
470 "iep_6_14", "oep_6_14",
471 "iep_7_15", "oep_7_15",
474 clocks = <&prcc_pclk 5 0>;
477 dma: dma-controller@801C0000 {
478 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
479 reg = <0x801C0000 0x1000 0x40010000 0x800>;
480 reg-names = "base", "lcpa";
481 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
484 memcpy-channels = <56 57 58 59 60>;
486 clocks = <&prcmu_clk PRCMU_DMACLK>;
489 prcmu: prcmu@80157000 {
490 compatible = "stericsson,db8500-prcmu", "syscon";
491 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
492 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
493 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
500 prcmu-timer-4@80157450 {
501 compatible = "stericsson,db8500-prcmu-timer-4";
502 reg = <0x80157450 0xC>;
506 compatible = "stericsson,db8500-thermal";
507 reg = <0x801573c0 0x40>;
508 interrupt-parent = <&prcmu>;
509 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
510 <22 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
514 trip0-temp = <70000>;
515 trip0-type = "active";
516 trip0-cdev-num = <1>;
517 trip0-cdev-name0 = "thermal-cpufreq-0";
519 trip1-temp = <75000>;
520 trip1-type = "active";
521 trip1-cdev-num = <1>;
522 trip1-cdev-name0 = "thermal-cpufreq-0";
524 trip2-temp = <80000>;
525 trip2-type = "active";
526 trip2-cdev-num = <1>;
527 trip2-cdev-name0 = "thermal-cpufreq-0";
529 trip3-temp = <85000>;
530 trip3-type = "critical";
531 trip3-cdev-num = <0>;
534 db8500-prcmu-regulators {
535 compatible = "stericsson,db8500-prcmu-regulator";
537 // DB8500_REGULATOR_VAPE
538 db8500_vape_reg: db8500_vape {
542 // DB8500_REGULATOR_VARM
543 db8500_varm_reg: db8500_varm {
546 // DB8500_REGULATOR_VMODEM
547 db8500_vmodem_reg: db8500_vmodem {
550 // DB8500_REGULATOR_VPLL
551 db8500_vpll_reg: db8500_vpll {
554 // DB8500_REGULATOR_VSMPS1
555 db8500_vsmps1_reg: db8500_vsmps1 {
558 // DB8500_REGULATOR_VSMPS2
559 db8500_vsmps2_reg: db8500_vsmps2 {
562 // DB8500_REGULATOR_VSMPS3
563 db8500_vsmps3_reg: db8500_vsmps3 {
566 // DB8500_REGULATOR_VRF1
567 db8500_vrf1_reg: db8500_vrf1 {
570 // DB8500_REGULATOR_SWITCH_SVAMMDSP
571 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
574 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
575 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
578 // DB8500_REGULATOR_SWITCH_SVAPIPE
579 db8500_sva_pipe_reg: db8500_sva_pipe {
582 // DB8500_REGULATOR_SWITCH_SIAMMDSP
583 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
586 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
587 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
590 // DB8500_REGULATOR_SWITCH_SIAPIPE
591 db8500_sia_pipe_reg: db8500_sia_pipe {
594 // DB8500_REGULATOR_SWITCH_SGA
595 db8500_sga_reg: db8500_sga {
596 vin-supply = <&db8500_vape_reg>;
599 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
600 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
601 vin-supply = <&db8500_vape_reg>;
604 // DB8500_REGULATOR_SWITCH_ESRAM12
605 db8500_esram12_reg: db8500_esram12 {
608 // DB8500_REGULATOR_SWITCH_ESRAM12RET
609 db8500_esram12_ret_reg: db8500_esram12_ret {
612 // DB8500_REGULATOR_SWITCH_ESRAM34
613 db8500_esram34_reg: db8500_esram34 {
616 // DB8500_REGULATOR_SWITCH_ESRAM34RET
617 db8500_esram34_ret_reg: db8500_esram34_ret {
622 compatible = "stericsson,ab8500";
623 interrupt-parent = <&intc>;
624 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
628 ab8500_clock: clock-controller {
629 compatible = "stericsson,ab8500-clk";
633 ab8500_gpio: ab8500-gpio {
634 compatible = "stericsson,ab8500-gpio";
640 compatible = "stericsson,ab8500-rtc";
641 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
642 18 IRQ_TYPE_LEVEL_HIGH>;
643 interrupt-names = "60S", "ALARM";
647 compatible = "stericsson,ab8500-gpadc";
648 interrupts = <32 IRQ_TYPE_LEVEL_HIGH
649 39 IRQ_TYPE_LEVEL_HIGH>;
650 interrupt-names = "HW_CONV_END", "SW_CONV_END";
651 vddadc-supply = <&ab8500_ldo_tvout_reg>;
654 ab8500_battery: ab8500_battery {
655 stericsson,battery-type = "LIPO";
656 thermistor-on-batctrl;
660 compatible = "stericsson,ab8500-fg";
661 battery = <&ab8500_battery>;
665 compatible = "stericsson,ab8500-btemp";
666 battery = <&ab8500_battery>;
670 compatible = "stericsson,ab8500-charger";
671 battery = <&ab8500_battery>;
672 vddadc-supply = <&ab8500_ldo_tvout_reg>;
676 compatible = "stericsson,ab8500-chargalg";
677 battery = <&ab8500_battery>;
681 compatible = "stericsson,ab8500-usb";
682 interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
683 96 IRQ_TYPE_LEVEL_HIGH
684 14 IRQ_TYPE_LEVEL_HIGH
685 15 IRQ_TYPE_LEVEL_HIGH
686 79 IRQ_TYPE_LEVEL_HIGH
687 74 IRQ_TYPE_LEVEL_HIGH
688 75 IRQ_TYPE_LEVEL_HIGH>;
689 interrupt-names = "ID_WAKEUP_R",
694 "USB_ADP_PROBE_PLUG",
695 "USB_ADP_PROBE_UNPLUG";
696 vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
697 v-ape-supply = <&db8500_vape_reg>;
698 musb_1v8-supply = <&db8500_vsmps2_reg>;
699 clocks = <&prcmu_clk PRCMU_SYSCLK>;
700 clock-names = "sysclk";
704 compatible = "stericsson,ab8500-poweron-key";
705 interrupts = <6 IRQ_TYPE_LEVEL_HIGH
706 7 IRQ_TYPE_LEVEL_HIGH>;
707 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
711 compatible = "stericsson,ab8500-sysctrl";
715 compatible = "stericsson,ab8500-pwm";
716 clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
717 clock-names = "intclk";
721 compatible = "stericsson,ab8500-debug";
724 codec: ab8500-codec {
725 compatible = "stericsson,ab8500-codec";
727 V-AUD-supply = <&ab8500_ldo_audio_reg>;
728 V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
729 V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
730 V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
732 clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
733 clock-names = "audioclk";
735 stericsson,earpeice-cmv = <950>; /* Units in mV. */
738 ext_regulators: ab8500-ext-regulators {
739 compatible = "stericsson,ab8500-ext-regulator";
741 ab8500_ext1_reg: ab8500_ext1 {
742 regulator-min-microvolt = <1800000>;
743 regulator-max-microvolt = <1800000>;
748 ab8500_ext2_reg: ab8500_ext2 {
749 regulator-min-microvolt = <1360000>;
750 regulator-max-microvolt = <1360000>;
755 ab8500_ext3_reg: ab8500_ext3 {
756 regulator-min-microvolt = <3400000>;
757 regulator-max-microvolt = <3400000>;
763 compatible = "stericsson,ab8500-regulator";
764 vin-supply = <&ab8500_ext3_reg>;
766 // supplies to the display/camera
767 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
768 regulator-min-microvolt = <2500000>;
769 regulator-max-microvolt = <2900000>;
771 /* BUG: If turned off MMC will be affected. */
775 // supplies to the on-board eMMC
776 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
777 regulator-min-microvolt = <1100000>;
778 regulator-max-microvolt = <3300000>;
781 // supply for VAUX3; SDcard slots
782 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
783 regulator-min-microvolt = <1100000>;
784 regulator-max-microvolt = <3300000>;
787 // supply for v-intcore12; VINTCORE12 LDO
788 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
791 // supply for tvout; gpadc; TVOUT LDO
792 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
795 // supply for ab8500-usb; USB LDO
796 ab8500_ldo_usb_reg: ab8500_ldo_usb {
799 // supply for ab8500-vaudio; VAUDIO LDO
800 ab8500_ldo_audio_reg: ab8500_ldo_audio {
803 // supply for v-anamic1 VAMIC1 LDO
804 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
807 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
808 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
811 // supply for v-dmic; VDMIC LDO
812 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
815 // supply for U8500 CSI/DSI; VANA LDO
816 ab8500_ldo_ana_reg: ab8500_ldo_ana {
823 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
824 reg = <0x80004000 0x1000>;
825 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
827 #address-cells = <1>;
829 v-i2c-supply = <&db8500_vape_reg>;
831 clock-frequency = <400000>;
832 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
833 clock-names = "i2cclk", "apb_pclk";
834 power-domains = <&pm_domains DOMAIN_VAPE>;
838 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
839 reg = <0x80122000 0x1000>;
840 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
842 #address-cells = <1>;
844 v-i2c-supply = <&db8500_vape_reg>;
846 clock-frequency = <400000>;
848 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
849 clock-names = "i2cclk", "apb_pclk";
850 power-domains = <&pm_domains DOMAIN_VAPE>;
854 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
855 reg = <0x80128000 0x1000>;
856 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
858 #address-cells = <1>;
860 v-i2c-supply = <&db8500_vape_reg>;
862 clock-frequency = <400000>;
864 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
865 clock-names = "i2cclk", "apb_pclk";
866 power-domains = <&pm_domains DOMAIN_VAPE>;
870 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
871 reg = <0x80110000 0x1000>;
872 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
874 #address-cells = <1>;
876 v-i2c-supply = <&db8500_vape_reg>;
878 clock-frequency = <400000>;
880 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
881 clock-names = "i2cclk", "apb_pclk";
882 power-domains = <&pm_domains DOMAIN_VAPE>;
886 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
887 reg = <0x8012a000 0x1000>;
888 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
890 #address-cells = <1>;
892 v-i2c-supply = <&db8500_vape_reg>;
894 clock-frequency = <400000>;
896 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
897 clock-names = "i2cclk", "apb_pclk";
898 power-domains = <&pm_domains DOMAIN_VAPE>;
902 compatible = "arm,pl022", "arm,primecell";
903 reg = <0x80002000 0x1000>;
904 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
905 #address-cells = <1>;
907 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
908 clock-names = "SSPCLK", "apb_pclk";
909 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
910 <&dma 8 0 0x0>; /* Logical - MemToDev */
911 dma-names = "rx", "tx";
912 power-domains = <&pm_domains DOMAIN_VAPE>;
916 compatible = "arm,pl022", "arm,primecell";
917 reg = <0x80003000 0x1000>;
918 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
919 #address-cells = <1>;
921 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
922 clock-names = "SSPCLK", "apb_pclk";
923 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
924 <&dma 9 0 0x0>; /* Logical - MemToDev */
925 dma-names = "rx", "tx";
926 power-domains = <&pm_domains DOMAIN_VAPE>;
930 compatible = "arm,pl022", "arm,primecell";
931 reg = <0x8011a000 0x1000>;
932 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells = <1>;
935 /* Same clock wired to kernel and pclk */
936 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
937 clock-names = "SSPCLK", "apb_pclk";
938 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
939 <&dma 0 0 0x0>; /* Logical - MemToDev */
940 dma-names = "rx", "tx";
941 power-domains = <&pm_domains DOMAIN_VAPE>;
945 compatible = "arm,pl022", "arm,primecell";
946 reg = <0x80112000 0x1000>;
947 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
948 #address-cells = <1>;
950 /* Same clock wired to kernel and pclk */
951 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
952 clock-names = "SSPCLK", "apb_pclk";
953 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
954 <&dma 35 0 0x0>; /* Logical - MemToDev */
955 dma-names = "rx", "tx";
956 power-domains = <&pm_domains DOMAIN_VAPE>;
960 compatible = "arm,pl022", "arm,primecell";
961 reg = <0x80111000 0x1000>;
962 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
963 #address-cells = <1>;
965 /* Same clock wired to kernel and pclk */
966 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
967 clock-names = "SSPCLK", "apb_pclk";
968 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
969 <&dma 33 0 0x0>; /* Logical - MemToDev */
970 dma-names = "rx", "tx";
971 power-domains = <&pm_domains DOMAIN_VAPE>;
975 compatible = "arm,pl022", "arm,primecell";
976 reg = <0x80129000 0x1000>;
977 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
978 #address-cells = <1>;
980 /* Same clock wired to kernel and pclk */
981 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
982 clock-names = "SSPCLK", "apb_pclk";
983 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
984 <&dma 40 0 0x0>; /* Logical - MemToDev */
985 dma-names = "rx", "tx";
986 power-domains = <&pm_domains DOMAIN_VAPE>;
989 ux500_serial0: uart@80120000 {
990 compatible = "arm,pl011", "arm,primecell";
991 reg = <0x80120000 0x1000>;
992 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
994 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
995 <&dma 13 0 0x0>; /* Logical - MemToDev */
996 dma-names = "rx", "tx";
998 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
999 clock-names = "uart", "apb_pclk";
1001 status = "disabled";
1004 ux500_serial1: uart@80121000 {
1005 compatible = "arm,pl011", "arm,primecell";
1006 reg = <0x80121000 0x1000>;
1007 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1009 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
1010 <&dma 12 0 0x0>; /* Logical - MemToDev */
1011 dma-names = "rx", "tx";
1013 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
1014 clock-names = "uart", "apb_pclk";
1016 status = "disabled";
1019 ux500_serial2: uart@80007000 {
1020 compatible = "arm,pl011", "arm,primecell";
1021 reg = <0x80007000 0x1000>;
1022 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1024 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1025 <&dma 11 0 0x0>; /* Logical - MemToDev */
1026 dma-names = "rx", "tx";
1028 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1029 clock-names = "uart", "apb_pclk";
1031 status = "disabled";
1034 sdi0_per1@80126000 {
1035 compatible = "arm,pl18x", "arm,primecell";
1036 reg = <0x80126000 0x1000>;
1037 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1039 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1040 <&dma 29 0 0x0>; /* Logical - MemToDev */
1041 dma-names = "rx", "tx";
1043 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1044 clock-names = "sdi", "apb_pclk";
1045 power-domains = <&pm_domains DOMAIN_VAPE>;
1047 status = "disabled";
1050 sdi1_per2@80118000 {
1051 compatible = "arm,pl18x", "arm,primecell";
1052 reg = <0x80118000 0x1000>;
1053 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1055 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1056 <&dma 32 0 0x0>; /* Logical - MemToDev */
1057 dma-names = "rx", "tx";
1059 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1060 clock-names = "sdi", "apb_pclk";
1061 power-domains = <&pm_domains DOMAIN_VAPE>;
1063 status = "disabled";
1066 sdi2_per3@80005000 {
1067 compatible = "arm,pl18x", "arm,primecell";
1068 reg = <0x80005000 0x1000>;
1069 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1071 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1072 <&dma 28 0 0x0>; /* Logical - MemToDev */
1073 dma-names = "rx", "tx";
1075 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1076 clock-names = "sdi", "apb_pclk";
1077 power-domains = <&pm_domains DOMAIN_VAPE>;
1079 status = "disabled";
1082 sdi3_per2@80119000 {
1083 compatible = "arm,pl18x", "arm,primecell";
1084 reg = <0x80119000 0x1000>;
1085 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1087 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1088 <&dma 41 0 0x0>; /* Logical - MemToDev */
1089 dma-names = "rx", "tx";
1091 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1092 clock-names = "sdi", "apb_pclk";
1093 power-domains = <&pm_domains DOMAIN_VAPE>;
1095 status = "disabled";
1098 sdi4_per2@80114000 {
1099 compatible = "arm,pl18x", "arm,primecell";
1100 reg = <0x80114000 0x1000>;
1101 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1103 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1104 <&dma 42 0 0x0>; /* Logical - MemToDev */
1105 dma-names = "rx", "tx";
1107 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1108 clock-names = "sdi", "apb_pclk";
1109 power-domains = <&pm_domains DOMAIN_VAPE>;
1111 status = "disabled";
1114 sdi5_per3@80008000 {
1115 compatible = "arm,pl18x", "arm,primecell";
1116 reg = <0x80008000 0x1000>;
1117 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1120 <&dma 43 0 0x0>; /* Logical - MemToDev */
1121 dma-names = "rx", "tx";
1123 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1124 clock-names = "sdi", "apb_pclk";
1125 power-domains = <&pm_domains DOMAIN_VAPE>;
1127 status = "disabled";
1131 compatible = "stericsson,snd-soc-mop500";
1132 stericsson,cpu-dai = <&msp1 &msp3>;
1133 stericsson,audio-codec = <&codec>;
1134 clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
1135 clock-names = "sysclk", "ulpclk", "intclk";
1138 msp0: msp@80123000 {
1139 compatible = "stericsson,ux500-msp-i2s";
1140 reg = <0x80123000 0x1000>;
1141 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1142 v-ape-supply = <&db8500_vape_reg>;
1144 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1145 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1146 dma-names = "rx", "tx";
1148 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1149 clock-names = "msp", "apb_pclk";
1151 status = "disabled";
1154 msp1: msp@80124000 {
1155 compatible = "stericsson,ux500-msp-i2s";
1156 reg = <0x80124000 0x1000>;
1157 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1158 v-ape-supply = <&db8500_vape_reg>;
1160 /* This DMA channel only exist on DB8500 v1 */
1161 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1164 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1165 clock-names = "msp", "apb_pclk";
1167 status = "disabled";
1171 msp2: msp@80117000 {
1172 compatible = "stericsson,ux500-msp-i2s";
1173 reg = <0x80117000 0x1000>;
1174 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1175 v-ape-supply = <&db8500_vape_reg>;
1177 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1178 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1180 dma-names = "rx", "tx";
1182 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1183 clock-names = "msp", "apb_pclk";
1185 status = "disabled";
1188 msp3: msp@80125000 {
1189 compatible = "stericsson,ux500-msp-i2s";
1190 reg = <0x80125000 0x1000>;
1191 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1192 v-ape-supply = <&db8500_vape_reg>;
1194 /* This DMA channel only exist on DB8500 v2 */
1195 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1198 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1199 clock-names = "msp", "apb_pclk";
1201 status = "disabled";
1204 external-bus@50000000 {
1205 compatible = "simple-bus";
1206 reg = <0x50000000 0x4000000>;
1207 #address-cells = <1>;
1209 ranges = <0 0x50000000 0x4000000>;
1210 status = "disabled";
1215 * This block is referred to as "Smart Graphics Adapter SGA500"
1216 * in documentation but is in practice a pretty straight-forward
1217 * MALI-400 GPU block.
1219 compatible = "stericsson,db8500-mali", "arm,mali-400";
1220 reg = <0xa0300000 0x10000>;
1221 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1226 interrupt-names = "gp",
1231 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1232 clock-names = "bus", "core";
1233 mali-supply = <&db8500_sga_reg>;
1234 power-domains = <&pm_domains DOMAIN_VAPE>;
1238 compatible = "ste,mcde";
1239 reg = <0xa0350000 0x1000>;
1240 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1241 epod-supply = <&db8500_b2r2_mcde_reg>;
1242 vana-supply = <&ab8500_ldo_ana_reg>;
1243 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1244 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1245 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1246 clock-names = "mcde", "lcd", "hdmi";
1247 #address-cells = <1>;
1250 status = "disabled";
1252 dsi0: dsi@a0351000 {
1253 compatible = "ste,mcde-dsi";
1254 reg = <0xa0351000 0x1000>;
1255 vana-supply = <&ab8500_ldo_ana_reg>;
1256 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1257 clock-names = "hs", "lp";
1258 #address-cells = <1>;
1261 dsi1: dsi@a0352000 {
1262 compatible = "ste,mcde-dsi";
1263 reg = <0xa0352000 0x1000>;
1264 vana-supply = <&ab8500_ldo_ana_reg>;
1265 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1266 clock-names = "hs", "lp";
1267 #address-cells = <1>;
1270 dsi2: dsi@a0353000 {
1271 compatible = "ste,mcde-dsi";
1272 reg = <0xa0353000 0x1000>;
1273 vana-supply = <&ab8500_ldo_ana_reg>;
1274 /* This DSI port only has the Low Power / Energy Save clock */
1275 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1277 #address-cells = <1>;
1283 compatible = "stericsson,ux500-cryp";
1284 reg = <0xa03cb000 0x1000>;
1285 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1287 v-ape-supply = <&db8500_vape_reg>;
1288 clocks = <&prcc_pclk 6 1>;
1292 compatible = "stericsson,ux500-hash";
1293 reg = <0xa03c2000 0x1000>;
1295 v-ape-supply = <&db8500_vape_reg>;
1296 clocks = <&prcc_pclk 6 2>;