1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Linaro Ltd
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/mfd/dbx500-prcmu.h>
9 #include <dt-bindings/arm/ux500_pm_domains.h>
10 #include <dt-bindings/gpio/gpio.h>
22 enable-method = "ste,dbx500-smp";
36 compatible = "arm,cortex-a9";
38 /* cpufreq controls */
39 operating-points = <998400 0
43 clocks = <&prcmu_clk PRCMU_ARMSS>;
45 clock-latency = <20000>;
50 compatible = "arm,cortex-a9";
57 * Thermal zone for the SoC, using the thermal sensor in the
58 * PRCMU for temperature and the cpufreq driver for passive
61 cpu_thermal: cpu-thermal {
62 polling-delay-passive = <0>;
63 polling-delay = <1000>;
65 thermal-sensors = <&thermal>;
68 cpu_alert: cpu-alert {
69 temperature = <70000>;
74 temperature = <85000>;
82 cooling-device = <&CPU0 0 2>;
91 compatible = "stericsson,db8500";
92 interrupt-parent = <&intc>;
96 compatible = "arm,coresight-etm3x", "arm,primecell";
97 reg = <0x801ae000 0x1000>;
99 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
100 clock-names = "apb_pclk", "atclk";
104 ptm0_out_port: endpoint {
105 remote-endpoint = <&funnel_in_port0>;
112 compatible = "arm,coresight-etm3x", "arm,primecell";
113 reg = <0x801af000 0x1000>;
115 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
116 clock-names = "apb_pclk", "atclk";
120 ptm1_out_port: endpoint {
121 remote-endpoint = <&funnel_in_port1>;
128 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
129 reg = <0x801a6000 0x1000>;
131 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
132 clock-names = "apb_pclk", "atclk";
135 funnel_out_port: endpoint {
137 <&replicator_in_port0>;
143 #address-cells = <1>;
148 funnel_in_port0: endpoint {
149 remote-endpoint = <&ptm0_out_port>;
155 funnel_in_port1: endpoint {
156 remote-endpoint = <&ptm1_out_port>;
163 compatible = "arm,coresight-static-replicator";
164 clocks = <&prcmu_clk PRCMU_APEATCLK>;
165 clock-names = "atclk";
168 #address-cells = <1>;
173 replicator_out_port0: endpoint {
174 remote-endpoint = <&tpiu_in_port>;
179 replicator_out_port1: endpoint {
180 remote-endpoint = <&etb_in_port>;
187 replicator_in_port0: endpoint {
188 remote-endpoint = <&funnel_out_port>;
195 compatible = "arm,coresight-tpiu", "arm,primecell";
196 reg = <0x80190000 0x1000>;
198 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
199 clock-names = "apb_pclk", "atclk";
202 tpiu_in_port: endpoint {
203 remote-endpoint = <&replicator_out_port0>;
210 compatible = "arm,coresight-etb10", "arm,primecell";
211 reg = <0x801a4000 0x1000>;
213 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
214 clock-names = "apb_pclk", "atclk";
217 etb_in_port: endpoint {
218 remote-endpoint = <&replicator_out_port1>;
224 intc: interrupt-controller@a0411000 {
225 compatible = "arm,cortex-a9-gic";
226 #interrupt-cells = <3>;
227 #address-cells = <1>;
228 interrupt-controller;
229 reg = <0xa0411000 0x1000>,
234 compatible = "arm,cortex-a9-scu";
235 reg = <0xa0410000 0x100>;
239 * The backup RAM is used for retention during sleep
240 * and various things like spin tables
243 compatible = "ste,dbx500-backupram";
244 reg = <0x80150000 0x2000>;
248 compatible = "arm,pl310-cache";
249 reg = <0xa0412000 0x1000>;
250 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
256 compatible = "arm,cortex-a9-pmu";
257 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
260 pm_domains: pm_domains0 {
261 compatible = "stericsson,ux500-pm-domains";
262 #power-domain-cells = <1>;
266 compatible = "stericsson,u8500-clks";
268 * Registers for the CLKRST block on peripheral
269 * groups 1, 2, 3, 5, 6,
271 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
272 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
275 prcmu_clk: prcmu-clock {
279 prcc_pclk: prcc-periph-clock {
283 prcc_kclk: prcc-kernel-clock {
287 rtc_clk: rtc32k-clock {
291 smp_twd_clk: smp-twd-clock {
297 /* Nomadik System Timer */
298 compatible = "st,nomadik-mtu";
299 reg = <0xa03c6000 0x1000>;
300 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
303 clock-names = "timclk", "apb_pclk";
307 compatible = "arm,cortex-a9-twd-timer";
308 reg = <0xa0410600 0x20>;
309 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
311 clocks = <&smp_twd_clk>;
315 compatible = "arm,cortex-a9-twd-wdt";
316 reg = <0xa0410620 0x20>;
317 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
318 clocks = <&smp_twd_clk>;
322 compatible = "arm,rtc-pl031", "arm,primecell";
323 reg = <0x80154000 0x1000>;
324 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
327 clock-names = "apb_pclk";
330 gpio0: gpio@8012e000 {
331 compatible = "stericsson,db8500-gpio",
333 reg = <0x8012e000 0x80>;
334 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 st,supports-sleepmode;
341 gpio-ranges = <&pinctrl 0 0 32>;
342 clocks = <&prcc_pclk 1 9>;
345 gpio1: gpio@8012e080 {
346 compatible = "stericsson,db8500-gpio",
348 reg = <0x8012e080 0x80>;
349 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 st,supports-sleepmode;
356 gpio-ranges = <&pinctrl 0 32 5>;
357 clocks = <&prcc_pclk 1 9>;
360 gpio2: gpio@8000e000 {
361 compatible = "stericsson,db8500-gpio",
363 reg = <0x8000e000 0x80>;
364 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
367 st,supports-sleepmode;
371 gpio-ranges = <&pinctrl 0 64 32>;
372 clocks = <&prcc_pclk 3 8>;
375 gpio3: gpio@8000e080 {
376 compatible = "stericsson,db8500-gpio",
378 reg = <0x8000e080 0x80>;
379 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 st,supports-sleepmode;
386 gpio-ranges = <&pinctrl 0 96 2>;
387 clocks = <&prcc_pclk 3 8>;
390 gpio4: gpio@8000e100 {
391 compatible = "stericsson,db8500-gpio",
393 reg = <0x8000e100 0x80>;
394 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 st,supports-sleepmode;
401 gpio-ranges = <&pinctrl 0 128 32>;
402 clocks = <&prcc_pclk 3 8>;
405 gpio5: gpio@8000e180 {
406 compatible = "stericsson,db8500-gpio",
408 reg = <0x8000e180 0x80>;
409 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 st,supports-sleepmode;
416 gpio-ranges = <&pinctrl 0 160 12>;
417 clocks = <&prcc_pclk 3 8>;
420 gpio6: gpio@8011e000 {
421 compatible = "stericsson,db8500-gpio",
423 reg = <0x8011e000 0x80>;
424 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
427 st,supports-sleepmode;
431 gpio-ranges = <&pinctrl 0 192 32>;
432 clocks = <&prcc_pclk 2 11>;
435 gpio7: gpio@8011e080 {
436 compatible = "stericsson,db8500-gpio",
438 reg = <0x8011e080 0x80>;
439 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 st,supports-sleepmode;
446 gpio-ranges = <&pinctrl 0 224 7>;
447 clocks = <&prcc_pclk 2 11>;
450 gpio8: gpio@a03fe000 {
451 compatible = "stericsson,db8500-gpio",
453 reg = <0xa03fe000 0x80>;
454 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 st,supports-sleepmode;
461 gpio-ranges = <&pinctrl 0 256 12>;
462 clocks = <&prcc_pclk 5 1>;
466 compatible = "stericsson,db8500-pinctrl";
467 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
468 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
474 compatible = "stericsson,db8500-musb";
475 reg = <0xa03e0000 0x10000>;
476 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "mc";
481 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
482 <&dma 38 0 0x0>, /* Logical - MemToDev */
483 <&dma 37 0 0x2>, /* Logical - DevToMem */
484 <&dma 37 0 0x0>, /* Logical - MemToDev */
485 <&dma 36 0 0x2>, /* Logical - DevToMem */
486 <&dma 36 0 0x0>, /* Logical - MemToDev */
487 <&dma 19 0 0x2>, /* Logical - DevToMem */
488 <&dma 19 0 0x0>, /* Logical - MemToDev */
489 <&dma 18 0 0x2>, /* Logical - DevToMem */
490 <&dma 18 0 0x0>, /* Logical - MemToDev */
491 <&dma 17 0 0x2>, /* Logical - DevToMem */
492 <&dma 17 0 0x0>, /* Logical - MemToDev */
493 <&dma 16 0 0x2>, /* Logical - DevToMem */
494 <&dma 16 0 0x0>, /* Logical - MemToDev */
495 <&dma 39 0 0x2>, /* Logical - DevToMem */
496 <&dma 39 0 0x0>; /* Logical - MemToDev */
498 dma-names = "iep_1_9", "oep_1_9",
499 "iep_2_10", "oep_2_10",
500 "iep_3_11", "oep_3_11",
501 "iep_4_12", "oep_4_12",
502 "iep_5_13", "oep_5_13",
503 "iep_6_14", "oep_6_14",
504 "iep_7_15", "oep_7_15",
507 clocks = <&prcc_pclk 5 0>;
510 dma: dma-controller@801C0000 {
511 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
512 reg = <0x801C0000 0x1000 0x40010000 0x800>;
513 reg-names = "base", "lcpa";
514 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
517 memcpy-channels = <56 57 58 59 60>;
519 clocks = <&prcmu_clk PRCMU_DMACLK>;
522 prcmu: prcmu@80157000 {
523 compatible = "stericsson,db8500-prcmu", "syscon";
524 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
525 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
526 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
533 prcmu-timer-4@80157450 {
534 compatible = "stericsson,db8500-prcmu-timer-4";
535 reg = <0x80157450 0xC>;
538 thermal: thermal@801573c0 {
539 compatible = "stericsson,db8500-thermal";
540 reg = <0x801573c0 0x40>;
541 interrupt-parent = <&prcmu>;
542 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
543 <22 IRQ_TYPE_LEVEL_HIGH>;
544 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
545 #thermal-sensor-cells = <0>;
548 db8500-prcmu-regulators {
549 compatible = "stericsson,db8500-prcmu-regulator";
551 // DB8500_REGULATOR_VAPE
552 db8500_vape_reg: db8500_vape {
556 // DB8500_REGULATOR_VARM
557 db8500_varm_reg: db8500_varm {
560 // DB8500_REGULATOR_VMODEM
561 db8500_vmodem_reg: db8500_vmodem {
564 // DB8500_REGULATOR_VPLL
565 db8500_vpll_reg: db8500_vpll {
568 // DB8500_REGULATOR_VSMPS1
569 db8500_vsmps1_reg: db8500_vsmps1 {
572 // DB8500_REGULATOR_VSMPS2
573 db8500_vsmps2_reg: db8500_vsmps2 {
576 // DB8500_REGULATOR_VSMPS3
577 db8500_vsmps3_reg: db8500_vsmps3 {
580 // DB8500_REGULATOR_VRF1
581 db8500_vrf1_reg: db8500_vrf1 {
584 // DB8500_REGULATOR_SWITCH_SVAMMDSP
585 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
588 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
589 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
592 // DB8500_REGULATOR_SWITCH_SVAPIPE
593 db8500_sva_pipe_reg: db8500_sva_pipe {
596 // DB8500_REGULATOR_SWITCH_SIAMMDSP
597 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
600 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
601 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
604 // DB8500_REGULATOR_SWITCH_SIAPIPE
605 db8500_sia_pipe_reg: db8500_sia_pipe {
608 // DB8500_REGULATOR_SWITCH_SGA
609 db8500_sga_reg: db8500_sga {
610 vin-supply = <&db8500_vape_reg>;
613 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
614 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
615 vin-supply = <&db8500_vape_reg>;
618 // DB8500_REGULATOR_SWITCH_ESRAM12
619 db8500_esram12_reg: db8500_esram12 {
622 // DB8500_REGULATOR_SWITCH_ESRAM12RET
623 db8500_esram12_ret_reg: db8500_esram12_ret {
626 // DB8500_REGULATOR_SWITCH_ESRAM34
627 db8500_esram34_reg: db8500_esram34 {
630 // DB8500_REGULATOR_SWITCH_ESRAM34RET
631 db8500_esram34_ret_reg: db8500_esram34_ret {
637 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
638 reg = <0x80004000 0x1000>;
639 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
643 v-i2c-supply = <&db8500_vape_reg>;
645 clock-frequency = <400000>;
646 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
647 clock-names = "i2cclk", "apb_pclk";
648 power-domains = <&pm_domains DOMAIN_VAPE>;
652 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
653 reg = <0x80122000 0x1000>;
654 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
656 #address-cells = <1>;
658 v-i2c-supply = <&db8500_vape_reg>;
660 clock-frequency = <400000>;
662 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
663 clock-names = "i2cclk", "apb_pclk";
664 power-domains = <&pm_domains DOMAIN_VAPE>;
668 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
669 reg = <0x80128000 0x1000>;
670 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
672 #address-cells = <1>;
674 v-i2c-supply = <&db8500_vape_reg>;
676 clock-frequency = <400000>;
678 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
679 clock-names = "i2cclk", "apb_pclk";
680 power-domains = <&pm_domains DOMAIN_VAPE>;
684 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
685 reg = <0x80110000 0x1000>;
686 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
688 #address-cells = <1>;
690 v-i2c-supply = <&db8500_vape_reg>;
692 clock-frequency = <400000>;
694 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
695 clock-names = "i2cclk", "apb_pclk";
696 power-domains = <&pm_domains DOMAIN_VAPE>;
700 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
701 reg = <0x8012a000 0x1000>;
702 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
704 #address-cells = <1>;
706 v-i2c-supply = <&db8500_vape_reg>;
708 clock-frequency = <400000>;
710 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
711 clock-names = "i2cclk", "apb_pclk";
712 power-domains = <&pm_domains DOMAIN_VAPE>;
716 compatible = "arm,pl022", "arm,primecell";
717 reg = <0x80002000 0x1000>;
718 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <1>;
721 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
722 clock-names = "SSPCLK", "apb_pclk";
723 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
724 <&dma 8 0 0x0>; /* Logical - MemToDev */
725 dma-names = "rx", "tx";
726 power-domains = <&pm_domains DOMAIN_VAPE>;
730 compatible = "arm,pl022", "arm,primecell";
731 reg = <0x80003000 0x1000>;
732 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
733 #address-cells = <1>;
735 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
736 clock-names = "SSPCLK", "apb_pclk";
737 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
738 <&dma 9 0 0x0>; /* Logical - MemToDev */
739 dma-names = "rx", "tx";
740 power-domains = <&pm_domains DOMAIN_VAPE>;
744 compatible = "arm,pl022", "arm,primecell";
745 reg = <0x8011a000 0x1000>;
746 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
747 #address-cells = <1>;
749 /* Same clock wired to kernel and pclk */
750 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
751 clock-names = "SSPCLK", "apb_pclk";
752 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
753 <&dma 0 0 0x0>; /* Logical - MemToDev */
754 dma-names = "rx", "tx";
755 power-domains = <&pm_domains DOMAIN_VAPE>;
759 compatible = "arm,pl022", "arm,primecell";
760 reg = <0x80112000 0x1000>;
761 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
762 #address-cells = <1>;
764 /* Same clock wired to kernel and pclk */
765 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
766 clock-names = "SSPCLK", "apb_pclk";
767 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
768 <&dma 35 0 0x0>; /* Logical - MemToDev */
769 dma-names = "rx", "tx";
770 power-domains = <&pm_domains DOMAIN_VAPE>;
774 compatible = "arm,pl022", "arm,primecell";
775 reg = <0x80111000 0x1000>;
776 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
777 #address-cells = <1>;
779 /* Same clock wired to kernel and pclk */
780 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
781 clock-names = "SSPCLK", "apb_pclk";
782 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
783 <&dma 33 0 0x0>; /* Logical - MemToDev */
784 dma-names = "rx", "tx";
785 power-domains = <&pm_domains DOMAIN_VAPE>;
789 compatible = "arm,pl022", "arm,primecell";
790 reg = <0x80129000 0x1000>;
791 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
792 #address-cells = <1>;
794 /* Same clock wired to kernel and pclk */
795 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
796 clock-names = "SSPCLK", "apb_pclk";
797 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
798 <&dma 40 0 0x0>; /* Logical - MemToDev */
799 dma-names = "rx", "tx";
800 power-domains = <&pm_domains DOMAIN_VAPE>;
803 ux500_serial0: uart@80120000 {
804 compatible = "arm,pl011", "arm,primecell";
805 reg = <0x80120000 0x1000>;
806 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
808 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
809 <&dma 13 0 0x0>; /* Logical - MemToDev */
810 dma-names = "rx", "tx";
812 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
813 clock-names = "uart", "apb_pclk";
818 ux500_serial1: uart@80121000 {
819 compatible = "arm,pl011", "arm,primecell";
820 reg = <0x80121000 0x1000>;
821 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
823 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
824 <&dma 12 0 0x0>; /* Logical - MemToDev */
825 dma-names = "rx", "tx";
827 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
828 clock-names = "uart", "apb_pclk";
833 ux500_serial2: uart@80007000 {
834 compatible = "arm,pl011", "arm,primecell";
835 reg = <0x80007000 0x1000>;
836 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
838 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
839 <&dma 11 0 0x0>; /* Logical - MemToDev */
840 dma-names = "rx", "tx";
842 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
843 clock-names = "uart", "apb_pclk";
849 compatible = "arm,pl18x", "arm,primecell";
850 reg = <0x80126000 0x1000>;
851 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
853 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
854 <&dma 29 0 0x0>; /* Logical - MemToDev */
855 dma-names = "rx", "tx";
857 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
858 clock-names = "sdi", "apb_pclk";
859 power-domains = <&pm_domains DOMAIN_VAPE>;
865 compatible = "arm,pl18x", "arm,primecell";
866 reg = <0x80118000 0x1000>;
867 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
869 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
870 <&dma 32 0 0x0>; /* Logical - MemToDev */
871 dma-names = "rx", "tx";
873 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
874 clock-names = "sdi", "apb_pclk";
875 power-domains = <&pm_domains DOMAIN_VAPE>;
881 compatible = "arm,pl18x", "arm,primecell";
882 reg = <0x80005000 0x1000>;
883 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
885 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
886 <&dma 28 0 0x0>; /* Logical - MemToDev */
887 dma-names = "rx", "tx";
889 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
890 clock-names = "sdi", "apb_pclk";
891 power-domains = <&pm_domains DOMAIN_VAPE>;
897 compatible = "arm,pl18x", "arm,primecell";
898 reg = <0x80119000 0x1000>;
899 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
901 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
902 <&dma 41 0 0x0>; /* Logical - MemToDev */
903 dma-names = "rx", "tx";
905 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
906 clock-names = "sdi", "apb_pclk";
907 power-domains = <&pm_domains DOMAIN_VAPE>;
913 compatible = "arm,pl18x", "arm,primecell";
914 reg = <0x80114000 0x1000>;
915 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
917 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
918 <&dma 42 0 0x0>; /* Logical - MemToDev */
919 dma-names = "rx", "tx";
921 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
922 clock-names = "sdi", "apb_pclk";
923 power-domains = <&pm_domains DOMAIN_VAPE>;
929 compatible = "arm,pl18x", "arm,primecell";
930 reg = <0x80008000 0x1000>;
931 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
933 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
934 <&dma 43 0 0x0>; /* Logical - MemToDev */
935 dma-names = "rx", "tx";
937 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
938 clock-names = "sdi", "apb_pclk";
939 power-domains = <&pm_domains DOMAIN_VAPE>;
945 compatible = "stericsson,snd-soc-mop500";
946 stericsson,cpu-dai = <&msp1 &msp3>;
950 compatible = "stericsson,ux500-msp-i2s";
951 reg = <0x80123000 0x1000>;
952 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
953 v-ape-supply = <&db8500_vape_reg>;
955 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
956 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
957 dma-names = "rx", "tx";
959 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
960 clock-names = "msp", "apb_pclk";
966 compatible = "stericsson,ux500-msp-i2s";
967 reg = <0x80124000 0x1000>;
968 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
969 v-ape-supply = <&db8500_vape_reg>;
971 /* This DMA channel only exist on DB8500 v1 */
972 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
975 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
976 clock-names = "msp", "apb_pclk";
983 compatible = "stericsson,ux500-msp-i2s";
984 reg = <0x80117000 0x1000>;
985 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
986 v-ape-supply = <&db8500_vape_reg>;
988 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
989 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
991 dma-names = "rx", "tx";
993 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
994 clock-names = "msp", "apb_pclk";
1000 compatible = "stericsson,ux500-msp-i2s";
1001 reg = <0x80125000 0x1000>;
1002 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1003 v-ape-supply = <&db8500_vape_reg>;
1005 /* This DMA channel only exist on DB8500 v2 */
1006 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1009 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1010 clock-names = "msp", "apb_pclk";
1012 status = "disabled";
1015 external-bus@50000000 {
1016 compatible = "simple-bus";
1017 reg = <0x50000000 0x4000000>;
1018 #address-cells = <1>;
1020 ranges = <0 0x50000000 0x4000000>;
1021 status = "disabled";
1026 * This block is referred to as "Smart Graphics Adapter SGA500"
1027 * in documentation but is in practice a pretty straight-forward
1028 * MALI-400 GPU block.
1030 compatible = "stericsson,db8500-mali", "arm,mali-400";
1031 reg = <0xa0300000 0x10000>;
1032 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1037 interrupt-names = "gp",
1042 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1043 clock-names = "bus", "core";
1044 mali-supply = <&db8500_sga_reg>;
1045 power-domains = <&pm_domains DOMAIN_VAPE>;
1049 compatible = "ste,mcde";
1050 reg = <0xa0350000 0x1000>;
1051 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1052 epod-supply = <&db8500_b2r2_mcde_reg>;
1053 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1054 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1055 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1056 clock-names = "mcde", "lcd", "hdmi";
1057 #address-cells = <1>;
1060 status = "disabled";
1062 dsi0: dsi@a0351000 {
1063 compatible = "ste,mcde-dsi";
1064 reg = <0xa0351000 0x1000>;
1065 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1066 clock-names = "hs", "lp";
1067 #address-cells = <1>;
1070 dsi1: dsi@a0352000 {
1071 compatible = "ste,mcde-dsi";
1072 reg = <0xa0352000 0x1000>;
1073 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1074 clock-names = "hs", "lp";
1075 #address-cells = <1>;
1078 dsi2: dsi@a0353000 {
1079 compatible = "ste,mcde-dsi";
1080 reg = <0xa0353000 0x1000>;
1081 /* This DSI port only has the Low Power / Energy Save clock */
1082 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1084 #address-cells = <1>;
1090 compatible = "stericsson,ux500-cryp";
1091 reg = <0xa03cb000 0x1000>;
1092 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1094 v-ape-supply = <&db8500_vape_reg>;
1095 clocks = <&prcc_pclk 6 1>;
1099 compatible = "stericsson,ux500-hash";
1100 reg = <0xa03c2000 0x1000>;
1102 v-ape-supply = <&db8500_vape_reg>;
1103 clocks = <&prcc_pclk 6 2>;