1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Linaro Ltd
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
9 #include <dt-bindings/mfd/dbx500-prcmu.h>
10 #include <dt-bindings/arm/ux500_pm_domains.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/thermal/thermal.h>
18 /* This stablilizes the device enumeration */
40 enable-method = "ste,dbx500-smp";
54 compatible = "arm,cortex-a9";
56 clocks = <&prcmu_clk PRCMU_ARMSS>;
58 clock-latency = <20000>;
63 compatible = "arm,cortex-a9";
70 * Thermal zone for the SoC, using the thermal sensor in the
71 * PRCMU for temperature and the cpufreq driver for passive
74 cpu_thermal: cpu-thermal {
75 polling-delay-passive = <250>;
77 * This sensor fires interrupts to update the thermal
78 * zone, so no polling is needed.
82 thermal-sensors = <&thermal>;
85 cpu_alert: cpu-alert {
86 temperature = <70000>;
91 temperature = <85000>;
99 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
100 contribution = <100>;
106 #address-cells = <1>;
108 compatible = "stericsson,db8500", "simple-bus";
109 interrupt-parent = <&intc>;
113 compatible = "arm,coresight-etm3x", "arm,primecell";
114 reg = <0x801ae000 0x1000>;
116 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
117 clock-names = "apb_pclk", "atclk";
121 ptm0_out_port: endpoint {
122 remote-endpoint = <&funnel_in_port0>;
129 compatible = "arm,coresight-etm3x", "arm,primecell";
130 reg = <0x801af000 0x1000>;
132 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
133 clock-names = "apb_pclk", "atclk";
137 ptm1_out_port: endpoint {
138 remote-endpoint = <&funnel_in_port1>;
145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
146 reg = <0x801a6000 0x1000>;
148 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
149 clock-names = "apb_pclk", "atclk";
152 funnel_out_port: endpoint {
154 <&replicator_in_port0>;
160 #address-cells = <1>;
165 funnel_in_port0: endpoint {
166 remote-endpoint = <&ptm0_out_port>;
172 funnel_in_port1: endpoint {
173 remote-endpoint = <&ptm1_out_port>;
180 compatible = "arm,coresight-static-replicator";
181 clocks = <&prcmu_clk PRCMU_APEATCLK>;
182 clock-names = "atclk";
185 #address-cells = <1>;
190 replicator_out_port0: endpoint {
191 remote-endpoint = <&tpiu_in_port>;
196 replicator_out_port1: endpoint {
197 remote-endpoint = <&etb_in_port>;
204 replicator_in_port0: endpoint {
205 remote-endpoint = <&funnel_out_port>;
212 compatible = "arm,coresight-tpiu", "arm,primecell";
213 reg = <0x80190000 0x1000>;
215 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
216 clock-names = "apb_pclk", "atclk";
219 tpiu_in_port: endpoint {
220 remote-endpoint = <&replicator_out_port0>;
227 compatible = "arm,coresight-etb10", "arm,primecell";
228 reg = <0x801a4000 0x1000>;
230 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
231 clock-names = "apb_pclk", "atclk";
234 etb_in_port: endpoint {
235 remote-endpoint = <&replicator_out_port1>;
241 intc: interrupt-controller@a0411000 {
242 compatible = "arm,cortex-a9-gic";
243 #interrupt-cells = <3>;
244 #address-cells = <1>;
245 interrupt-controller;
246 reg = <0xa0411000 0x1000>,
251 compatible = "arm,cortex-a9-scu";
252 reg = <0xa0410000 0x100>;
256 * The backup RAM is used for retention during sleep
257 * and various things like spin tables
260 compatible = "ste,dbx500-backupram";
261 reg = <0x80150000 0x2000>;
264 L2: cache-controller {
265 compatible = "arm,pl310-cache";
266 reg = <0xa0412000 0x1000>;
267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
273 compatible = "arm,cortex-a9-pmu";
274 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
277 pm_domains: pm_domains0 {
278 compatible = "stericsson,ux500-pm-domains";
279 #power-domain-cells = <1>;
283 compatible = "stericsson,u8500-clks";
285 * Registers for the CLKRST block on peripheral
286 * groups 1, 2, 3, 5, 6,
288 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
289 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
292 prcmu_clk: prcmu-clock {
296 prcc_pclk: prcc-periph-clock {
300 prcc_kclk: prcc-kernel-clock {
304 prcc_reset: prcc-reset-controller {
308 rtc_clk: rtc32k-clock {
312 smp_twd_clk: smp-twd-clock {
318 /* Nomadik System Timer */
319 compatible = "st,nomadik-mtu";
320 reg = <0xa03c6000 0x1000>;
321 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
324 clock-names = "timclk", "apb_pclk";
328 compatible = "arm,cortex-a9-twd-timer";
329 reg = <0xa0410600 0x20>;
330 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
332 clocks = <&smp_twd_clk>;
336 compatible = "arm,cortex-a9-twd-wdt";
337 reg = <0xa0410620 0x20>;
338 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
339 clocks = <&smp_twd_clk>;
343 compatible = "arm,pl031", "arm,primecell";
344 reg = <0x80154000 0x1000>;
345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
348 clock-names = "apb_pclk";
351 gpio0: gpio@8012e000 {
352 compatible = "stericsson,db8500-gpio",
354 reg = <0x8012e000 0x80>;
355 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 st,supports-sleepmode;
362 gpio-ranges = <&pinctrl 0 0 32>;
363 clocks = <&prcc_pclk 1 9>;
366 gpio1: gpio@8012e080 {
367 compatible = "stericsson,db8500-gpio",
369 reg = <0x8012e080 0x80>;
370 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 st,supports-sleepmode;
377 gpio-ranges = <&pinctrl 0 32 5>;
378 clocks = <&prcc_pclk 1 9>;
381 gpio2: gpio@8000e000 {
382 compatible = "stericsson,db8500-gpio",
384 reg = <0x8000e000 0x80>;
385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 st,supports-sleepmode;
392 gpio-ranges = <&pinctrl 0 64 32>;
393 clocks = <&prcc_pclk 3 8>;
396 gpio3: gpio@8000e080 {
397 compatible = "stericsson,db8500-gpio",
399 reg = <0x8000e080 0x80>;
400 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 st,supports-sleepmode;
407 gpio-ranges = <&pinctrl 0 96 2>;
408 clocks = <&prcc_pclk 3 8>;
411 gpio4: gpio@8000e100 {
412 compatible = "stericsson,db8500-gpio",
414 reg = <0x8000e100 0x80>;
415 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 st,supports-sleepmode;
422 gpio-ranges = <&pinctrl 0 128 32>;
423 clocks = <&prcc_pclk 3 8>;
426 gpio5: gpio@8000e180 {
427 compatible = "stericsson,db8500-gpio",
429 reg = <0x8000e180 0x80>;
430 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 st,supports-sleepmode;
437 gpio-ranges = <&pinctrl 0 160 12>;
438 clocks = <&prcc_pclk 3 8>;
441 gpio6: gpio@8011e000 {
442 compatible = "stericsson,db8500-gpio",
444 reg = <0x8011e000 0x80>;
445 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 st,supports-sleepmode;
452 gpio-ranges = <&pinctrl 0 192 32>;
453 clocks = <&prcc_pclk 2 11>;
456 gpio7: gpio@8011e080 {
457 compatible = "stericsson,db8500-gpio",
459 reg = <0x8011e080 0x80>;
460 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 st,supports-sleepmode;
467 gpio-ranges = <&pinctrl 0 224 7>;
468 clocks = <&prcc_pclk 2 11>;
471 gpio8: gpio@a03fe000 {
472 compatible = "stericsson,db8500-gpio",
474 reg = <0xa03fe000 0x80>;
475 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 st,supports-sleepmode;
482 gpio-ranges = <&pinctrl 0 256 12>;
483 clocks = <&prcc_pclk 5 1>;
487 compatible = "stericsson,db8500-pinctrl";
488 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
489 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
495 compatible = "stericsson,db8500-musb";
496 reg = <0xa03e0000 0x10000>;
497 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-names = "mc";
502 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
503 <&dma 38 0 0x0>, /* Logical - MemToDev */
504 <&dma 37 0 0x2>, /* Logical - DevToMem */
505 <&dma 37 0 0x0>, /* Logical - MemToDev */
506 <&dma 36 0 0x2>, /* Logical - DevToMem */
507 <&dma 36 0 0x0>, /* Logical - MemToDev */
508 <&dma 19 0 0x2>, /* Logical - DevToMem */
509 <&dma 19 0 0x0>, /* Logical - MemToDev */
510 <&dma 18 0 0x2>, /* Logical - DevToMem */
511 <&dma 18 0 0x0>, /* Logical - MemToDev */
512 <&dma 17 0 0x2>, /* Logical - DevToMem */
513 <&dma 17 0 0x0>, /* Logical - MemToDev */
514 <&dma 16 0 0x2>, /* Logical - DevToMem */
515 <&dma 16 0 0x0>, /* Logical - MemToDev */
516 <&dma 39 0 0x2>, /* Logical - DevToMem */
517 <&dma 39 0 0x0>; /* Logical - MemToDev */
519 dma-names = "iep_1_9", "oep_1_9",
520 "iep_2_10", "oep_2_10",
521 "iep_3_11", "oep_3_11",
522 "iep_4_12", "oep_4_12",
523 "iep_5_13", "oep_5_13",
524 "iep_6_14", "oep_6_14",
525 "iep_7_15", "oep_7_15",
528 clocks = <&prcc_pclk 5 0>;
531 dma: dma-controller@801C0000 {
532 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
533 reg = <0x801C0000 0x1000 0x40010000 0x800>;
534 reg-names = "base", "lcpa";
535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
538 memcpy-channels = <56 57 58 59 60>;
540 clocks = <&prcmu_clk PRCMU_DMACLK>;
543 prcmu: prcmu@80157000 {
544 compatible = "stericsson,db8500-prcmu", "syscon";
545 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
546 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
547 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
554 prcmu-timer-4@80157450 {
555 compatible = "stericsson,db8500-prcmu-timer-4";
556 reg = <0x80157450 0xC>;
559 thermal: thermal@801573c0 {
560 compatible = "stericsson,db8500-thermal";
561 reg = <0x801573c0 0x40>;
562 interrupt-parent = <&prcmu>;
563 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
564 <22 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
566 #thermal-sensor-cells = <0>;
569 db8500-prcmu-regulators {
570 compatible = "stericsson,db8500-prcmu-regulator";
572 // DB8500_REGULATOR_VAPE
573 db8500_vape_reg: db8500_vape {
577 // DB8500_REGULATOR_VARM
578 db8500_varm_reg: db8500_varm {
581 // DB8500_REGULATOR_VMODEM
582 db8500_vmodem_reg: db8500_vmodem {
585 // DB8500_REGULATOR_VPLL
586 db8500_vpll_reg: db8500_vpll {
589 // DB8500_REGULATOR_VSMPS1
590 db8500_vsmps1_reg: db8500_vsmps1 {
593 // DB8500_REGULATOR_VSMPS2
594 db8500_vsmps2_reg: db8500_vsmps2 {
597 // DB8500_REGULATOR_VSMPS3
598 db8500_vsmps3_reg: db8500_vsmps3 {
601 // DB8500_REGULATOR_VRF1
602 db8500_vrf1_reg: db8500_vrf1 {
605 // DB8500_REGULATOR_SWITCH_SVAMMDSP
606 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
609 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
610 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
613 // DB8500_REGULATOR_SWITCH_SVAPIPE
614 db8500_sva_pipe_reg: db8500_sva_pipe {
617 // DB8500_REGULATOR_SWITCH_SIAMMDSP
618 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
621 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
622 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
625 // DB8500_REGULATOR_SWITCH_SIAPIPE
626 db8500_sia_pipe_reg: db8500_sia_pipe {
629 // DB8500_REGULATOR_SWITCH_SGA
630 db8500_sga_reg: db8500_sga {
631 vin-supply = <&db8500_vape_reg>;
634 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
635 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
636 vin-supply = <&db8500_vape_reg>;
639 // DB8500_REGULATOR_SWITCH_ESRAM12
640 db8500_esram12_reg: db8500_esram12 {
643 // DB8500_REGULATOR_SWITCH_ESRAM12RET
644 db8500_esram12_ret_reg: db8500_esram12_ret {
647 // DB8500_REGULATOR_SWITCH_ESRAM34
648 db8500_esram34_reg: db8500_esram34 {
651 // DB8500_REGULATOR_SWITCH_ESRAM34RET
652 db8500_esram34_ret_reg: db8500_esram34_ret {
658 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
659 reg = <0x80004000 0x1000>;
660 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
662 #address-cells = <1>;
664 v-i2c-supply = <&db8500_vape_reg>;
666 clock-frequency = <400000>;
667 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
668 clock-names = "i2cclk", "apb_pclk";
669 power-domains = <&pm_domains DOMAIN_VAPE>;
670 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;
676 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
677 reg = <0x80122000 0x1000>;
678 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
680 #address-cells = <1>;
682 v-i2c-supply = <&db8500_vape_reg>;
684 clock-frequency = <400000>;
686 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
687 clock-names = "i2cclk", "apb_pclk";
688 power-domains = <&pm_domains DOMAIN_VAPE>;
689 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>;
695 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
696 reg = <0x80128000 0x1000>;
697 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
701 v-i2c-supply = <&db8500_vape_reg>;
703 clock-frequency = <400000>;
705 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
706 clock-names = "i2cclk", "apb_pclk";
707 power-domains = <&pm_domains DOMAIN_VAPE>;
708 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>;
714 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
715 reg = <0x80110000 0x1000>;
716 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells = <1>;
720 v-i2c-supply = <&db8500_vape_reg>;
722 clock-frequency = <400000>;
724 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
725 clock-names = "i2cclk", "apb_pclk";
726 power-domains = <&pm_domains DOMAIN_VAPE>;
727 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>;
733 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
734 reg = <0x8012a000 0x1000>;
735 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
737 #address-cells = <1>;
739 v-i2c-supply = <&db8500_vape_reg>;
741 clock-frequency = <400000>;
743 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
744 clock-names = "i2cclk", "apb_pclk";
745 power-domains = <&pm_domains DOMAIN_VAPE>;
746 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>;
752 compatible = "arm,pl022", "arm,primecell";
753 reg = <0x80002000 0x1000>;
754 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>;
757 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
758 clock-names = "SSPCLK", "apb_pclk";
759 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
760 <&dma 8 0 0x0>; /* Logical - MemToDev */
761 dma-names = "rx", "tx";
762 power-domains = <&pm_domains DOMAIN_VAPE>;
763 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>;
769 compatible = "arm,pl022", "arm,primecell";
770 reg = <0x80003000 0x1000>;
771 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
772 #address-cells = <1>;
774 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
775 clock-names = "SSPCLK", "apb_pclk";
776 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
777 <&dma 9 0 0x0>; /* Logical - MemToDev */
778 dma-names = "rx", "tx";
779 power-domains = <&pm_domains DOMAIN_VAPE>;
780 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>;
786 compatible = "arm,pl022", "arm,primecell";
787 reg = <0x8011a000 0x1000>;
788 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
789 #address-cells = <1>;
791 /* Same clock wired to kernel and pclk */
792 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
793 clock-names = "SSPCLK", "apb_pclk";
794 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
795 <&dma 0 0 0x0>; /* Logical - MemToDev */
796 dma-names = "rx", "tx";
797 power-domains = <&pm_domains DOMAIN_VAPE>;
803 compatible = "arm,pl022", "arm,primecell";
804 reg = <0x80112000 0x1000>;
805 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
806 #address-cells = <1>;
808 /* Same clock wired to kernel and pclk */
809 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
810 clock-names = "SSPCLK", "apb_pclk";
811 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
812 <&dma 35 0 0x0>; /* Logical - MemToDev */
813 dma-names = "rx", "tx";
814 power-domains = <&pm_domains DOMAIN_VAPE>;
820 compatible = "arm,pl022", "arm,primecell";
821 reg = <0x80111000 0x1000>;
822 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
823 #address-cells = <1>;
825 /* Same clock wired to kernel and pclk */
826 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
827 clock-names = "SSPCLK", "apb_pclk";
828 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
829 <&dma 33 0 0x0>; /* Logical - MemToDev */
830 dma-names = "rx", "tx";
831 power-domains = <&pm_domains DOMAIN_VAPE>;
837 compatible = "arm,pl022", "arm,primecell";
838 reg = <0x80129000 0x1000>;
839 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
840 #address-cells = <1>;
842 /* Same clock wired to kernel and pclk */
843 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
844 clock-names = "SSPCLK", "apb_pclk";
845 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
846 <&dma 40 0 0x0>; /* Logical - MemToDev */
847 dma-names = "rx", "tx";
848 power-domains = <&pm_domains DOMAIN_VAPE>;
849 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>;
854 serial0: uart@80120000 {
855 compatible = "arm,pl011", "arm,primecell";
856 reg = <0x80120000 0x1000>;
857 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
859 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
860 <&dma 13 0 0x0>; /* Logical - MemToDev */
861 dma-names = "rx", "tx";
863 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
864 clock-names = "uart", "apb_pclk";
865 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>;
870 serial1: uart@80121000 {
871 compatible = "arm,pl011", "arm,primecell";
872 reg = <0x80121000 0x1000>;
873 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
875 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
876 <&dma 12 0 0x0>; /* Logical - MemToDev */
877 dma-names = "rx", "tx";
879 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
880 clock-names = "uart", "apb_pclk";
881 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>;
886 serial2: uart@80007000 {
887 compatible = "arm,pl011", "arm,primecell";
888 reg = <0x80007000 0x1000>;
889 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
891 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
892 <&dma 11 0 0x0>; /* Logical - MemToDev */
893 dma-names = "rx", "tx";
895 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
896 clock-names = "uart", "apb_pclk";
897 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>;
903 compatible = "arm,pl18x", "arm,primecell";
904 reg = <0x80126000 0x1000>;
905 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
907 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
908 <&dma 29 0 0x0>; /* Logical - MemToDev */
909 dma-names = "rx", "tx";
911 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
912 clock-names = "sdi", "apb_pclk";
913 power-domains = <&pm_domains DOMAIN_VAPE>;
914 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>;
920 compatible = "arm,pl18x", "arm,primecell";
921 reg = <0x80118000 0x1000>;
922 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
924 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
925 <&dma 32 0 0x0>; /* Logical - MemToDev */
926 dma-names = "rx", "tx";
928 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
929 clock-names = "sdi", "apb_pclk";
930 power-domains = <&pm_domains DOMAIN_VAPE>;
931 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>;
937 compatible = "arm,pl18x", "arm,primecell";
938 reg = <0x80005000 0x1000>;
939 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
941 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
942 <&dma 28 0 0x0>; /* Logical - MemToDev */
943 dma-names = "rx", "tx";
945 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
946 clock-names = "sdi", "apb_pclk";
947 power-domains = <&pm_domains DOMAIN_VAPE>;
948 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>;
954 compatible = "arm,pl18x", "arm,primecell";
955 reg = <0x80119000 0x1000>;
956 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
958 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
959 <&dma 41 0 0x0>; /* Logical - MemToDev */
960 dma-names = "rx", "tx";
962 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
963 clock-names = "sdi", "apb_pclk";
964 power-domains = <&pm_domains DOMAIN_VAPE>;
965 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>;
971 compatible = "arm,pl18x", "arm,primecell";
972 reg = <0x80114000 0x1000>;
973 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
975 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
976 <&dma 42 0 0x0>; /* Logical - MemToDev */
977 dma-names = "rx", "tx";
979 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
980 clock-names = "sdi", "apb_pclk";
981 power-domains = <&pm_domains DOMAIN_VAPE>;
982 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>;
988 compatible = "arm,pl18x", "arm,primecell";
989 reg = <0x80008000 0x1000>;
990 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
992 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
993 <&dma 43 0 0x0>; /* Logical - MemToDev */
994 dma-names = "rx", "tx";
996 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
997 clock-names = "sdi", "apb_pclk";
998 power-domains = <&pm_domains DOMAIN_VAPE>;
999 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>;
1001 status = "disabled";
1005 compatible = "stericsson,snd-soc-mop500";
1006 stericsson,cpu-dai = <&msp1 &msp3>;
1009 msp0: msp@80123000 {
1010 compatible = "stericsson,ux500-msp-i2s";
1011 reg = <0x80123000 0x1000>;
1012 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1013 v-ape-supply = <&db8500_vape_reg>;
1015 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1016 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1017 dma-names = "rx", "tx";
1019 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1020 clock-names = "msp", "apb_pclk";
1021 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>;
1023 status = "disabled";
1026 msp1: msp@80124000 {
1027 compatible = "stericsson,ux500-msp-i2s";
1028 reg = <0x80124000 0x1000>;
1029 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1030 v-ape-supply = <&db8500_vape_reg>;
1032 /* This DMA channel only exist on DB8500 v1 */
1033 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1036 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1037 clock-names = "msp", "apb_pclk";
1038 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>;
1040 status = "disabled";
1044 msp2: msp@80117000 {
1045 compatible = "stericsson,ux500-msp-i2s";
1046 reg = <0x80117000 0x1000>;
1047 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1048 v-ape-supply = <&db8500_vape_reg>;
1050 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1051 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1053 dma-names = "rx", "tx";
1055 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1056 clock-names = "msp", "apb_pclk";
1057 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>;
1059 status = "disabled";
1062 msp3: msp@80125000 {
1063 compatible = "stericsson,ux500-msp-i2s";
1064 reg = <0x80125000 0x1000>;
1065 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1066 v-ape-supply = <&db8500_vape_reg>;
1068 /* This DMA channel only exist on DB8500 v2 */
1069 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1072 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1073 clock-names = "msp", "apb_pclk";
1074 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>;
1076 status = "disabled";
1079 external-bus@50000000 {
1080 compatible = "simple-bus";
1081 reg = <0x50000000 0x4000000>;
1082 #address-cells = <1>;
1084 ranges = <0 0x50000000 0x4000000>;
1085 status = "disabled";
1090 * This block is referred to as "Smart Graphics Adapter SGA500"
1091 * in documentation but is in practice a pretty straight-forward
1092 * MALI-400 GPU block.
1094 compatible = "stericsson,db8500-mali", "arm,mali-400";
1095 reg = <0xa0300000 0x10000>;
1096 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1101 interrupt-names = "gp",
1106 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1107 clock-names = "bus", "core";
1108 mali-supply = <&db8500_sga_reg>;
1109 power-domains = <&pm_domains DOMAIN_VAPE>;
1113 compatible = "ste,mcde";
1114 reg = <0xa0350000 0x1000>;
1115 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1116 epod-supply = <&db8500_b2r2_mcde_reg>;
1117 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1118 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1119 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1120 clock-names = "mcde", "lcd", "hdmi";
1121 #address-cells = <1>;
1124 status = "disabled";
1126 dsi0: dsi@a0351000 {
1127 compatible = "ste,mcde-dsi";
1128 reg = <0xa0351000 0x1000>;
1129 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1130 clock-names = "hs", "lp";
1131 #address-cells = <1>;
1134 dsi1: dsi@a0352000 {
1135 compatible = "ste,mcde-dsi";
1136 reg = <0xa0352000 0x1000>;
1137 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1138 clock-names = "hs", "lp";
1139 #address-cells = <1>;
1142 dsi2: dsi@a0353000 {
1143 compatible = "ste,mcde-dsi";
1144 reg = <0xa0353000 0x1000>;
1145 /* This DSI port only has the Low Power / Energy Save clock */
1146 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1148 #address-cells = <1>;
1154 compatible = "stericsson,ux500-cryp";
1155 reg = <0xa03cb000 0x1000>;
1156 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1158 v-ape-supply = <&db8500_vape_reg>;
1159 clocks = <&prcc_pclk 6 1>;
1163 compatible = "stericsson,ux500-hash";
1164 reg = <0xa03c2000 0x1000>;
1166 v-ape-supply = <&db8500_vape_reg>;
1167 clocks = <&prcc_pclk 6 2>;