arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Altera Corporation <www.altera.com>
   4  */
   5 #include "socfpga_arria10.dtsi"
   6
   7 / {
   8         model = "Altera SOCFPGA Arria 10";
   9         compatible = "altr,socfpga-arria10", "altr,socfpga";
  10
  11         aliases {
  12                 ethernet0 = &gmac0;
  13                 serial0 = &uart1;
  14         };
  15
  16         chosen {
  17                 bootargs = "earlyprintk";
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         memory@0 {
  22                 name = "memory";
  23                 device_type = "memory";
  24                 reg = <0x0 0x40000000>; /* 1GB */
  25         };
  26
  27         a10leds {
  28                 compatible = "gpio-leds";
  29
  30                 a10sr_led0 {
  31                         label = "a10sr-led0";
  32                         gpios = <&a10sr_gpio 0 1>;
  33                 };
  34
  35                 a10sr_led1 {
  36                         label = "a10sr-led1";
  37                         gpios = <&a10sr_gpio 1 1>;
  38                 };
  39
  40                 a10sr_led2 {
  41                         label = "a10sr-led2";
  42                         gpios = <&a10sr_gpio 2 1>;
  43                 };
  44
  45                 a10sr_led3 {
  46                         label = "a10sr-led3";
  47                         gpios = <&a10sr_gpio 3 1>;
  48                 };
  49         };
  50
  51         soc {
  52                 clkmgr@ffd04000 {
  53                         clocks {
  54                                 osc1 {
  55                                         clock-frequency = <25000000>;
  56                                 };
  57                         };
  58                 };
  59         };
  60 };
  61
  62 &gmac0 {
  63         phy-mode = "rgmii";
  64         phy-addr = <0xffffffff>; /* probe for phy addr */
  65
  66         /*
  67          * These skews assume the user's FPGA design is adding 600ps of delay
  68          * for TX_CLK on Arria 10.
  69          *
  70          * All skews are offset since hardware skew values for the ksz9031
  71          * range from a negative skew to a positive skew.
  72          * See the micrel-ksz90x1.txt Documentation file for details.
  73          */
  74         txd0-skew-ps = <0>; /* -420ps */
  75         txd1-skew-ps = <0>; /* -420ps */
  76         txd2-skew-ps = <0>; /* -420ps */
  77         txd3-skew-ps = <0>; /* -420ps */
  78         rxd0-skew-ps = <420>; /* 0ps */
  79         rxd1-skew-ps = <420>; /* 0ps */
  80         rxd2-skew-ps = <420>; /* 0ps */
  81         rxd3-skew-ps = <420>; /* 0ps */
  82         txen-skew-ps = <0>; /* -420ps */
  83         txc-skew-ps = <1860>; /* 960ps */
  84         rxdv-skew-ps = <420>; /* 0ps */
  85         rxc-skew-ps = <1680>; /* 780ps */
  86         max-frame-size = <3800>;
  87         status = "okay";
  88 };
  89
  90 &gpio1 {
  91         status = "okay";
  92 };
  93
  94 &spi1 {
  95         status = "okay";
  96
  97         resource-manager@0 {
  98                 compatible = "altr,a10sr";
  99                 reg = <0>;
 100                 spi-max-frequency = <100000>;
 101                 /* low-level active IRQ at GPIO1_5 */
 102                 interrupt-parent = <&portb>;
 103                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
 104                 interrupt-controller;
 105                 #interrupt-cells = <2>;
 106
 107                 a10sr_gpio: gpio-controller {
 108                         compatible = "altr,a10sr-gpio";
 109                         gpio-controller;
 110                         #gpio-cells = <2>;
 111                 };
 112
 113                 a10sr_rst: reset-controller {
 114                         compatible = "altr,a10sr-reset";
 115                         #reset-cells = <1>;
 116                 };
 117         };
 118 };
 119
 120 &i2c1 {
 121         status = "okay";
 122
 123         /*
 124          * adjust the falling times to decrease the i2c frequency to 50Khz
 125          * because the LCD module does not work at the standard 100Khz
 126          */
 127         clock-frequency = <100000>;
 128         i2c-sda-falling-time-ns = <6000>;
 129         i2c-scl-falling-time-ns = <6000>;
 130
 131         eeprom@51 {
 132                 compatible = "atmel,24c32";
 133                 reg = <0x51>;
 134                 pagesize = <32>;
 135         };
 136
 137         rtc@68 {
 138                 compatible = "dallas,ds1339";
 139                 reg = <0x68>;
 140         };
 141
 142         ltc@5c {
 143                 compatible = "ltc2977";
 144                 reg = <0x5c>;
 145         };
 146 };
 147
 148 &uart1 {
 149         status = "okay";
 150 };
 151
 152 &usb0 {
 153         status = "okay";
 154         disable-over-current;
 155 };
 156
 157 &watchdog1 {
 158         status = "okay";
 159 };