arch/arm/boot/dts/socfpga_arria10.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright Altera Corporation (C) 2014. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16                 enable-method = "altr,socfpga-a10-smp";
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a9";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                 };
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                         next-level-cache = <&L2>;
  29                 };
  30         };
  31
  32         pmu: pmu@ff111000 {
  33                 compatible = "arm,cortex-a9-pmu";
  34                 interrupt-parent = <&intc>;
  35                 interrupts = <0 124 4>, <0 125 4>;
  36                 interrupt-affinity = <&cpu0>, <&cpu1>;
  37                 reg = <0xff111000 0x1000>,
  38                       <0xff113000 0x1000>;
  39         };
  40
  41         intc: intc@ffffd000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 #interrupt-cells = <3>;
  44                 interrupt-controller;
  45                 reg = <0xffffd000 0x1000>,
  46                       <0xffffc100 0x100>;
  47         };
  48
  49         soc {
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 compatible = "simple-bus";
  53                 device_type = "soc";
  54                 interrupt-parent = <&intc>;
  55                 ranges;
  56
  57                 amba {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges;
  62
  63                         pdma: pdma@ffda1000 {
  64                                 compatible = "arm,pl330", "arm,primecell";
  65                                 reg = <0xffda1000 0x1000>;
  66                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  67                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  68                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  69                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  70                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  71                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  72                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  73                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  74                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  75                                 #dma-cells = <1>;
  76                                 #dma-channels = <8>;
  77                                 #dma-requests = <32>;
  78                                 clocks = <&l4_main_clk>;
  79                                 clock-names = "apb_pclk";
  80                                 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
  81                                 reset-names = "dma", "dma-ocp";
  82                         };
  83                 };
  84
  85                 base_fpga_region {
  86                         #address-cells = <0x1>;
  87                         #size-cells = <0x1>;
  88
  89                         compatible = "fpga-region";
  90                         fpga-mgr = <&fpga_mgr>;
  91                 };
  92
  93                 clkmgr@ffd04000 {
  94                                 compatible = "altr,clk-mgr";
  95                                 reg = <0xffd04000 0x1000>;
  96
  97                                 clocks {
  98                                         #address-cells = <1>;
  99                                         #size-cells = <0>;
 100
 101                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 102                                                 #clock-cells = <0>;
 103                                                 compatible = "fixed-clock";
 104                                         };
 105
 106                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
 107                                                 #clock-cells = <0>;
 108                                                 compatible = "fixed-clock";
 109                                         };
 110
 111                                         f2s_free_clk: f2s_free_clk {
 112                                                 #clock-cells = <0>;
 113                                                 compatible = "fixed-clock";
 114                                         };
 115
 116                                         osc1: osc1 {
 117                                                 #clock-cells = <0>;
 118                                                 compatible = "fixed-clock";
 119                                         };
 120
 121                                         main_pll: main_pll@40 {
 122                                                 #address-cells = <1>;
 123                                                 #size-cells = <0>;
 124                                                 #clock-cells = <0>;
 125                                                 compatible = "altr,socfpga-a10-pll-clock";
 126                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 127                                                          <&f2s_free_clk>;
 128                                                 reg = <0x40>;
 129
 130                                                 main_mpu_base_clk: main_mpu_base_clk {
 131                                                         #clock-cells = <0>;
 132                                                         compatible = "altr,socfpga-a10-perip-clk";
 133                                                         clocks = <&main_pll>;
 134                                                         div-reg = <0x140 0 11>;
 135                                                 };
 136
 137                                                 main_noc_base_clk: main_noc_base_clk {
 138                                                         #clock-cells = <0>;
 139                                                         compatible = "altr,socfpga-a10-perip-clk";
 140                                                         clocks = <&main_pll>;
 141                                                         div-reg = <0x144 0 11>;
 142                                                 };
 143
 144                                                 main_emaca_clk: main_emaca_clk@68 {
 145                                                         #clock-cells = <0>;
 146                                                         compatible = "altr,socfpga-a10-perip-clk";
 147                                                         clocks = <&main_pll>;
 148                                                         reg = <0x68>;
 149                                                 };
 150
 151                                                 main_emacb_clk: main_emacb_clk@6c {
 152                                                         #clock-cells = <0>;
 153                                                         compatible = "altr,socfpga-a10-perip-clk";
 154                                                         clocks = <&main_pll>;
 155                                                         reg = <0x6C>;
 156                                                 };
 157
 158                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
 159                                                         #clock-cells = <0>;
 160                                                         compatible = "altr,socfpga-a10-perip-clk";
 161                                                         clocks = <&main_pll>;
 162                                                         reg = <0x70>;
 163                                                 };
 164
 165                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
 166                                                         #clock-cells = <0>;
 167                                                         compatible = "altr,socfpga-a10-perip-clk";
 168                                                         clocks = <&main_pll>;
 169                                                         reg = <0x74>;
 170                                                 };
 171
 172                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
 173                                                         #clock-cells = <0>;
 174                                                         compatible = "altr,socfpga-a10-perip-clk"
 175 ;
 176                                                         clocks = <&main_pll>;
 177                                                         reg = <0x78>;
 178                                                 };
 179
 180                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
 181                                                         #clock-cells = <0>;
 182                                                         compatible = "altr,socfpga-a10-perip-clk";
 183                                                         clocks = <&main_pll>;
 184                                                         reg = <0x7C>;
 185                                                 };
 186
 187                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
 188                                                         #clock-cells = <0>;
 189                                                         compatible = "altr,socfpga-a10-perip-clk";
 190                                                         clocks = <&main_pll>;
 191                                                         reg = <0x80>;
 192                                                 };
 193
 194                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
 195                                                         #clock-cells = <0>;
 196                                                         compatible = "altr,socfpga-a10-perip-clk";
 197                                                         clocks = <&main_pll>;
 198                                                         reg = <0x84>;
 199                                                 };
 200
 201                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
 202                                                         #clock-cells = <0>;
 203                                                         compatible = "altr,socfpga-a10-perip-clk";
 204                                                         clocks = <&main_pll>;
 205                                                         reg = <0x9C>;
 206                                                 };
 207                                         };
 208
 209                                         periph_pll: periph_pll@c0 {
 210                                                 #address-cells = <1>;
 211                                                 #size-cells = <0>;
 212                                                 #clock-cells = <0>;
 213                                                 compatible = "altr,socfpga-a10-pll-clock";
 214                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 215                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 216                                                 reg = <0xC0>;
 217
 218                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 219                                                         #clock-cells = <0>;
 220                                                         compatible = "altr,socfpga-a10-perip-clk";
 221                                                         clocks = <&periph_pll>;
 222                                                         div-reg = <0x140 16 11>;
 223                                                 };
 224
 225                                                 peri_noc_base_clk: peri_noc_base_clk {
 226                                                         #clock-cells = <0>;
 227                                                         compatible = "altr,socfpga-a10-perip-clk";
 228                                                         clocks = <&periph_pll>;
 229                                                         div-reg = <0x144 16 11>;
 230                                                 };
 231
 232                                                 peri_emaca_clk: peri_emaca_clk@e8 {
 233                                                         #clock-cells = <0>;
 234                                                         compatible = "altr,socfpga-a10-perip-clk";
 235                                                         clocks = <&periph_pll>;
 236                                                         reg = <0xE8>;
 237                                                 };
 238
 239                                                 peri_emacb_clk: peri_emacb_clk@ec {
 240                                                         #clock-cells = <0>;
 241                                                         compatible = "altr,socfpga-a10-perip-clk";
 242                                                         clocks = <&periph_pll>;
 243                                                         reg = <0xEC>;
 244                                                 };
 245
 246                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
 247                                                         #clock-cells = <0>;
 248                                                         compatible = "altr,socfpga-a10-perip-clk";
 249                                                         clocks = <&periph_pll>;
 250                                                         reg = <0xF0>;
 251                                                 };
 252
 253                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
 254                                                         #clock-cells = <0>;
 255                                                         compatible = "altr,socfpga-a10-perip-clk";
 256                                                         clocks = <&periph_pll>;
 257                                                         reg = <0xF4>;
 258                                                 };
 259
 260                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
 261                                                         #clock-cells = <0>;
 262                                                         compatible = "altr,socfpga-a10-perip-clk";
 263                                                         clocks = <&periph_pll>;
 264                                                         reg = <0xF8>;
 265                                                 };
 266
 267                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
 268                                                         #clock-cells = <0>;
 269                                                         compatible = "altr,socfpga-a10-perip-clk";
 270                                                         clocks = <&periph_pll>;
 271                                                         reg = <0xFC>;
 272                                                 };
 273
 274                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
 275                                                         #clock-cells = <0>;
 276                                                         compatible = "altr,socfpga-a10-perip-clk";
 277                                                         clocks = <&periph_pll>;
 278                                                         reg = <0x100>;
 279                                                 };
 280
 281                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
 282                                                         #clock-cells = <0>;
 283                                                         compatible = "altr,socfpga-a10-perip-clk";
 284                                                         clocks = <&periph_pll>;
 285                                                         reg = <0x104>;
 286                                                 };
 287                                         };
 288
 289                                         mpu_free_clk: mpu_free_clk@60 {
 290                                                 #clock-cells = <0>;
 291                                                 compatible = "altr,socfpga-a10-perip-clk";
 292                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 293                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 294                                                          <&f2s_free_clk>;
 295                                                 reg = <0x60>;
 296                                         };
 297
 298                                         noc_free_clk: noc_free_clk@64 {
 299                                                 #clock-cells = <0>;
 300                                                 compatible = "altr,socfpga-a10-perip-clk";
 301                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 302                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 303                                                          <&f2s_free_clk>;
 304                                                 reg = <0x64>;
 305                                         };
 306
 307                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
 308                                                 #clock-cells = <0>;
 309                                                 compatible = "altr,socfpga-a10-perip-clk";
 310                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 311                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 312                                                          <&f2s_free_clk>;
 313                                                 reg = <0x104>;
 314                                         };
 315
 316                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
 317                                                 #clock-cells = <0>;
 318                                                 compatible = "altr,socfpga-a10-perip-clk";
 319                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 320                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 321                                                          <&f2s_free_clk>;
 322                                                 fixed-divider = <4>;
 323                                                 reg = <0xF8>;
 324                                         };
 325
 326                                         l4_sys_free_clk: l4_sys_free_clk {
 327                                                 #clock-cells = <0>;
 328                                                 compatible = "altr,socfpga-a10-perip-clk";
 329                                                 clocks = <&noc_free_clk>;
 330                                                 fixed-divider = <4>;
 331                                         };
 332
 333                                         l4_main_clk: l4_main_clk {
 334                                                 #clock-cells = <0>;
 335                                                 compatible = "altr,socfpga-a10-gate-clk";
 336                                                 clocks = <&noc_free_clk>;
 337                                                 div-reg = <0xA8 0 2>;
 338                                                 clk-gate = <0x48 1>;
 339                                         };
 340
 341                                         l4_mp_clk: l4_mp_clk {
 342                                                 #clock-cells = <0>;
 343                                                 compatible = "altr,socfpga-a10-gate-clk";
 344                                                 clocks = <&noc_free_clk>;
 345                                                 div-reg = <0xA8 8 2>;
 346                                                 clk-gate = <0x48 2>;
 347                                         };
 348
 349                                         l4_sp_clk: l4_sp_clk {
 350                                                 #clock-cells = <0>;
 351                                                 compatible = "altr,socfpga-a10-gate-clk";
 352                                                 clocks = <&noc_free_clk>;
 353                                                 div-reg = <0xA8 16 2>;
 354                                                 clk-gate = <0x48 3>;
 355                                         };
 356
 357                                         mpu_periph_clk: mpu_periph_clk {
 358                                                 #clock-cells = <0>;
 359                                                 compatible = "altr,socfpga-a10-gate-clk";
 360                                                 clocks = <&mpu_free_clk>;
 361                                                 fixed-divider = <4>;
 362                                                 clk-gate = <0x48 0>;
 363                                         };
 364
 365                                         sdmmc_clk: sdmmc_clk {
 366                                                 #clock-cells = <0>;
 367                                                 compatible = "altr,socfpga-a10-gate-clk";
 368                                                 clocks = <&sdmmc_free_clk>;
 369                                                 clk-gate = <0xC8 5>;
 370                                                 clk-phase = <0 135>;
 371                                         };
 372
 373                                         qspi_clk: qspi_clk {
 374                                                 #clock-cells = <0>;
 375                                                 compatible = "altr,socfpga-a10-gate-clk";
 376                                                 clocks = <&l4_main_clk>;
 377                                                 clk-gate = <0xC8 11>;
 378                                         };
 379
 380                                         nand_x_clk: nand_x_clk {
 381                                                 #clock-cells = <0>;
 382                                                 compatible = "altr,socfpga-a10-gate-clk";
 383                                                 clocks = <&l4_mp_clk>;
 384                                                 clk-gate = <0xC8 10>;
 385                                         };
 386
 387                                         nand_ecc_clk: nand_ecc_clk {
 388                                                 #clock-cells = <0>;
 389                                                 compatible = "altr,socfpga-a10-gate-clk";
 390                                                 clocks = <&nand_x_clk>;
 391                                                 clk-gate = <0xC8 10>;
 392                                         };
 393
 394                                         nand_clk: nand_clk {
 395                                                 #clock-cells = <0>;
 396                                                 compatible = "altr,socfpga-a10-gate-clk";
 397                                                 clocks = <&nand_x_clk>;
 398                                                 fixed-divider = <4>;
 399                                                 clk-gate = <0xC8 10>;
 400                                         };
 401
 402                                         spi_m_clk: spi_m_clk {
 403                                                 #clock-cells = <0>;
 404                                                 compatible = "altr,socfpga-a10-gate-clk";
 405                                                 clocks = <&l4_main_clk>;
 406                                                 clk-gate = <0xC8 9>;
 407                                         };
 408
 409                                         usb_clk: usb_clk {
 410                                                 #clock-cells = <0>;
 411                                                 compatible = "altr,socfpga-a10-gate-clk";
 412                                                 clocks = <&l4_mp_clk>;
 413                                                 clk-gate = <0xC8 8>;
 414                                         };
 415
 416                                         s2f_usr1_clk: s2f_usr1_clk {
 417                                                 #clock-cells = <0>;
 418                                                 compatible = "altr,socfpga-a10-gate-clk";
 419                                                 clocks = <&peri_s2f_usr1_clk>;
 420                                                 clk-gate = <0xC8 6>;
 421                                         };
 422                                 };
 423                 };
 424
 425                 socfpga_axi_setup: stmmac-axi-config {
 426                         snps,wr_osr_lmt = <0xf>;
 427                         snps,rd_osr_lmt = <0xf>;
 428                         snps,blen = <0 0 0 0 16 0 0>;
 429                 };
 430
 431                 gmac0: ethernet@ff800000 {
 432                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 433                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 434                         reg = <0xff800000 0x2000>;
 435                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 436                         interrupt-names = "macirq";
 437                         /* Filled in by bootloader */
 438                         mac-address = [00 00 00 00 00 00];
 439                         snps,multicast-filter-bins = <256>;
 440                         snps,perfect-filter-entries = <128>;
 441                         tx-fifo-depth = <4096>;
 442                         rx-fifo-depth = <16384>;
 443                         clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 444                         clock-names = "stmmaceth", "ptp_ref";
 445                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 446                         reset-names = "stmmaceth", "stmmaceth-ocp";
 447                         snps,axi-config = <&socfpga_axi_setup>;
 448                         status = "disabled";
 449                 };
 450
 451                 gmac1: ethernet@ff802000 {
 452                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 453                         altr,sysmgr-syscon = <&sysmgr 0x48 8>;
 454                         reg = <0xff802000 0x2000>;
 455                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 456                         interrupt-names = "macirq";
 457                         /* Filled in by bootloader */
 458                         mac-address = [00 00 00 00 00 00];
 459                         snps,multicast-filter-bins = <256>;
 460                         snps,perfect-filter-entries = <128>;
 461                         tx-fifo-depth = <4096>;
 462                         rx-fifo-depth = <16384>;
 463                         clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 464                         clock-names = "stmmaceth", "ptp_ref";
 465                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 466                         reset-names = "stmmaceth", "stmmaceth-ocp";
 467                         snps,axi-config = <&socfpga_axi_setup>;
 468                         status = "disabled";
 469                 };
 470
 471                 gmac2: ethernet@ff804000 {
 472                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 473                         altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
 474                         reg = <0xff804000 0x2000>;
 475                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 476                         interrupt-names = "macirq";
 477                         /* Filled in by bootloader */
 478                         mac-address = [00 00 00 00 00 00];
 479                         snps,multicast-filter-bins = <256>;
 480                         snps,perfect-filter-entries = <128>;
 481                         tx-fifo-depth = <4096>;
 482                         rx-fifo-depth = <16384>;
 483                         clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 484                         clock-names = "stmmaceth", "ptp_ref";
 485                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 486                         reset-names = "stmmaceth", "stmmaceth-ocp";
 487                         snps,axi-config = <&socfpga_axi_setup>;
 488                         status = "disabled";
 489                 };
 490
 491                 gpio0: gpio@ffc02900 {
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         compatible = "snps,dw-apb-gpio";
 495                         reg = <0xffc02900 0x100>;
 496                         resets = <&rst GPIO0_RESET>;
 497                         status = "disabled";
 498
 499                         porta: gpio-controller@0 {
 500                                 compatible = "snps,dw-apb-gpio-port";
 501                                 gpio-controller;
 502                                 #gpio-cells = <2>;
 503                                 snps,nr-gpios = <29>;
 504                                 reg = <0>;
 505                                 interrupt-controller;
 506                                 #interrupt-cells = <2>;
 507                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 508                         };
 509                 };
 510
 511                 gpio1: gpio@ffc02a00 {
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                         compatible = "snps,dw-apb-gpio";
 515                         reg = <0xffc02a00 0x100>;
 516                         resets = <&rst GPIO1_RESET>;
 517                         status = "disabled";
 518
 519                         portb: gpio-controller@0 {
 520                                 compatible = "snps,dw-apb-gpio-port";
 521                                 gpio-controller;
 522                                 #gpio-cells = <2>;
 523                                 snps,nr-gpios = <29>;
 524                                 reg = <0>;
 525                                 interrupt-controller;
 526                                 #interrupt-cells = <2>;
 527                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 528                         };
 529                 };
 530
 531                 gpio2: gpio@ffc02b00 {
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                         compatible = "snps,dw-apb-gpio";
 535                         reg = <0xffc02b00 0x100>;
 536                         resets = <&rst GPIO2_RESET>;
 537                         status = "disabled";
 538
 539                         portc: gpio-controller@0 {
 540                                 compatible = "snps,dw-apb-gpio-port";
 541                                 gpio-controller;
 542                                 #gpio-cells = <2>;
 543                                 snps,nr-gpios = <27>;
 544                                 reg = <0>;
 545                                 interrupt-controller;
 546                                 #interrupt-cells = <2>;
 547                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 548                         };
 549                 };
 550
 551                 fpga_mgr: fpga-mgr@ffd03000 {
 552                         compatible = "altr,socfpga-a10-fpga-mgr";
 553                         reg = <0xffd03000 0x100
 554                                0xffcfe400 0x20>;
 555                         clocks = <&l4_mp_clk>;
 556                         resets = <&rst FPGAMGR_RESET>;
 557                         reset-names = "fpgamgr";
 558                 };
 559
 560                 i2c0: i2c@ffc02200 {
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         compatible = "snps,designware-i2c";
 564                         reg = <0xffc02200 0x100>;
 565                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&l4_sp_clk>;
 567                         resets = <&rst I2C0_RESET>;
 568                         status = "disabled";
 569                 };
 570
 571                 i2c1: i2c@ffc02300 {
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         compatible = "snps,designware-i2c";
 575                         reg = <0xffc02300 0x100>;
 576                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&l4_sp_clk>;
 578                         resets = <&rst I2C1_RESET>;
 579                         status = "disabled";
 580                 };
 581
 582                 i2c2: i2c@ffc02400 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         compatible = "snps,designware-i2c";
 586                         reg = <0xffc02400 0x100>;
 587                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&l4_sp_clk>;
 589                         resets = <&rst I2C2_RESET>;
 590                         status = "disabled";
 591                 };
 592
 593                 i2c3: i2c@ffc02500 {
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         compatible = "snps,designware-i2c";
 597                         reg = <0xffc02500 0x100>;
 598                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&l4_sp_clk>;
 600                         resets = <&rst I2C3_RESET>;
 601                         status = "disabled";
 602                 };
 603
 604                 i2c4: i2c@ffc02600 {
 605                         #address-cells = <1>;
 606                         #size-cells = <0>;
 607                         compatible = "snps,designware-i2c";
 608                         reg = <0xffc02600 0x100>;
 609                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&l4_sp_clk>;
 611                         resets = <&rst I2C4_RESET>;
 612                         status = "disabled";
 613                 };
 614
 615                 spi0: spi@ffda4000 {
 616                         compatible = "snps,dw-apb-ssi";
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                         reg = <0xffda4000 0x100>;
 620                         interrupts = <0 101 4>;
 621                         num-cs = <4>;
 622                         /*32bit_access;*/
 623                         clocks = <&spi_m_clk>;
 624                         resets = <&rst SPIM0_RESET>;
 625                         reset-names = "spi";
 626                         status = "disabled";
 627                 };
 628
 629                 spi1: spi@ffda5000 {
 630                         compatible = "snps,dw-apb-ssi";
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         reg = <0xffda5000 0x100>;
 634                         interrupts = <0 102 4>;
 635                         num-cs = <4>;
 636                         /*32bit_access;*/
 637                         tx-dma-channel = <&pdma 16>;
 638                         rx-dma-channel = <&pdma 17>;
 639                         clocks = <&spi_m_clk>;
 640                         resets = <&rst SPIM1_RESET>;
 641                         reset-names = "spi";
 642                         status = "disabled";
 643                 };
 644
 645                 sdr: sdr@ffcfb100 {
 646                         compatible = "altr,sdr-ctl", "syscon";
 647                         reg = <0xffcfb100 0x80>;
 648                 };
 649
 650                 L2: cache-controller@fffff000 {
 651                         compatible = "arm,pl310-cache";
 652                         reg = <0xfffff000 0x1000>;
 653                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 654                         cache-unified;
 655                         cache-level = <2>;
 656                         prefetch-data = <1>;
 657                         prefetch-instr = <1>;
 658                         arm,shared-override;
 659                 };
 660
 661                 mmc: dwmmc0@ff808000 {
 662                         #address-cells = <1>;
 663                         #size-cells = <0>;
 664                         compatible = "altr,socfpga-dw-mshc";
 665                         reg = <0xff808000 0x1000>;
 666                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 667                         fifo-depth = <0x400>;
 668                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 669                         clock-names = "biu", "ciu";
 670                         resets = <&rst SDMMC_RESET>;
 671                         status = "disabled";
 672                 };
 673
 674                 nand: nand@ffb90000 {
 675                         #address-cells = <1>;
 676                         #size-cells = <0>;
 677                         compatible = "altr,socfpga-denali-nand";
 678                         reg = <0xffb90000 0x72000>,
 679                               <0xffb80000 0x10000>;
 680                         reg-names = "nand_data", "denali_reg";
 681                         interrupts = <0 99 4>;
 682                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 683                         clock-names = "nand", "nand_x", "ecc";
 684                         resets = <&rst NAND_RESET>;
 685                         status = "disabled";
 686                 };
 687
 688                 ocram: sram@ffe00000 {
 689                         compatible = "mmio-sram";
 690                         reg = <0xffe00000 0x40000>;
 691                 };
 692
 693                 eccmgr: eccmgr {
 694                         compatible = "altr,socfpga-a10-ecc-manager";
 695                         altr,sysmgr-syscon = <&sysmgr>;
 696                         #address-cells = <1>;
 697                         #size-cells = <1>;
 698                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 700                         interrupt-controller;
 701                         #interrupt-cells = <2>;
 702                         ranges;
 703
 704                         sdramedac {
 705                                 compatible = "altr,sdram-edac-a10";
 706                                 altr,sdr-syscon = <&sdr>;
 707                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
 708                                              <49 IRQ_TYPE_LEVEL_HIGH>;
 709                         };
 710
 711                         l2-ecc@ffd06010 {
 712                                 compatible = "altr,socfpga-a10-l2-ecc";
 713                                 reg = <0xffd06010 0x4>;
 714                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
 715                                              <32 IRQ_TYPE_LEVEL_HIGH>;
 716                         };
 717
 718                         ocram-ecc@ff8c3000 {
 719                                 compatible = "altr,socfpga-a10-ocram-ecc";
 720                                 reg = <0xff8c3000 0x400>;
 721                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 722                                              <33 IRQ_TYPE_LEVEL_HIGH>;
 723                         };
 724
 725                         emac0-rx-ecc@ff8c0800 {
 726                                 compatible = "altr,socfpga-eth-mac-ecc";
 727                                 reg = <0xff8c0800 0x400>;
 728                                 altr,ecc-parent = <&gmac0>;
 729                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 730                                              <36 IRQ_TYPE_LEVEL_HIGH>;
 731                         };
 732
 733                         emac0-tx-ecc@ff8c0c00 {
 734                                 compatible = "altr,socfpga-eth-mac-ecc";
 735                                 reg = <0xff8c0c00 0x400>;
 736                                 altr,ecc-parent = <&gmac0>;
 737                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 738                                              <37 IRQ_TYPE_LEVEL_HIGH>;
 739                         };
 740
 741                         dma-ecc@ff8c8000 {
 742                                 compatible = "altr,socfpga-dma-ecc";
 743                                 reg = <0xff8c8000 0x400>;
 744                                 altr,ecc-parent = <&pdma>;
 745                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
 746                                              <42 IRQ_TYPE_LEVEL_HIGH>;
 747                         };
 748
 749                         usb0-ecc@ff8c8800 {
 750                                 compatible = "altr,socfpga-usb-ecc";
 751                                 reg = <0xff8c8800 0x400>;
 752                                 altr,ecc-parent = <&usb0>;
 753                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
 754                                              <34 IRQ_TYPE_LEVEL_HIGH>;
 755                         };
 756                 };
 757
 758                 qspi: spi@ff809000 {
 759                         compatible = "cdns,qspi-nor";
 760                         #address-cells = <1>;
 761                         #size-cells = <0>;
 762                         reg = <0xff809000 0x100>,
 763                               <0xffa00000 0x100000>;
 764                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 765                         cdns,fifo-depth = <128>;
 766                         cdns,fifo-width = <4>;
 767                         cdns,trigger-address = <0x00000000>;
 768                         clocks = <&qspi_clk>;
 769                         resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
 770                         reset-names = "qspi", "qspi-ocp";
 771                         status = "disabled";
 772                 };
 773
 774                 rst: rstmgr@ffd05000 {
 775                         #reset-cells = <1>;
 776                         compatible = "altr,rst-mgr";
 777                         reg = <0xffd05000 0x100>;
 778                         altr,modrst-offset = <0x20>;
 779                 };
 780
 781                 scu: snoop-control-unit@ffffc000 {
 782                         compatible = "arm,cortex-a9-scu";
 783                         reg = <0xffffc000 0x100>;
 784                 };
 785
 786                 sysmgr: sysmgr@ffd06000 {
 787                         compatible = "altr,sys-mgr", "syscon";
 788                         reg = <0xffd06000 0x300>;
 789                         cpu1-start-addr = <0xffd06230>;
 790                 };
 791
 792                 /* Local timer */
 793                 timer@ffffc600 {
 794                         compatible = "arm,cortex-a9-twd-timer";
 795                         reg = <0xffffc600 0x100>;
 796                         interrupts = <1 13 0xf01>;
 797                         clocks = <&mpu_periph_clk>;
 798                 };
 799
 800                 timer0: timer0@ffc02700 {
 801                         compatible = "snps,dw-apb-timer";
 802                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 803                         reg = <0xffc02700 0x100>;
 804                         clocks = <&l4_sp_clk>;
 805                         clock-names = "timer";
 806                         resets = <&rst SPTIMER0_RESET>;
 807                         reset-names = "timer";
 808                 };
 809
 810                 timer1: timer1@ffc02800 {
 811                         compatible = "snps,dw-apb-timer";
 812                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 813                         reg = <0xffc02800 0x100>;
 814                         clocks = <&l4_sp_clk>;
 815                         clock-names = "timer";
 816                         resets = <&rst SPTIMER1_RESET>;
 817                         reset-names = "timer";
 818                 };
 819
 820                 timer2: timer2@ffd00000 {
 821                         compatible = "snps,dw-apb-timer";
 822                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 823                         reg = <0xffd00000 0x100>;
 824                         clocks = <&l4_sys_free_clk>;
 825                         clock-names = "timer";
 826                         resets = <&rst L4SYSTIMER0_RESET>;
 827                         reset-names = "timer";
 828                 };
 829
 830                 timer3: timer3@ffd00100 {
 831                         compatible = "snps,dw-apb-timer";
 832                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 833                         reg = <0xffd00100 0x100>;
 834                         clocks = <&l4_sys_free_clk>;
 835                         clock-names = "timer";
 836                         resets = <&rst L4SYSTIMER1_RESET>;
 837                         reset-names = "timer";
 838                 };
 839
 840                 uart0: serial0@ffc02000 {
 841                         compatible = "snps,dw-apb-uart";
 842                         reg = <0xffc02000 0x100>;
 843                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 844                         reg-shift = <2>;
 845                         reg-io-width = <4>;
 846                         clocks = <&l4_sp_clk>;
 847                         resets = <&rst UART0_RESET>;
 848                         status = "disabled";
 849                 };
 850
 851                 uart1: serial1@ffc02100 {
 852                         compatible = "snps,dw-apb-uart";
 853                         reg = <0xffc02100 0x100>;
 854                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 855                         reg-shift = <2>;
 856                         reg-io-width = <4>;
 857                         clocks = <&l4_sp_clk>;
 858                         resets = <&rst UART1_RESET>;
 859                         status = "disabled";
 860                 };
 861
 862                 usbphy0: usbphy {
 863                         #phy-cells = <0>;
 864                         compatible = "usb-nop-xceiv";
 865                         status = "okay";
 866                 };
 867
 868                 usb0: usb@ffb00000 {
 869                         compatible = "snps,dwc2";
 870                         reg = <0xffb00000 0xffff>;
 871                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 872                         clocks = <&usb_clk>;
 873                         clock-names = "otg";
 874                         resets = <&rst USB0_RESET>;
 875                         reset-names = "dwc2";
 876                         phys = <&usbphy0>;
 877                         phy-names = "usb2-phy";
 878                         status = "disabled";
 879                 };
 880
 881                 usb1: usb@ffb40000 {
 882                         compatible = "snps,dwc2";
 883                         reg = <0xffb40000 0xffff>;
 884                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 885                         clocks = <&usb_clk>;
 886                         clock-names = "otg";
 887                         resets = <&rst USB1_RESET>;
 888                         reset-names = "dwc2";
 889                         phys = <&usbphy0>;
 890                         phy-names = "usb2-phy";
 891                         status = "disabled";
 892                 };
 893
 894                 watchdog0: watchdog@ffd00200 {
 895                         compatible = "snps,dw-wdt";
 896                         reg = <0xffd00200 0x100>;
 897                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 898                         clocks = <&l4_sys_free_clk>;
 899                         resets = <&rst L4WD0_RESET>;
 900                         status = "disabled";
 901                 };
 902
 903                 watchdog1: watchdog@ffd00300 {
 904                         compatible = "snps,dw-wdt";
 905                         reg = <0xffd00300 0x100>;
 906                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 907                         clocks = <&l4_sys_free_clk>;
 908                         resets = <&rst L4WD1_RESET>;
 909                         status = "disabled";
 910                 };
 911         };
 912 };