1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2014. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9-pmu";
34 interrupt-parent = <&intc>;
35 interrupts = <0 124 4>, <0 125 4>;
36 interrupt-affinity = <&cpu0>, <&cpu1>;
37 reg = <0xff111000 0x1000>,
42 compatible = "arm,cortex-a9-gic";
43 #interrupt-cells = <3>;
45 reg = <0xffffd000 0x1000>,
52 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
58 compatible = "simple-bus";
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
67 <0 84 IRQ_TYPE_LEVEL_HIGH>,
68 <0 85 IRQ_TYPE_LEVEL_HIGH>,
69 <0 86 IRQ_TYPE_LEVEL_HIGH>,
70 <0 87 IRQ_TYPE_LEVEL_HIGH>,
71 <0 88 IRQ_TYPE_LEVEL_HIGH>,
72 <0 89 IRQ_TYPE_LEVEL_HIGH>,
73 <0 90 IRQ_TYPE_LEVEL_HIGH>,
74 <0 91 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&l4_main_clk>;
79 clock-names = "apb_pclk";
80 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
81 reset-names = "dma", "dma-ocp";
86 #address-cells = <0x1>;
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
103 compatible = "fixed-clock";
106 cb_intosc_ls_clk: cb_intosc_ls_clk {
108 compatible = "fixed-clock";
111 f2s_free_clk: f2s_free_clk {
113 compatible = "fixed-clock";
118 compatible = "fixed-clock";
121 main_pll: main_pll@40 {
122 #address-cells = <1>;
125 compatible = "altr,socfpga-a10-pll-clock";
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
130 main_mpu_base_clk: main_mpu_base_clk {
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x140 0 11>;
137 main_noc_base_clk: main_noc_base_clk {
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 div-reg = <0x144 0 11>;
144 main_emaca_clk: main_emaca_clk@68 {
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
151 main_emacb_clk: main_emacb_clk@6c {
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
165 main_gpio_db_clk: main_gpio_db_clk@74 {
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
172 main_sdmmc_clk: main_sdmmc_clk@78 {
174 compatible = "altr,socfpga-a10-perip-clk"
176 clocks = <&main_pll>;
180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
201 main_periph_ref_clk: main_periph_ref_clk@9c {
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
209 periph_pll: periph_pll@c0 {
210 #address-cells = <1>;
213 compatible = "altr,socfpga-a10-pll-clock";
214 clocks = <&osc1>, <&cb_intosc_ls_clk>,
215 <&f2s_free_clk>, <&main_periph_ref_clk>;
218 peri_mpu_base_clk: peri_mpu_base_clk {
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x140 16 11>;
225 peri_noc_base_clk: peri_noc_base_clk {
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 div-reg = <0x144 16 11>;
232 peri_emaca_clk: peri_emaca_clk@e8 {
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
239 peri_emacb_clk: peri_emacb_clk@ec {
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
283 compatible = "altr,socfpga-a10-perip-clk";
284 clocks = <&periph_pll>;
289 mpu_free_clk: mpu_free_clk@60 {
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
298 noc_free_clk: noc_free_clk@64 {
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
316 sdmmc_free_clk: sdmmc_free_clk@f8 {
318 compatible = "altr,socfpga-a10-perip-clk";
319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
320 <&osc1>, <&cb_intosc_hs_div2_clk>,
326 l4_sys_free_clk: l4_sys_free_clk {
328 compatible = "altr,socfpga-a10-perip-clk";
329 clocks = <&noc_free_clk>;
333 l4_main_clk: l4_main_clk {
335 compatible = "altr,socfpga-a10-gate-clk";
336 clocks = <&noc_free_clk>;
337 div-reg = <0xA8 0 2>;
341 l4_mp_clk: l4_mp_clk {
343 compatible = "altr,socfpga-a10-gate-clk";
344 clocks = <&noc_free_clk>;
345 div-reg = <0xA8 8 2>;
349 l4_sp_clk: l4_sp_clk {
351 compatible = "altr,socfpga-a10-gate-clk";
352 clocks = <&noc_free_clk>;
353 div-reg = <0xA8 16 2>;
357 mpu_periph_clk: mpu_periph_clk {
359 compatible = "altr,socfpga-a10-gate-clk";
360 clocks = <&mpu_free_clk>;
365 sdmmc_clk: sdmmc_clk {
367 compatible = "altr,socfpga-a10-gate-clk";
368 clocks = <&sdmmc_free_clk>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_main_clk>;
377 clk-gate = <0xC8 11>;
380 nand_x_clk: nand_x_clk {
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_mp_clk>;
384 clk-gate = <0xC8 10>;
387 nand_ecc_clk: nand_ecc_clk {
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&nand_x_clk>;
391 clk-gate = <0xC8 10>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&nand_x_clk>;
399 clk-gate = <0xC8 10>;
402 spi_m_clk: spi_m_clk {
404 compatible = "altr,socfpga-a10-gate-clk";
405 clocks = <&l4_main_clk>;
411 compatible = "altr,socfpga-a10-gate-clk";
412 clocks = <&l4_mp_clk>;
416 s2f_usr1_clk: s2f_usr1_clk {
418 compatible = "altr,socfpga-a10-gate-clk";
419 clocks = <&peri_s2f_usr1_clk>;
425 socfpga_axi_setup: stmmac-axi-config {
426 snps,wr_osr_lmt = <0xf>;
427 snps,rd_osr_lmt = <0xf>;
428 snps,blen = <0 0 0 0 16 0 0>;
431 gmac0: ethernet@ff800000 {
432 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
433 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
434 reg = <0xff800000 0x2000>;
435 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-names = "macirq";
437 /* Filled in by bootloader */
438 mac-address = [00 00 00 00 00 00];
439 snps,multicast-filter-bins = <256>;
440 snps,perfect-filter-entries = <128>;
441 tx-fifo-depth = <4096>;
442 rx-fifo-depth = <16384>;
443 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
444 clock-names = "stmmaceth", "ptp_ref";
445 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
446 reset-names = "stmmaceth", "stmmaceth-ocp";
447 snps,axi-config = <&socfpga_axi_setup>;
451 gmac1: ethernet@ff802000 {
452 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
453 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
454 reg = <0xff802000 0x2000>;
455 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
456 interrupt-names = "macirq";
457 /* Filled in by bootloader */
458 mac-address = [00 00 00 00 00 00];
459 snps,multicast-filter-bins = <256>;
460 snps,perfect-filter-entries = <128>;
461 tx-fifo-depth = <4096>;
462 rx-fifo-depth = <16384>;
463 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
464 clock-names = "stmmaceth", "ptp_ref";
465 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
466 reset-names = "stmmaceth", "stmmaceth-ocp";
467 snps,axi-config = <&socfpga_axi_setup>;
471 gmac2: ethernet@ff804000 {
472 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
473 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
474 reg = <0xff804000 0x2000>;
475 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "macirq";
477 /* Filled in by bootloader */
478 mac-address = [00 00 00 00 00 00];
479 snps,multicast-filter-bins = <256>;
480 snps,perfect-filter-entries = <128>;
481 tx-fifo-depth = <4096>;
482 rx-fifo-depth = <16384>;
483 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
484 clock-names = "stmmaceth", "ptp_ref";
485 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
486 reset-names = "stmmaceth", "stmmaceth-ocp";
487 snps,axi-config = <&socfpga_axi_setup>;
491 gpio0: gpio@ffc02900 {
492 #address-cells = <1>;
494 compatible = "snps,dw-apb-gpio";
495 reg = <0xffc02900 0x100>;
496 resets = <&rst GPIO0_RESET>;
499 porta: gpio-controller@0 {
500 compatible = "snps,dw-apb-gpio-port";
503 snps,nr-gpios = <29>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
511 gpio1: gpio@ffc02a00 {
512 #address-cells = <1>;
514 compatible = "snps,dw-apb-gpio";
515 reg = <0xffc02a00 0x100>;
516 resets = <&rst GPIO1_RESET>;
519 portb: gpio-controller@0 {
520 compatible = "snps,dw-apb-gpio-port";
523 snps,nr-gpios = <29>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
531 gpio2: gpio@ffc02b00 {
532 #address-cells = <1>;
534 compatible = "snps,dw-apb-gpio";
535 reg = <0xffc02b00 0x100>;
536 resets = <&rst GPIO2_RESET>;
539 portc: gpio-controller@0 {
540 compatible = "snps,dw-apb-gpio-port";
543 snps,nr-gpios = <27>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
551 fpga_mgr: fpga-mgr@ffd03000 {
552 compatible = "altr,socfpga-a10-fpga-mgr";
553 reg = <0xffd03000 0x100
555 clocks = <&l4_mp_clk>;
556 resets = <&rst FPGAMGR_RESET>;
557 reset-names = "fpgamgr";
561 #address-cells = <1>;
563 compatible = "snps,designware-i2c";
564 reg = <0xffc02200 0x100>;
565 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&l4_sp_clk>;
567 resets = <&rst I2C0_RESET>;
572 #address-cells = <1>;
574 compatible = "snps,designware-i2c";
575 reg = <0xffc02300 0x100>;
576 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&l4_sp_clk>;
578 resets = <&rst I2C1_RESET>;
583 #address-cells = <1>;
585 compatible = "snps,designware-i2c";
586 reg = <0xffc02400 0x100>;
587 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&l4_sp_clk>;
589 resets = <&rst I2C2_RESET>;
594 #address-cells = <1>;
596 compatible = "snps,designware-i2c";
597 reg = <0xffc02500 0x100>;
598 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&l4_sp_clk>;
600 resets = <&rst I2C3_RESET>;
605 #address-cells = <1>;
607 compatible = "snps,designware-i2c";
608 reg = <0xffc02600 0x100>;
609 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&l4_sp_clk>;
611 resets = <&rst I2C4_RESET>;
616 compatible = "snps,dw-apb-ssi";
617 #address-cells = <1>;
619 reg = <0xffda4000 0x100>;
620 interrupts = <0 101 4>;
623 clocks = <&spi_m_clk>;
624 resets = <&rst SPIM0_RESET>;
630 compatible = "snps,dw-apb-ssi";
631 #address-cells = <1>;
633 reg = <0xffda5000 0x100>;
634 interrupts = <0 102 4>;
637 tx-dma-channel = <&pdma 16>;
638 rx-dma-channel = <&pdma 17>;
639 clocks = <&spi_m_clk>;
640 resets = <&rst SPIM1_RESET>;
646 compatible = "altr,sdr-ctl", "syscon";
647 reg = <0xffcfb100 0x80>;
650 L2: cache-controller@fffff000 {
651 compatible = "arm,pl310-cache";
652 reg = <0xfffff000 0x1000>;
653 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
657 prefetch-instr = <1>;
661 mmc: dwmmc0@ff808000 {
662 #address-cells = <1>;
664 compatible = "altr,socfpga-dw-mshc";
665 reg = <0xff808000 0x1000>;
666 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
667 fifo-depth = <0x400>;
668 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
669 clock-names = "biu", "ciu";
670 resets = <&rst SDMMC_RESET>;
674 nand: nand@ffb90000 {
675 #address-cells = <1>;
677 compatible = "altr,socfpga-denali-nand";
678 reg = <0xffb90000 0x72000>,
679 <0xffb80000 0x10000>;
680 reg-names = "nand_data", "denali_reg";
681 interrupts = <0 99 4>;
682 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
683 clock-names = "nand", "nand_x", "ecc";
684 resets = <&rst NAND_RESET>;
688 ocram: sram@ffe00000 {
689 compatible = "mmio-sram";
690 reg = <0xffe00000 0x40000>;
694 compatible = "altr,socfpga-a10-ecc-manager";
695 altr,sysmgr-syscon = <&sysmgr>;
696 #address-cells = <1>;
698 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
699 <0 0 IRQ_TYPE_LEVEL_HIGH>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
705 compatible = "altr,sdram-edac-a10";
706 altr,sdr-syscon = <&sdr>;
707 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
708 <49 IRQ_TYPE_LEVEL_HIGH>;
712 compatible = "altr,socfpga-a10-l2-ecc";
713 reg = <0xffd06010 0x4>;
714 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
715 <32 IRQ_TYPE_LEVEL_HIGH>;
719 compatible = "altr,socfpga-a10-ocram-ecc";
720 reg = <0xff8c3000 0x400>;
721 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
722 <33 IRQ_TYPE_LEVEL_HIGH>;
725 emac0-rx-ecc@ff8c0800 {
726 compatible = "altr,socfpga-eth-mac-ecc";
727 reg = <0xff8c0800 0x400>;
728 altr,ecc-parent = <&gmac0>;
729 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
730 <36 IRQ_TYPE_LEVEL_HIGH>;
733 emac0-tx-ecc@ff8c0c00 {
734 compatible = "altr,socfpga-eth-mac-ecc";
735 reg = <0xff8c0c00 0x400>;
736 altr,ecc-parent = <&gmac0>;
737 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
738 <37 IRQ_TYPE_LEVEL_HIGH>;
742 compatible = "altr,socfpga-dma-ecc";
743 reg = <0xff8c8000 0x400>;
744 altr,ecc-parent = <&pdma>;
745 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
746 <42 IRQ_TYPE_LEVEL_HIGH>;
750 compatible = "altr,socfpga-usb-ecc";
751 reg = <0xff8c8800 0x400>;
752 altr,ecc-parent = <&usb0>;
753 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
754 <34 IRQ_TYPE_LEVEL_HIGH>;
759 compatible = "cdns,qspi-nor";
760 #address-cells = <1>;
762 reg = <0xff809000 0x100>,
763 <0xffa00000 0x100000>;
764 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
765 cdns,fifo-depth = <128>;
766 cdns,fifo-width = <4>;
767 cdns,trigger-address = <0x00000000>;
768 clocks = <&qspi_clk>;
769 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
770 reset-names = "qspi", "qspi-ocp";
774 rst: rstmgr@ffd05000 {
776 compatible = "altr,rst-mgr";
777 reg = <0xffd05000 0x100>;
778 altr,modrst-offset = <0x20>;
781 scu: snoop-control-unit@ffffc000 {
782 compatible = "arm,cortex-a9-scu";
783 reg = <0xffffc000 0x100>;
786 sysmgr: sysmgr@ffd06000 {
787 compatible = "altr,sys-mgr", "syscon";
788 reg = <0xffd06000 0x300>;
789 cpu1-start-addr = <0xffd06230>;
794 compatible = "arm,cortex-a9-twd-timer";
795 reg = <0xffffc600 0x100>;
796 interrupts = <1 13 0xf01>;
797 clocks = <&mpu_periph_clk>;
800 timer0: timer0@ffc02700 {
801 compatible = "snps,dw-apb-timer";
802 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0xffc02700 0x100>;
804 clocks = <&l4_sp_clk>;
805 clock-names = "timer";
806 resets = <&rst SPTIMER0_RESET>;
807 reset-names = "timer";
810 timer1: timer1@ffc02800 {
811 compatible = "snps,dw-apb-timer";
812 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
813 reg = <0xffc02800 0x100>;
814 clocks = <&l4_sp_clk>;
815 clock-names = "timer";
816 resets = <&rst SPTIMER1_RESET>;
817 reset-names = "timer";
820 timer2: timer2@ffd00000 {
821 compatible = "snps,dw-apb-timer";
822 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
823 reg = <0xffd00000 0x100>;
824 clocks = <&l4_sys_free_clk>;
825 clock-names = "timer";
826 resets = <&rst L4SYSTIMER0_RESET>;
827 reset-names = "timer";
830 timer3: timer3@ffd00100 {
831 compatible = "snps,dw-apb-timer";
832 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
833 reg = <0xffd00100 0x100>;
834 clocks = <&l4_sys_free_clk>;
835 clock-names = "timer";
836 resets = <&rst L4SYSTIMER1_RESET>;
837 reset-names = "timer";
840 uart0: serial0@ffc02000 {
841 compatible = "snps,dw-apb-uart";
842 reg = <0xffc02000 0x100>;
843 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&l4_sp_clk>;
847 resets = <&rst UART0_RESET>;
851 uart1: serial1@ffc02100 {
852 compatible = "snps,dw-apb-uart";
853 reg = <0xffc02100 0x100>;
854 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&l4_sp_clk>;
858 resets = <&rst UART1_RESET>;
864 compatible = "usb-nop-xceiv";
869 compatible = "snps,dwc2";
870 reg = <0xffb00000 0xffff>;
871 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
874 resets = <&rst USB0_RESET>;
875 reset-names = "dwc2";
877 phy-names = "usb2-phy";
882 compatible = "snps,dwc2";
883 reg = <0xffb40000 0xffff>;
884 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
887 resets = <&rst USB1_RESET>;
888 reset-names = "dwc2";
890 phy-names = "usb2-phy";
894 watchdog0: watchdog@ffd00200 {
895 compatible = "snps,dw-wdt";
896 reg = <0xffd00200 0x100>;
897 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&l4_sys_free_clk>;
899 resets = <&rst L4WD0_RESET>;
903 watchdog1: watchdog@ffd00300 {
904 compatible = "snps,dw-wdt";
905 reg = <0xffd00300 0x100>;
906 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&l4_sys_free_clk>;
908 resets = <&rst L4WD1_RESET>;