1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2014. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
36 reg = <0xffffd000 0x1000>,
43 compatible = "simple-bus";
45 interrupt-parent = <&intc>;
49 compatible = "simple-bus";
55 compatible = "arm,pl330", "arm,primecell";
56 reg = <0xffda1000 0x1000>;
57 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
58 <0 84 IRQ_TYPE_LEVEL_HIGH>,
59 <0 85 IRQ_TYPE_LEVEL_HIGH>,
60 <0 86 IRQ_TYPE_LEVEL_HIGH>,
61 <0 87 IRQ_TYPE_LEVEL_HIGH>,
62 <0 88 IRQ_TYPE_LEVEL_HIGH>,
63 <0 89 IRQ_TYPE_LEVEL_HIGH>,
64 <0 90 IRQ_TYPE_LEVEL_HIGH>,
65 <0 91 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&l4_main_clk>;
70 clock-names = "apb_pclk";
71 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
72 reset-names = "dma", "dma-ocp";
77 #address-cells = <0x1>;
80 compatible = "fpga-region";
81 fpga-mgr = <&fpga_mgr>;
85 compatible = "altr,clk-mgr";
86 reg = <0xffd04000 0x1000>;
92 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
94 compatible = "fixed-clock";
97 cb_intosc_ls_clk: cb_intosc_ls_clk {
99 compatible = "fixed-clock";
102 f2s_free_clk: f2s_free_clk {
104 compatible = "fixed-clock";
109 compatible = "fixed-clock";
112 main_pll: main_pll@40 {
113 #address-cells = <1>;
116 compatible = "altr,socfpga-a10-pll-clock";
117 clocks = <&osc1>, <&cb_intosc_ls_clk>,
121 main_mpu_base_clk: main_mpu_base_clk {
123 compatible = "altr,socfpga-a10-perip-clk";
124 clocks = <&main_pll>;
125 div-reg = <0x140 0 11>;
128 main_noc_base_clk: main_noc_base_clk {
130 compatible = "altr,socfpga-a10-perip-clk";
131 clocks = <&main_pll>;
132 div-reg = <0x144 0 11>;
135 main_emaca_clk: main_emaca_clk@68 {
137 compatible = "altr,socfpga-a10-perip-clk";
138 clocks = <&main_pll>;
142 main_emacb_clk: main_emacb_clk@6c {
144 compatible = "altr,socfpga-a10-perip-clk";
145 clocks = <&main_pll>;
149 main_emac_ptp_clk: main_emac_ptp_clk@70 {
151 compatible = "altr,socfpga-a10-perip-clk";
152 clocks = <&main_pll>;
156 main_gpio_db_clk: main_gpio_db_clk@74 {
158 compatible = "altr,socfpga-a10-perip-clk";
159 clocks = <&main_pll>;
163 main_sdmmc_clk: main_sdmmc_clk@78 {
165 compatible = "altr,socfpga-a10-perip-clk"
167 clocks = <&main_pll>;
171 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
173 compatible = "altr,socfpga-a10-perip-clk";
174 clocks = <&main_pll>;
178 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
180 compatible = "altr,socfpga-a10-perip-clk";
181 clocks = <&main_pll>;
185 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
187 compatible = "altr,socfpga-a10-perip-clk";
188 clocks = <&main_pll>;
192 main_periph_ref_clk: main_periph_ref_clk@9c {
194 compatible = "altr,socfpga-a10-perip-clk";
195 clocks = <&main_pll>;
200 periph_pll: periph_pll@c0 {
201 #address-cells = <1>;
204 compatible = "altr,socfpga-a10-pll-clock";
205 clocks = <&osc1>, <&cb_intosc_ls_clk>,
206 <&f2s_free_clk>, <&main_periph_ref_clk>;
209 peri_mpu_base_clk: peri_mpu_base_clk {
211 compatible = "altr,socfpga-a10-perip-clk";
212 clocks = <&periph_pll>;
213 div-reg = <0x140 16 11>;
216 peri_noc_base_clk: peri_noc_base_clk {
218 compatible = "altr,socfpga-a10-perip-clk";
219 clocks = <&periph_pll>;
220 div-reg = <0x144 16 11>;
223 peri_emaca_clk: peri_emaca_clk@e8 {
225 compatible = "altr,socfpga-a10-perip-clk";
226 clocks = <&periph_pll>;
230 peri_emacb_clk: peri_emacb_clk@ec {
232 compatible = "altr,socfpga-a10-perip-clk";
233 clocks = <&periph_pll>;
237 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
239 compatible = "altr,socfpga-a10-perip-clk";
240 clocks = <&periph_pll>;
244 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
246 compatible = "altr,socfpga-a10-perip-clk";
247 clocks = <&periph_pll>;
251 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
253 compatible = "altr,socfpga-a10-perip-clk";
254 clocks = <&periph_pll>;
258 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
260 compatible = "altr,socfpga-a10-perip-clk";
261 clocks = <&periph_pll>;
265 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
267 compatible = "altr,socfpga-a10-perip-clk";
268 clocks = <&periph_pll>;
272 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
274 compatible = "altr,socfpga-a10-perip-clk";
275 clocks = <&periph_pll>;
280 mpu_free_clk: mpu_free_clk@60 {
282 compatible = "altr,socfpga-a10-perip-clk";
283 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
284 <&osc1>, <&cb_intosc_hs_div2_clk>,
289 noc_free_clk: noc_free_clk@64 {
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
298 s2f_user1_free_clk: s2f_user1_free_clk@104 {
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
307 sdmmc_free_clk: sdmmc_free_clk@f8 {
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
317 l4_sys_free_clk: l4_sys_free_clk {
319 compatible = "altr,socfpga-a10-perip-clk";
320 clocks = <&noc_free_clk>;
324 l4_main_clk: l4_main_clk {
326 compatible = "altr,socfpga-a10-gate-clk";
327 clocks = <&noc_free_clk>;
328 div-reg = <0xA8 0 2>;
332 l4_mp_clk: l4_mp_clk {
334 compatible = "altr,socfpga-a10-gate-clk";
335 clocks = <&noc_free_clk>;
336 div-reg = <0xA8 8 2>;
340 l4_sp_clk: l4_sp_clk {
342 compatible = "altr,socfpga-a10-gate-clk";
343 clocks = <&noc_free_clk>;
344 div-reg = <0xA8 16 2>;
348 mpu_periph_clk: mpu_periph_clk {
350 compatible = "altr,socfpga-a10-gate-clk";
351 clocks = <&mpu_free_clk>;
356 sdmmc_clk: sdmmc_clk {
358 compatible = "altr,socfpga-a10-gate-clk";
359 clocks = <&sdmmc_free_clk>;
366 compatible = "altr,socfpga-a10-gate-clk";
367 clocks = <&l4_main_clk>;
368 clk-gate = <0xC8 11>;
371 nand_x_clk: nand_x_clk {
373 compatible = "altr,socfpga-a10-gate-clk";
374 clocks = <&l4_mp_clk>;
375 clk-gate = <0xC8 10>;
378 nand_ecc_clk: nand_ecc_clk {
380 compatible = "altr,socfpga-a10-gate-clk";
381 clocks = <&nand_x_clk>;
382 clk-gate = <0xC8 10>;
387 compatible = "altr,socfpga-a10-gate-clk";
388 clocks = <&nand_x_clk>;
390 clk-gate = <0xC8 10>;
393 spi_m_clk: spi_m_clk {
395 compatible = "altr,socfpga-a10-gate-clk";
396 clocks = <&l4_main_clk>;
402 compatible = "altr,socfpga-a10-gate-clk";
403 clocks = <&l4_mp_clk>;
407 s2f_usr1_clk: s2f_usr1_clk {
409 compatible = "altr,socfpga-a10-gate-clk";
410 clocks = <&peri_s2f_usr1_clk>;
416 socfpga_axi_setup: stmmac-axi-config {
417 snps,wr_osr_lmt = <0xf>;
418 snps,rd_osr_lmt = <0xf>;
419 snps,blen = <0 0 0 0 16 0 0>;
422 gmac0: ethernet@ff800000 {
423 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
425 reg = <0xff800000 0x2000>;
426 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
434 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
435 clock-names = "stmmaceth", "ptp_ref";
436 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
437 reset-names = "stmmaceth", "stmmaceth-ocp";
438 snps,axi-config = <&socfpga_axi_setup>;
442 gmac1: ethernet@ff802000 {
443 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
444 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
445 reg = <0xff802000 0x2000>;
446 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "macirq";
448 /* Filled in by bootloader */
449 mac-address = [00 00 00 00 00 00];
450 snps,multicast-filter-bins = <256>;
451 snps,perfect-filter-entries = <128>;
452 tx-fifo-depth = <4096>;
453 rx-fifo-depth = <16384>;
454 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
455 clock-names = "stmmaceth", "ptp_ref";
456 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
457 reset-names = "stmmaceth", "stmmaceth-ocp";
458 snps,axi-config = <&socfpga_axi_setup>;
462 gmac2: ethernet@ff804000 {
463 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
464 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
465 reg = <0xff804000 0x2000>;
466 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "macirq";
468 /* Filled in by bootloader */
469 mac-address = [00 00 00 00 00 00];
470 snps,multicast-filter-bins = <256>;
471 snps,perfect-filter-entries = <128>;
472 tx-fifo-depth = <4096>;
473 rx-fifo-depth = <16384>;
474 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
475 clock-names = "stmmaceth", "ptp_ref";
476 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
477 reset-names = "stmmaceth", "stmmaceth-ocp";
478 snps,axi-config = <&socfpga_axi_setup>;
482 gpio0: gpio@ffc02900 {
483 #address-cells = <1>;
485 compatible = "snps,dw-apb-gpio";
486 reg = <0xffc02900 0x100>;
487 resets = <&rst GPIO0_RESET>;
490 porta: gpio-controller@0 {
491 compatible = "snps,dw-apb-gpio-port";
494 snps,nr-gpios = <29>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
502 gpio1: gpio@ffc02a00 {
503 #address-cells = <1>;
505 compatible = "snps,dw-apb-gpio";
506 reg = <0xffc02a00 0x100>;
507 resets = <&rst GPIO1_RESET>;
510 portb: gpio-controller@0 {
511 compatible = "snps,dw-apb-gpio-port";
514 snps,nr-gpios = <29>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
522 gpio2: gpio@ffc02b00 {
523 #address-cells = <1>;
525 compatible = "snps,dw-apb-gpio";
526 reg = <0xffc02b00 0x100>;
527 resets = <&rst GPIO2_RESET>;
530 portc: gpio-controller@0 {
531 compatible = "snps,dw-apb-gpio-port";
534 snps,nr-gpios = <27>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
542 fpga_mgr: fpga-mgr@ffd03000 {
543 compatible = "altr,socfpga-a10-fpga-mgr";
544 reg = <0xffd03000 0x100
546 clocks = <&l4_mp_clk>;
547 resets = <&rst FPGAMGR_RESET>;
548 reset-names = "fpgamgr";
552 #address-cells = <1>;
554 compatible = "snps,designware-i2c";
555 reg = <0xffc02200 0x100>;
556 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&l4_sp_clk>;
558 resets = <&rst I2C0_RESET>;
563 #address-cells = <1>;
565 compatible = "snps,designware-i2c";
566 reg = <0xffc02300 0x100>;
567 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&l4_sp_clk>;
569 resets = <&rst I2C1_RESET>;
574 #address-cells = <1>;
576 compatible = "snps,designware-i2c";
577 reg = <0xffc02400 0x100>;
578 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&l4_sp_clk>;
580 resets = <&rst I2C2_RESET>;
585 #address-cells = <1>;
587 compatible = "snps,designware-i2c";
588 reg = <0xffc02500 0x100>;
589 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&l4_sp_clk>;
591 resets = <&rst I2C3_RESET>;
596 #address-cells = <1>;
598 compatible = "snps,designware-i2c";
599 reg = <0xffc02600 0x100>;
600 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&l4_sp_clk>;
602 resets = <&rst I2C4_RESET>;
607 compatible = "snps,dw-apb-ssi";
608 #address-cells = <1>;
610 reg = <0xffda4000 0x100>;
611 interrupts = <0 101 4>;
614 clocks = <&spi_m_clk>;
615 resets = <&rst SPIM0_RESET>;
621 compatible = "snps,dw-apb-ssi";
622 #address-cells = <1>;
624 reg = <0xffda5000 0x100>;
625 interrupts = <0 102 4>;
628 tx-dma-channel = <&pdma 16>;
629 rx-dma-channel = <&pdma 17>;
630 clocks = <&spi_m_clk>;
631 resets = <&rst SPIM1_RESET>;
637 compatible = "altr,sdr-ctl", "syscon";
638 reg = <0xffcfb100 0x80>;
641 L2: cache-controller@fffff000 {
642 compatible = "arm,pl310-cache";
643 reg = <0xfffff000 0x1000>;
644 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
648 prefetch-instr = <1>;
652 mmc: dwmmc0@ff808000 {
653 #address-cells = <1>;
655 compatible = "altr,socfpga-dw-mshc";
656 reg = <0xff808000 0x1000>;
657 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
658 fifo-depth = <0x400>;
659 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
660 clock-names = "biu", "ciu";
661 resets = <&rst SDMMC_RESET>;
665 nand: nand@ffb90000 {
666 #address-cells = <1>;
668 compatible = "altr,socfpga-denali-nand";
669 reg = <0xffb90000 0x72000>,
670 <0xffb80000 0x10000>;
671 reg-names = "nand_data", "denali_reg";
672 interrupts = <0 99 4>;
673 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
674 clock-names = "nand", "nand_x", "ecc";
675 resets = <&rst NAND_RESET>;
679 ocram: sram@ffe00000 {
680 compatible = "mmio-sram";
681 reg = <0xffe00000 0x40000>;
685 compatible = "altr,socfpga-a10-ecc-manager";
686 altr,sysmgr-syscon = <&sysmgr>;
687 #address-cells = <1>;
689 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
690 <0 0 IRQ_TYPE_LEVEL_HIGH>;
691 interrupt-controller;
692 #interrupt-cells = <2>;
696 compatible = "altr,sdram-edac-a10";
697 altr,sdr-syscon = <&sdr>;
698 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
699 <49 IRQ_TYPE_LEVEL_HIGH>;
703 compatible = "altr,socfpga-a10-l2-ecc";
704 reg = <0xffd06010 0x4>;
705 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
706 <32 IRQ_TYPE_LEVEL_HIGH>;
710 compatible = "altr,socfpga-a10-ocram-ecc";
711 reg = <0xff8c3000 0x400>;
712 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
713 <33 IRQ_TYPE_LEVEL_HIGH>;
716 emac0-rx-ecc@ff8c0800 {
717 compatible = "altr,socfpga-eth-mac-ecc";
718 reg = <0xff8c0800 0x400>;
719 altr,ecc-parent = <&gmac0>;
720 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
721 <36 IRQ_TYPE_LEVEL_HIGH>;
724 emac0-tx-ecc@ff8c0c00 {
725 compatible = "altr,socfpga-eth-mac-ecc";
726 reg = <0xff8c0c00 0x400>;
727 altr,ecc-parent = <&gmac0>;
728 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
729 <37 IRQ_TYPE_LEVEL_HIGH>;
733 compatible = "altr,socfpga-dma-ecc";
734 reg = <0xff8c8000 0x400>;
735 altr,ecc-parent = <&pdma>;
736 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
737 <42 IRQ_TYPE_LEVEL_HIGH>;
741 compatible = "altr,socfpga-usb-ecc";
742 reg = <0xff8c8800 0x400>;
743 altr,ecc-parent = <&usb0>;
744 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
745 <34 IRQ_TYPE_LEVEL_HIGH>;
750 compatible = "cdns,qspi-nor";
751 #address-cells = <1>;
753 reg = <0xff809000 0x100>,
754 <0xffa00000 0x100000>;
755 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
756 cdns,fifo-depth = <128>;
757 cdns,fifo-width = <4>;
758 cdns,trigger-address = <0x00000000>;
759 clocks = <&qspi_clk>;
760 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
761 reset-names = "qspi", "qspi-ocp";
765 rst: rstmgr@ffd05000 {
767 compatible = "altr,rst-mgr";
768 reg = <0xffd05000 0x100>;
769 altr,modrst-offset = <0x20>;
772 scu: snoop-control-unit@ffffc000 {
773 compatible = "arm,cortex-a9-scu";
774 reg = <0xffffc000 0x100>;
777 sysmgr: sysmgr@ffd06000 {
778 compatible = "altr,sys-mgr", "syscon";
779 reg = <0xffd06000 0x300>;
780 cpu1-start-addr = <0xffd06230>;
785 compatible = "arm,cortex-a9-twd-timer";
786 reg = <0xffffc600 0x100>;
787 interrupts = <1 13 0xf01>;
788 clocks = <&mpu_periph_clk>;
791 timer0: timer0@ffc02700 {
792 compatible = "snps,dw-apb-timer";
793 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
794 reg = <0xffc02700 0x100>;
795 clocks = <&l4_sp_clk>;
796 clock-names = "timer";
797 resets = <&rst SPTIMER0_RESET>;
798 reset-names = "timer";
801 timer1: timer1@ffc02800 {
802 compatible = "snps,dw-apb-timer";
803 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
804 reg = <0xffc02800 0x100>;
805 clocks = <&l4_sp_clk>;
806 clock-names = "timer";
807 resets = <&rst SPTIMER1_RESET>;
808 reset-names = "timer";
811 timer2: timer2@ffd00000 {
812 compatible = "snps,dw-apb-timer";
813 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
814 reg = <0xffd00000 0x100>;
815 clocks = <&l4_sys_free_clk>;
816 clock-names = "timer";
817 resets = <&rst L4SYSTIMER0_RESET>;
818 reset-names = "timer";
821 timer3: timer3@ffd00100 {
822 compatible = "snps,dw-apb-timer";
823 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0xffd00100 0x100>;
825 clocks = <&l4_sys_free_clk>;
826 clock-names = "timer";
827 resets = <&rst L4SYSTIMER1_RESET>;
828 reset-names = "timer";
831 uart0: serial0@ffc02000 {
832 compatible = "snps,dw-apb-uart";
833 reg = <0xffc02000 0x100>;
834 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&l4_sp_clk>;
838 resets = <&rst UART0_RESET>;
842 uart1: serial1@ffc02100 {
843 compatible = "snps,dw-apb-uart";
844 reg = <0xffc02100 0x100>;
845 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&l4_sp_clk>;
849 resets = <&rst UART1_RESET>;
855 compatible = "usb-nop-xceiv";
860 compatible = "snps,dwc2";
861 reg = <0xffb00000 0xffff>;
862 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
865 resets = <&rst USB0_RESET>;
866 reset-names = "dwc2";
868 phy-names = "usb2-phy";
873 compatible = "snps,dwc2";
874 reg = <0xffb40000 0xffff>;
875 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
878 resets = <&rst USB1_RESET>;
879 reset-names = "dwc2";
881 phy-names = "usb2-phy";
885 watchdog0: watchdog@ffd00200 {
886 compatible = "snps,dw-wdt";
887 reg = <0xffd00200 0x100>;
888 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&l4_sys_free_clk>;
890 resets = <&rst L4WD0_RESET>;
894 watchdog1: watchdog@ffd00300 {
895 compatible = "snps,dw-wdt";
896 reg = <0xffd00300 0x100>;
897 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&l4_sys_free_clk>;
899 resets = <&rst L4WD1_RESET>;