1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
17 model = "Atmel SAMA5D2 family SoC";
18 compatible = "atmel,sama5d2";
19 interrupt-parent = <&aic>;
32 compatible = "arm,cortex-a5";
34 next-level-cache = <&L2>;
39 compatible = "arm,cortex-a5-pmu";
40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
44 compatible = "arm,coresight-etb10", "arm,primecell";
45 reg = <0x740000 0x1000>;
47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
48 clock-names = "apb_pclk";
53 remote-endpoint = <&etm_out>;
60 compatible = "arm,coresight-etm3x", "arm,primecell";
61 reg = <0x73C000 0x1000>;
63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
64 clock-names = "apb_pclk";
69 remote-endpoint = <&etb_in>;
76 device_type = "memory";
77 reg = <0x20000000 0x20000000>;
81 slow_xtal: slow_xtal {
82 compatible = "fixed-clock";
84 clock-frequency = <0>;
87 main_xtal: main_xtal {
88 compatible = "fixed-clock";
90 clock-frequency = <0>;
94 ns_sram: sram@200000 {
95 compatible = "mmio-sram";
96 reg = <0x00200000 0x20000>;
99 ranges = <0 0x00200000 0x20000>;
103 compatible = "simple-bus";
104 #address-cells = <1>;
108 nfc_sram: sram@100000 {
109 compatible = "mmio-sram";
111 reg = <0x00100000 0x2400>;
112 #address-cells = <1>;
114 ranges = <0 0x00100000 0x2400>;
118 usb0: gadget@300000 {
119 compatible = "atmel,sama5d3-udc";
120 reg = <0x00300000 0x100000
122 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
123 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
124 clock-names = "pclk", "hclk";
129 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
130 reg = <0x00400000 0x100000>;
131 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
133 clock-names = "ohci_clk", "hclk", "uhpck";
138 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
139 reg = <0x00500000 0x100000>;
140 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
141 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
142 clock-names = "usb_clk", "ehci_clk";
146 L2: cache-controller@a00000 {
147 compatible = "arm,pl310-cache";
148 reg = <0x00a00000 0x1000>;
149 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
155 compatible = "atmel,sama5d3-ebi";
156 #address-cells = <2>;
159 reg = <0x10000000 0x10000000
160 0x60000000 0x30000000>;
161 ranges = <0x0 0x0 0x10000000 0x10000000
162 0x1 0x0 0x60000000 0x10000000
163 0x2 0x0 0x70000000 0x10000000
164 0x3 0x0 0x80000000 0x10000000>;
165 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
168 nand_controller: nand-controller {
169 compatible = "atmel,sama5d3-nand-controller";
170 atmel,nfc-sram = <&nfc_sram>;
171 atmel,nfc-io = <&nfc_io>;
172 ecc-engine = <&pmecc>;
173 #address-cells = <2>;
180 sdmmc0: sdio-host@a0000000 {
181 compatible = "atmel,sama5d2-sdhci";
182 reg = <0xa0000000 0x300>;
183 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
184 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
185 clock-names = "hclock", "multclk", "baseclk";
186 assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
187 assigned-clock-rates = <480000000>;
191 sdmmc1: sdio-host@b0000000 {
192 compatible = "atmel,sama5d2-sdhci";
193 reg = <0xb0000000 0x300>;
194 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
195 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
196 clock-names = "hclock", "multclk", "baseclk";
197 assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
198 assigned-clock-rates = <480000000>;
202 nfc_io: nfc-io@c0000000 {
203 compatible = "atmel,sama5d3-nfc-io", "syscon";
204 reg = <0xc0000000 0x8000000>;
208 compatible = "simple-bus";
209 #address-cells = <1>;
213 hlcdc: hlcdc@f0000000 {
214 compatible = "atmel,sama5d2-hlcdc";
215 reg = <0xf0000000 0x2000>;
216 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
217 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
218 clock-names = "periph_clk","sys_clk", "slow_clk";
221 hlcdc-display-controller {
222 compatible = "atmel,hlcdc-display-controller";
223 #address-cells = <1>;
227 #address-cells = <1>;
233 hlcdc_pwm: hlcdc-pwm {
234 compatible = "atmel,hlcdc-pwm";
240 compatible = "atmel,sama5d2-isc";
241 reg = <0xf0008000 0x4000>;
242 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
243 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
244 clock-names = "hclock", "iscck", "gck";
246 clock-output-names = "isc-mck";
250 ramc0: ramc@f000c000 {
251 compatible = "atmel,sama5d3-ddramc";
252 reg = <0xf000c000 0x200>;
253 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
254 clock-names = "ddrck", "mpddr";
257 dma0: dma-controller@f0010000 {
258 compatible = "atmel,sama5d4-dma";
259 reg = <0xf0010000 0x1000>;
260 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
262 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
263 clock-names = "dma_clk";
266 /* Place dma1 here despite its address */
267 dma1: dma-controller@f0004000 {
268 compatible = "atmel,sama5d4-dma";
269 reg = <0xf0004000 0x1000>;
270 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
272 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
273 clock-names = "dma_clk";
277 compatible = "atmel,sama5d2-pmc", "syscon";
278 reg = <0xf0014000 0x160>;
279 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
281 clocks = <&clk32k>, <&main_xtal>;
282 clock-names = "slow_clk", "main_xtal";
285 qspi0: spi@f0020000 {
286 compatible = "atmel,sama5d2-qspi";
287 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
288 reg-names = "qspi_base", "qspi_mmap";
289 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
290 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
291 #address-cells = <1>;
296 qspi1: spi@f0024000 {
297 compatible = "atmel,sama5d2-qspi";
298 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
299 reg-names = "qspi_base", "qspi_mmap";
300 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
301 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
302 #address-cells = <1>;
308 compatible = "atmel,at91sam9g46-sha";
309 reg = <0xf0028000 0x100>;
310 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
312 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
313 AT91_XDMAC_DT_PERID(30))>;
315 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
316 clock-names = "sha_clk";
321 compatible = "atmel,at91sam9g46-aes";
322 reg = <0xf002c000 0x100>;
323 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
326 AT91_XDMAC_DT_PERID(26))>,
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
329 AT91_XDMAC_DT_PERID(27))>;
330 dma-names = "tx", "rx";
331 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
332 clock-names = "aes_clk";
337 compatible = "atmel,at91rm9200-spi";
338 reg = <0xf8000000 0x100>;
339 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
341 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
342 AT91_XDMAC_DT_PERID(6))>,
344 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
345 AT91_XDMAC_DT_PERID(7))>;
346 dma-names = "tx", "rx";
347 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
348 clock-names = "spi_clk";
349 atmel,fifo-size = <16>;
350 #address-cells = <1>;
356 compatible = "atmel,at91sam9g45-ssc";
357 reg = <0xf8004000 0x4000>;
358 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
361 AT91_XDMAC_DT_PERID(21))>,
363 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
364 AT91_XDMAC_DT_PERID(22))>;
365 dma-names = "tx", "rx";
366 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
367 clock-names = "pclk";
371 macb0: ethernet@f8008000 {
372 compatible = "atmel,sama5d2-gem";
373 reg = <0xf8008000 0x1000>;
374 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
375 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
376 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
377 #address-cells = <1>;
379 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
380 clock-names = "hclk", "pclk";
384 tcb0: timer@f800c000 {
385 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
386 #address-cells = <1>;
388 reg = <0xf800c000 0x100>;
389 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
390 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
391 clock-names = "t0_clk", "gclk", "slow_clk";
394 tcb1: timer@f8010000 {
395 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
396 #address-cells = <1>;
398 reg = <0xf8010000 0x100>;
399 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
400 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
401 clock-names = "t0_clk", "gclk", "slow_clk";
404 hsmc: hsmc@f8014000 {
405 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
406 reg = <0xf8014000 0x1000>;
407 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
408 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
409 #address-cells = <1>;
413 pmecc: ecc-engine@f8014070 {
414 compatible = "atmel,sama5d2-pmecc";
415 reg = <0xf8014070 0x490>,
420 pdmic: pdmic@f8018000 {
421 compatible = "atmel,sama5d2-pdmic";
422 reg = <0xf8018000 0x124>;
423 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
425 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
426 | AT91_XDMAC_DT_PERID(50))>;
428 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
429 clock-names = "pclk", "gclk";
433 uart0: serial@f801c000 {
434 compatible = "atmel,at91sam9260-usart";
435 reg = <0xf801c000 0x100>;
436 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
438 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
439 AT91_XDMAC_DT_PERID(35))>,
441 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
442 AT91_XDMAC_DT_PERID(36))>;
443 dma-names = "tx", "rx";
444 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
445 clock-names = "usart";
449 uart1: serial@f8020000 {
450 compatible = "atmel,at91sam9260-usart";
451 reg = <0xf8020000 0x100>;
452 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
454 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
455 AT91_XDMAC_DT_PERID(37))>,
457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
458 AT91_XDMAC_DT_PERID(38))>;
459 dma-names = "tx", "rx";
460 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
461 clock-names = "usart";
465 uart2: serial@f8024000 {
466 compatible = "atmel,at91sam9260-usart";
467 reg = <0xf8024000 0x100>;
468 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
470 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
471 AT91_XDMAC_DT_PERID(39))>,
473 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
474 AT91_XDMAC_DT_PERID(40))>;
475 dma-names = "tx", "rx";
476 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
477 clock-names = "usart";
482 compatible = "atmel,sama5d2-i2c";
483 reg = <0xf8028000 0x100>;
484 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
486 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
487 AT91_XDMAC_DT_PERID(0))>,
489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
490 AT91_XDMAC_DT_PERID(1))>;
491 dma-names = "tx", "rx";
492 #address-cells = <1>;
494 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
495 atmel,fifo-size = <16>;
500 compatible = "atmel,sama5d2-pwm";
501 reg = <0xf802c000 0x4000>;
502 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
504 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
509 compatible = "atmel,sama5d2-sfr", "syscon";
510 reg = <0xf8030000 0x98>;
513 flx0: flexcom@f8034000 {
514 compatible = "atmel,sama5d2-flexcom";
515 reg = <0xf8034000 0x200>;
516 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
517 #address-cells = <1>;
519 ranges = <0x0 0xf8034000 0x800>;
523 compatible = "atmel,at91sam9260-usart";
525 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
526 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
527 clock-names = "usart";
529 (AT91_XDMAC_DT_MEM_IF(0) |
530 AT91_XDMAC_DT_PER_IF(1) |
531 AT91_XDMAC_DT_PERID(11))>,
533 (AT91_XDMAC_DT_MEM_IF(0) |
534 AT91_XDMAC_DT_PER_IF(1) |
535 AT91_XDMAC_DT_PERID(12))>;
536 dma-names = "tx", "rx";
537 atmel,fifo-size = <32>;
542 compatible = "atmel,at91rm9200-spi";
544 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
545 #address-cells = <1>;
547 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
548 clock-names = "spi_clk";
550 (AT91_XDMAC_DT_MEM_IF(0) |
551 AT91_XDMAC_DT_PER_IF(1) |
552 AT91_XDMAC_DT_PERID(11))>,
554 (AT91_XDMAC_DT_MEM_IF(0) |
555 AT91_XDMAC_DT_PER_IF(1) |
556 AT91_XDMAC_DT_PERID(12))>;
557 dma-names = "tx", "rx";
558 atmel,fifo-size = <16>;
563 compatible = "atmel,sama5d2-i2c";
565 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
566 #address-cells = <1>;
568 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
570 (AT91_XDMAC_DT_MEM_IF(0) |
571 AT91_XDMAC_DT_PER_IF(1) |
572 AT91_XDMAC_DT_PERID(11))>,
574 (AT91_XDMAC_DT_MEM_IF(0) |
575 AT91_XDMAC_DT_PER_IF(1) |
576 AT91_XDMAC_DT_PERID(12))>;
577 dma-names = "tx", "rx";
578 atmel,fifo-size = <16>;
583 flx1: flexcom@f8038000 {
584 compatible = "atmel,sama5d2-flexcom";
585 reg = <0xf8038000 0x200>;
586 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
587 #address-cells = <1>;
589 ranges = <0x0 0xf8038000 0x800>;
593 compatible = "atmel,at91sam9260-usart";
595 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
596 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
597 clock-names = "usart";
599 (AT91_XDMAC_DT_MEM_IF(0) |
600 AT91_XDMAC_DT_PER_IF(1) |
601 AT91_XDMAC_DT_PERID(13))>,
603 (AT91_XDMAC_DT_MEM_IF(0) |
604 AT91_XDMAC_DT_PER_IF(1) |
605 AT91_XDMAC_DT_PERID(14))>;
606 dma-names = "tx", "rx";
607 atmel,fifo-size = <32>;
612 compatible = "atmel,at91rm9200-spi";
614 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
615 #address-cells = <1>;
617 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
618 clock-names = "spi_clk";
620 (AT91_XDMAC_DT_MEM_IF(0) |
621 AT91_XDMAC_DT_PER_IF(1) |
622 AT91_XDMAC_DT_PERID(13))>,
624 (AT91_XDMAC_DT_MEM_IF(0) |
625 AT91_XDMAC_DT_PER_IF(1) |
626 AT91_XDMAC_DT_PERID(14))>;
627 dma-names = "tx", "rx";
628 atmel,fifo-size = <16>;
633 compatible = "atmel,sama5d2-i2c";
635 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
636 #address-cells = <1>;
638 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
640 (AT91_XDMAC_DT_MEM_IF(0) |
641 AT91_XDMAC_DT_PER_IF(1) |
642 AT91_XDMAC_DT_PERID(13))>,
644 (AT91_XDMAC_DT_MEM_IF(0) |
645 AT91_XDMAC_DT_PER_IF(1) |
646 AT91_XDMAC_DT_PERID(14))>;
647 dma-names = "tx", "rx";
648 atmel,fifo-size = <16>;
653 securam: sram@f8044000 {
654 compatible = "atmel,sama5d2-securam", "mmio-sram";
655 reg = <0xf8044000 0x1420>;
656 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
657 #address-cells = <1>;
659 ranges = <0 0xf8044000 0x1420>;
662 reset_controller: rstc@f8048000 {
663 compatible = "atmel,sama5d3-rstc";
664 reg = <0xf8048000 0x10>;
668 shutdown_controller: shdwc@f8048010 {
669 compatible = "atmel,sama5d2-shdwc";
670 reg = <0xf8048010 0x10>;
672 #address-cells = <1>;
674 atmel,wakeup-rtc-timer;
677 pit: timer@f8048030 {
678 compatible = "atmel,at91sam9260-pit";
679 reg = <0xf8048030 0x10>;
680 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
681 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
684 watchdog: watchdog@f8048040 {
685 compatible = "atmel,sama5d4-wdt";
686 reg = <0xf8048040 0x10>;
687 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
692 clk32k: sckc@f8048050 {
693 compatible = "atmel,sama5d4-sckc";
694 reg = <0xf8048050 0x4>;
696 clocks = <&slow_xtal>;
701 compatible = "atmel,sama5d2-rtc";
702 reg = <0xf80480b0 0x30>;
703 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
708 compatible = "atmel,sama5d2-i2s";
709 reg = <0xf8050000 0x100>;
710 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
712 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
713 AT91_XDMAC_DT_PERID(31))>,
715 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
716 AT91_XDMAC_DT_PERID(32))>;
717 dma-names = "tx", "rx";
718 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
719 clock-names = "pclk", "gclk";
720 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
721 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
726 compatible = "bosch,m_can";
727 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
728 reg-names = "m_can", "message_ram";
729 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
730 <64 IRQ_TYPE_LEVEL_HIGH 7>;
731 interrupt-names = "int0", "int1";
732 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
733 clock-names = "hclk", "cclk";
734 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
735 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
736 assigned-clock-rates = <40000000>;
737 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
742 compatible = "atmel,at91rm9200-spi";
743 reg = <0xfc000000 0x100>;
744 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
746 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
747 AT91_XDMAC_DT_PERID(8))>,
749 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
750 AT91_XDMAC_DT_PERID(9))>;
751 dma-names = "tx", "rx";
752 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
753 clock-names = "spi_clk";
754 atmel,fifo-size = <16>;
755 #address-cells = <1>;
760 uart3: serial@fc008000 {
761 compatible = "atmel,at91sam9260-usart";
762 reg = <0xfc008000 0x100>;
763 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
765 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
766 AT91_XDMAC_DT_PERID(41))>,
768 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
769 AT91_XDMAC_DT_PERID(42))>;
770 dma-names = "tx", "rx";
771 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
772 clock-names = "usart";
776 uart4: serial@fc00c000 {
777 compatible = "atmel,at91sam9260-usart";
778 reg = <0xfc00c000 0x100>;
780 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
781 AT91_XDMAC_DT_PERID(43))>,
783 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
784 AT91_XDMAC_DT_PERID(44))>;
785 dma-names = "tx", "rx";
786 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
787 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
788 clock-names = "usart";
792 flx2: flexcom@fc010000 {
793 compatible = "atmel,sama5d2-flexcom";
794 reg = <0xfc010000 0x200>;
795 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
796 #address-cells = <1>;
798 ranges = <0x0 0xfc010000 0x800>;
802 compatible = "atmel,at91sam9260-usart";
804 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
805 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
806 clock-names = "usart";
808 (AT91_XDMAC_DT_MEM_IF(0) |
809 AT91_XDMAC_DT_PER_IF(1) |
810 AT91_XDMAC_DT_PERID(15))>,
812 (AT91_XDMAC_DT_MEM_IF(0) |
813 AT91_XDMAC_DT_PER_IF(1) |
814 AT91_XDMAC_DT_PERID(16))>;
815 dma-names = "tx", "rx";
816 atmel,fifo-size = <32>;
821 compatible = "atmel,at91rm9200-spi";
823 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
824 #address-cells = <1>;
826 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
827 clock-names = "spi_clk";
829 (AT91_XDMAC_DT_MEM_IF(0) |
830 AT91_XDMAC_DT_PER_IF(1) |
831 AT91_XDMAC_DT_PERID(15))>,
833 (AT91_XDMAC_DT_MEM_IF(0) |
834 AT91_XDMAC_DT_PER_IF(1) |
835 AT91_XDMAC_DT_PERID(16))>;
836 dma-names = "tx", "rx";
837 atmel,fifo-size = <16>;
842 compatible = "atmel,sama5d2-i2c";
844 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
845 #address-cells = <1>;
847 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
849 (AT91_XDMAC_DT_MEM_IF(0) |
850 AT91_XDMAC_DT_PER_IF(1) |
851 AT91_XDMAC_DT_PERID(15))>,
853 (AT91_XDMAC_DT_MEM_IF(0) |
854 AT91_XDMAC_DT_PER_IF(1) |
855 AT91_XDMAC_DT_PERID(16))>;
856 dma-names = "tx", "rx";
857 atmel,fifo-size = <16>;
862 flx3: flexcom@fc014000 {
863 compatible = "atmel,sama5d2-flexcom";
864 reg = <0xfc014000 0x200>;
865 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
866 #address-cells = <1>;
868 ranges = <0x0 0xfc014000 0x800>;
872 compatible = "atmel,at91sam9260-usart";
874 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
875 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
876 clock-names = "usart";
878 (AT91_XDMAC_DT_MEM_IF(0) |
879 AT91_XDMAC_DT_PER_IF(1) |
880 AT91_XDMAC_DT_PERID(17))>,
882 (AT91_XDMAC_DT_MEM_IF(0) |
883 AT91_XDMAC_DT_PER_IF(1) |
884 AT91_XDMAC_DT_PERID(18))>;
885 dma-names = "tx", "rx";
886 atmel,fifo-size = <32>;
891 compatible = "atmel,at91rm9200-spi";
893 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
894 #address-cells = <1>;
896 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
897 clock-names = "spi_clk";
899 (AT91_XDMAC_DT_MEM_IF(0) |
900 AT91_XDMAC_DT_PER_IF(1) |
901 AT91_XDMAC_DT_PERID(17))>,
903 (AT91_XDMAC_DT_MEM_IF(0) |
904 AT91_XDMAC_DT_PER_IF(1) |
905 AT91_XDMAC_DT_PERID(18))>;
906 dma-names = "tx", "rx";
907 atmel,fifo-size = <16>;
912 compatible = "atmel,sama5d2-i2c";
914 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
915 #address-cells = <1>;
917 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
919 (AT91_XDMAC_DT_MEM_IF(0) |
920 AT91_XDMAC_DT_PER_IF(1) |
921 AT91_XDMAC_DT_PERID(17))>,
923 (AT91_XDMAC_DT_MEM_IF(0) |
924 AT91_XDMAC_DT_PER_IF(1) |
925 AT91_XDMAC_DT_PERID(18))>;
926 dma-names = "tx", "rx";
927 atmel,fifo-size = <16>;
933 flx4: flexcom@fc018000 {
934 compatible = "atmel,sama5d2-flexcom";
935 reg = <0xfc018000 0x200>;
936 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
937 #address-cells = <1>;
939 ranges = <0x0 0xfc018000 0x800>;
943 compatible = "atmel,at91sam9260-usart";
945 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
946 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
947 clock-names = "usart";
949 (AT91_XDMAC_DT_MEM_IF(0) |
950 AT91_XDMAC_DT_PER_IF(1) |
951 AT91_XDMAC_DT_PERID(19))>,
953 (AT91_XDMAC_DT_MEM_IF(0) |
954 AT91_XDMAC_DT_PER_IF(1) |
955 AT91_XDMAC_DT_PERID(20))>;
956 dma-names = "tx", "rx";
957 atmel,fifo-size = <32>;
962 compatible = "atmel,at91rm9200-spi";
964 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
965 #address-cells = <1>;
967 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
968 clock-names = "spi_clk";
970 (AT91_XDMAC_DT_MEM_IF(0) |
971 AT91_XDMAC_DT_PER_IF(1) |
972 AT91_XDMAC_DT_PERID(19))>,
974 (AT91_XDMAC_DT_MEM_IF(0) |
975 AT91_XDMAC_DT_PER_IF(1) |
976 AT91_XDMAC_DT_PERID(20))>;
977 dma-names = "tx", "rx";
978 atmel,fifo-size = <16>;
983 compatible = "atmel,sama5d2-i2c";
985 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
986 #address-cells = <1>;
988 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
990 (AT91_XDMAC_DT_MEM_IF(0) |
991 AT91_XDMAC_DT_PER_IF(1) |
992 AT91_XDMAC_DT_PERID(19))>,
994 (AT91_XDMAC_DT_MEM_IF(0) |
995 AT91_XDMAC_DT_PER_IF(1) |
996 AT91_XDMAC_DT_PERID(20))>;
997 dma-names = "tx", "rx";
998 atmel,fifo-size = <16>;
1004 compatible = "atmel,at91sam9g45-trng";
1005 reg = <0xfc01c000 0x100>;
1006 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1007 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
1010 aic: interrupt-controller@fc020000 {
1011 #interrupt-cells = <3>;
1012 compatible = "atmel,sama5d2-aic";
1013 interrupt-controller;
1014 reg = <0xfc020000 0x200>;
1015 atmel,external-irqs = <49>;
1018 i2c1: i2c@fc028000 {
1019 compatible = "atmel,sama5d2-i2c";
1020 reg = <0xfc028000 0x100>;
1021 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1023 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1024 AT91_XDMAC_DT_PERID(2))>,
1026 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1027 AT91_XDMAC_DT_PERID(3))>;
1028 dma-names = "tx", "rx";
1029 #address-cells = <1>;
1031 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
1032 atmel,fifo-size = <16>;
1033 status = "disabled";
1037 compatible = "atmel,sama5d2-adc";
1038 reg = <0xfc030000 0x100>;
1039 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1040 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
1041 clock-names = "adc_clk";
1042 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1044 atmel,min-sample-rate-hz = <200000>;
1045 atmel,max-sample-rate-hz = <20000000>;
1046 atmel,startup-time-ms = <4>;
1047 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1048 #io-channel-cells = <1>;
1049 status = "disabled";
1052 resistive_touch: resistive-touch {
1053 compatible = "resistive-adc-touch";
1054 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
1055 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
1056 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
1057 io-channel-names = "x", "y", "pressure";
1058 touchscreen-min-pressure = <50000>;
1059 status = "disabled";
1062 pioA: pinctrl@fc038000 {
1063 compatible = "atmel,sama5d2-pinctrl";
1064 reg = <0xfc038000 0x600>;
1065 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1066 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1067 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1068 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1069 interrupt-controller;
1070 #interrupt-cells = <2>;
1073 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1076 pioBU: secumod@fc040000 {
1077 compatible = "atmel,sama5d2-secumod", "syscon";
1078 reg = <0xfc040000 0x100>;
1085 compatible = "atmel,at91sam9g46-tdes";
1086 reg = <0xfc044000 0x100>;
1087 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1089 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1090 AT91_XDMAC_DT_PERID(28))>,
1092 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1093 AT91_XDMAC_DT_PERID(29))>;
1094 dma-names = "tx", "rx";
1095 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
1096 clock-names = "tdes_clk";
1100 classd: classd@fc048000 {
1101 compatible = "atmel,sama5d2-classd";
1102 reg = <0xfc048000 0x100>;
1103 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1105 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1106 AT91_XDMAC_DT_PERID(47))>;
1108 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
1109 clock-names = "pclk", "gclk";
1110 status = "disabled";
1113 i2s1: i2s@fc04c000 {
1114 compatible = "atmel,sama5d2-i2s";
1115 reg = <0xfc04c000 0x100>;
1116 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1118 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1119 AT91_XDMAC_DT_PERID(33))>,
1121 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1122 AT91_XDMAC_DT_PERID(34))>;
1123 dma-names = "tx", "rx";
1124 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
1125 clock-names = "pclk", "gclk";
1126 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
1127 assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
1128 status = "disabled";
1131 can1: can@fc050000 {
1132 compatible = "bosch,m_can";
1133 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1134 reg-names = "m_can", "message_ram";
1135 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1136 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1137 interrupt-names = "int0", "int1";
1138 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
1139 clock-names = "hclk", "cclk";
1140 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
1141 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
1142 assigned-clock-rates = <40000000>;
1143 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1144 status = "disabled";
1147 sfrbu: sfr@fc05c000 {
1148 compatible = "atmel,sama5d2-sfrbu", "syscon";
1149 reg = <0xfc05c000 0x20>;
1153 compatible = "atmel,sama5d2-chipid";
1154 reg = <0xfc069000 0x8>;