1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
13 compatible = "rockchip,rv1108";
15 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
89 compatible = "simple-bus";
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
99 arm,pl330-broken-no-flushp;
100 clocks = <&cru ACLK_DMAC>;
101 clock-names = "apb_pclk";
105 bus_intmem: sram@10080000 {
106 compatible = "mmio-sram";
107 reg = <0x10080000 0x2000>;
108 #address-cells = <1>;
110 ranges = <0 0x10080000 0x2000>;
113 uart2: serial@10210000 {
114 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
115 reg = <0x10210000 0x100>;
116 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
119 clock-frequency = <24000000>;
120 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
121 clock-names = "baudclk", "apb_pclk";
122 dmas = <&pdma 6>, <&pdma 7>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&uart2m0_xfer>;
128 uart1: serial@10220000 {
129 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
130 reg = <0x10220000 0x100>;
131 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
134 clock-frequency = <24000000>;
135 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
136 clock-names = "baudclk", "apb_pclk";
137 dmas = <&pdma 4>, <&pdma 5>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&uart1_xfer>;
143 uart0: serial@10230000 {
144 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
145 reg = <0x10230000 0x100>;
146 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
149 clock-frequency = <24000000>;
150 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
151 clock-names = "baudclk", "apb_pclk";
152 dmas = <&pdma 2>, <&pdma 3>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
159 compatible = "rockchip,rv1108-i2c";
160 reg = <0x10240000 0x1000>;
161 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
162 #address-cells = <1>;
164 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
165 clock-names = "i2c", "pclk";
166 pinctrl-names = "default";
167 pinctrl-0 = <&i2c1_xfer>;
168 rockchip,grf = <&grf>;
173 compatible = "rockchip,rv1108-i2c";
174 reg = <0x10250000 0x1000>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 #address-cells = <1>;
178 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
179 clock-names = "i2c", "pclk";
180 pinctrl-names = "default";
181 pinctrl-0 = <&i2c2m1_xfer>;
182 rockchip,grf = <&grf>;
187 compatible = "rockchip,rv1108-i2c";
188 reg = <0x10260000 0x1000>;
189 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
190 #address-cells = <1>;
192 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
193 clock-names = "i2c", "pclk";
194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c3_xfer>;
196 rockchip,grf = <&grf>;
201 compatible = "rockchip,rv1108-spi";
202 reg = <0x10270000 0x1000>;
203 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
205 clock-names = "spiclk", "apb_pclk";
206 dmas = <&pdma 8>, <&pdma 9>;
207 dma-names = "tx", "rx";
208 #address-cells = <1>;
214 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
215 reg = <0x10280000 0x10>;
216 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
218 clock-names = "pwm", "pclk";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pwm4_pin>;
226 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
227 reg = <0x10280010 0x10>;
228 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
230 clock-names = "pwm", "pclk";
231 pinctrl-names = "default";
232 pinctrl-0 = <&pwm5_pin>;
238 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
239 reg = <0x10280020 0x10>;
240 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
242 clock-names = "pwm", "pclk";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pwm6_pin>;
250 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
251 reg = <0x10280030 0x10>;
252 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
254 clock-names = "pwm", "pclk";
255 pinctrl-names = "default";
256 pinctrl-0 = <&pwm7_pin>;
261 grf: syscon@10300000 {
262 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
263 reg = <0x10300000 0x1000>;
264 #address-cells = <1>;
267 u2phy: usb2-phy@100 {
268 compatible = "rockchip,rv1108-usb2phy";
270 clocks = <&cru SCLK_USBPHY>;
271 clock-names = "phyclk";
273 clock-output-names = "usbphy";
274 rockchip,usbgrf = <&usbgrf>;
277 u2phy_otg: otg-port {
278 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "otg-mux";
284 u2phy_host: host-port {
285 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-names = "linestate";
293 timer: timer@10350000 {
294 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
295 reg = <0x10350000 0x20>;
296 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&xin24m>, <&cru PCLK_TIMER>;
298 clock-names = "timer", "pclk";
301 watchdog: wdt@10360000 {
302 compatible = "snps,dw-wdt";
303 reg = <0x10360000 0x100>;
304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru PCLK_WDT>;
306 clock-names = "pclk_wdt";
311 soc_thermal: soc-thermal {
312 polling-delay-passive = <20>;
313 polling-delay = <1000>;
314 sustainable-power = <50>;
315 thermal-sensors = <&tsadc 0>;
318 threshold: trip-point0 {
319 temperature = <70000>;
323 target: trip-point1 {
324 temperature = <85000>;
329 temperature = <95000>;
338 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 contribution = <4096>;
345 tsadc: tsadc@10370000 {
346 compatible = "rockchip,rv1108-tsadc";
347 reg = <0x10370000 0x100>;
348 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
349 assigned-clocks = <&cru SCLK_TSADC>;
350 assigned-clock-rates = <750000>;
351 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
352 clock-names = "tsadc", "apb_pclk";
353 pinctrl-names = "init", "default", "sleep";
354 pinctrl-0 = <&otp_gpio>;
355 pinctrl-1 = <&otp_out>;
356 pinctrl-2 = <&otp_gpio>;
357 resets = <&cru SRST_TSADC>;
358 reset-names = "tsadc-apb";
359 rockchip,hw-tshut-temp = <120000>;
360 #thermal-sensor-cells = <1>;
365 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
366 reg = <0x1038c000 0x100>;
367 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
368 #io-channel-cells = <1>;
369 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
370 clock-names = "saradc", "apb_pclk";
375 compatible = "rockchip,rv1108-i2c";
376 reg = <0x20000000 0x1000>;
377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
381 clock-names = "i2c", "pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c0_xfer>;
384 rockchip,grf = <&grf>;
389 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
390 reg = <0x20040000 0x10>;
391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
393 clock-names = "pwm", "pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&pwm0_pin>;
401 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
402 reg = <0x20040010 0x10>;
403 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
405 clock-names = "pwm", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm1_pin>;
413 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
414 reg = <0x20040020 0x10>;
415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
417 clock-names = "pwm", "pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&pwm2_pin>;
425 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
426 reg = <0x20040030 0x10>;
427 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
429 clock-names = "pwm", "pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pwm3_pin>;
436 pmugrf: syscon@20060000 {
437 compatible = "rockchip,rv1108-pmugrf", "syscon";
438 reg = <0x20060000 0x1000>;
441 usbgrf: syscon@202a0000 {
442 compatible = "rockchip,rv1108-usbgrf", "syscon";
443 reg = <0x202a0000 0x1000>;
446 cru: clock-controller@20200000 {
447 compatible = "rockchip,rv1108-cru";
448 reg = <0x20200000 0x1000>;
449 rockchip,grf = <&grf>;
455 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
456 reg = <0x30110000 0x4000>;
457 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
459 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
460 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
461 fifo-depth = <0x100>;
462 max-frequency = <150000000>;
467 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
468 reg = <0x30120000 0x4000>;
469 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
471 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
472 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
473 fifo-depth = <0x100>;
474 max-frequency = <150000000>;
478 sdmmc: mmc@30130000 {
479 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
480 reg = <0x30130000 0x4000>;
481 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
483 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
484 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
485 fifo-depth = <0x100>;
486 max-frequency = <100000000>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
492 usb_host_ehci: usb@30140000 {
493 compatible = "generic-ehci";
494 reg = <0x30140000 0x20000>;
495 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cru HCLK_HOST0>, <&u2phy>;
497 phys = <&u2phy_host>;
502 usb_host_ohci: usb@30160000 {
503 compatible = "generic-ohci";
504 reg = <0x30160000 0x20000>;
505 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&cru HCLK_HOST0>, <&u2phy>;
507 phys = <&u2phy_host>;
512 usb_otg: usb@30180000 {
513 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
515 reg = <0x30180000 0x40000>;
516 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru HCLK_OTG>;
520 g-np-tx-fifo-size = <16>;
521 g-rx-fifo-size = <280>;
522 g-tx-fifo-size = <256 128 128 64 32 16>;
524 phy-names = "usb2-phy";
529 compatible = "rockchip,rv1108-gmac";
530 reg = <0x30200000 0x10000>;
531 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
533 interrupt-names = "macirq", "eth_wake_irq";
534 clocks = <&cru SCLK_MAC>,
535 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
536 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
537 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
538 clock-names = "stmmaceth",
539 "mac_clk_rx", "mac_clk_tx",
540 "clk_mac_ref", "clk_mac_refout",
541 "aclk_mac", "pclk_mac";
542 /* rv1108 only supports an rmii interface */
544 pinctrl-names = "default";
545 pinctrl-0 = <&rmii_pins>;
546 rockchip,grf = <&grf>;
550 gic: interrupt-controller@32010000 {
551 compatible = "arm,gic-400";
552 interrupt-controller;
553 #interrupt-cells = <3>;
554 #address-cells = <0>;
556 reg = <0x32011000 0x1000>,
560 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
564 compatible = "rockchip,rv1108-pinctrl";
565 rockchip,grf = <&grf>;
566 rockchip,pmu = <&pmugrf>;
567 #address-cells = <1>;
571 gpio0: gpio0@20030000 {
572 compatible = "rockchip,gpio-bank";
573 reg = <0x20030000 0x100>;
574 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cru PCLK_GPIO0_PMU>;
580 interrupt-controller;
581 #interrupt-cells = <2>;
584 gpio1: gpio1@10310000 {
585 compatible = "rockchip,gpio-bank";
586 reg = <0x10310000 0x100>;
587 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cru PCLK_GPIO1>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
597 gpio2: gpio2@10320000 {
598 compatible = "rockchip,gpio-bank";
599 reg = <0x10320000 0x100>;
600 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cru PCLK_GPIO2>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
610 gpio3: gpio3@10330000 {
611 compatible = "rockchip,gpio-bank";
612 reg = <0x10330000 0x100>;
613 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cru PCLK_GPIO3>;
619 interrupt-controller;
620 #interrupt-cells = <2>;
623 pcfg_pull_up: pcfg-pull-up {
627 pcfg_pull_down: pcfg-pull-down {
631 pcfg_pull_none: pcfg-pull-none {
635 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
636 drive-strength = <8>;
639 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
640 drive-strength = <12>;
643 pcfg_pull_none_smt: pcfg-pull-none-smt {
645 input-schmitt-enable;
648 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
650 drive-strength = <8>;
653 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
654 drive-strength = <4>;
657 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
659 drive-strength = <4>;
662 pcfg_output_high: pcfg-output-high {
666 pcfg_output_low: pcfg-output-low {
670 pcfg_input_high: pcfg-input-high {
676 emmc_bus8: emmc-bus8 {
677 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
678 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
679 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
680 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
681 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
682 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
683 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
684 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
688 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
692 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
697 rmii_pins: rmii-pins {
698 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
699 <1 RK_PC3 2 &pcfg_pull_none>,
700 <1 RK_PC4 2 &pcfg_pull_none>,
701 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
702 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
703 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
704 <1 RK_PB5 3 &pcfg_pull_none>,
705 <1 RK_PB6 3 &pcfg_pull_none>,
706 <1 RK_PB7 3 &pcfg_pull_none>,
707 <1 RK_PC2 3 &pcfg_pull_none>;
712 i2c0_xfer: i2c0-xfer {
713 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
714 <0 RK_PB2 1 &pcfg_pull_none_smt>;
719 i2c1_xfer: i2c1-xfer {
720 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
721 <2 RK_PD4 1 &pcfg_pull_up>;
726 i2c2m1_xfer: i2c2m1-xfer {
727 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
728 <0 RK_PC6 3 &pcfg_pull_none>;
731 i2c2m1_gpio: i2c2m1-gpio {
732 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
733 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
738 i2c2m05v_xfer: i2c2m05v-xfer {
739 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
740 <1 RK_PD4 2 &pcfg_pull_none>;
743 i2c2m05v_gpio: i2c2m05v-gpio {
744 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
745 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
750 i2c3_xfer: i2c3-xfer {
751 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
752 <0 RK_PC4 2 &pcfg_pull_none>;
758 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
764 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
770 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
776 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
782 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
788 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
794 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
800 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
805 sdmmc_clk: sdmmc-clk {
806 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
809 sdmmc_cmd: sdmmc-cmd {
810 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
814 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
817 sdmmc_bus1: sdmmc-bus1 {
818 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
821 sdmmc_bus4: sdmmc-bus4 {
822 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
823 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
824 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
825 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
830 spim0_clk: spim0-clk {
831 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
834 spim0_cs0: spim0-cs0 {
835 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
839 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
843 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
848 spim1_clk: spim1-clk {
849 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
852 spim1_cs0: spim1-cs0 {
853 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
857 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
861 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
867 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
871 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
876 uart0_xfer: uart0-xfer {
877 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
878 <3 RK_PA5 1 &pcfg_pull_none>;
881 uart0_cts: uart0-cts {
882 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
885 uart0_rts: uart0-rts {
886 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
889 uart0_rts_gpio: uart0-rts-gpio {
890 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
895 uart1_xfer: uart1-xfer {
896 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
897 <1 RK_PD2 1 &pcfg_pull_none>;
900 uart1_cts: uart1-cts {
901 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
904 uart1_rts: uart1-rts {
905 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
910 uart2m0_xfer: uart2m0-xfer {
911 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
912 <2 RK_PD1 1 &pcfg_pull_none>;
917 uart2m1_xfer: uart2m1-xfer {
918 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
919 <3 RK_PC2 2 &pcfg_pull_none>;
924 uart2_5v_cts: uart2_5v-cts {
925 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
928 uart2_5v_rts: uart2_5v-rts {
929 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;