1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
13 compatible = "rockchip,rv1108";
15 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
89 compatible = "simple-bus";
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
99 arm,pl330-broken-no-flushp;
100 arm,pl330-periph-burst;
101 clocks = <&cru ACLK_DMAC>;
102 clock-names = "apb_pclk";
106 bus_intmem: sram@10080000 {
107 compatible = "mmio-sram";
108 reg = <0x10080000 0x2000>;
109 #address-cells = <1>;
111 ranges = <0 0x10080000 0x2000>;
114 uart2: serial@10210000 {
115 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
116 reg = <0x10210000 0x100>;
117 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
120 clock-frequency = <24000000>;
121 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
122 clock-names = "baudclk", "apb_pclk";
123 dmas = <&pdma 6>, <&pdma 7>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
129 uart1: serial@10220000 {
130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
131 reg = <0x10220000 0x100>;
132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
135 clock-frequency = <24000000>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 clock-names = "baudclk", "apb_pclk";
138 dmas = <&pdma 4>, <&pdma 5>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&uart1_xfer>;
144 uart0: serial@10230000 {
145 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
146 reg = <0x10230000 0x100>;
147 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
150 clock-frequency = <24000000>;
151 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
152 clock-names = "baudclk", "apb_pclk";
153 dmas = <&pdma 2>, <&pdma 3>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
160 compatible = "rockchip,rv1108-i2c";
161 reg = <0x10240000 0x1000>;
162 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
163 #address-cells = <1>;
165 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
166 clock-names = "i2c", "pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&i2c1_xfer>;
169 rockchip,grf = <&grf>;
174 compatible = "rockchip,rv1108-i2c";
175 reg = <0x10250000 0x1000>;
176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
177 #address-cells = <1>;
179 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
180 clock-names = "i2c", "pclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c2m1_xfer>;
183 rockchip,grf = <&grf>;
188 compatible = "rockchip,rv1108-i2c";
189 reg = <0x10260000 0x1000>;
190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
191 #address-cells = <1>;
193 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
194 clock-names = "i2c", "pclk";
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2c3_xfer>;
197 rockchip,grf = <&grf>;
202 compatible = "rockchip,rv1108-spi";
203 reg = <0x10270000 0x1000>;
204 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
206 clock-names = "spiclk", "apb_pclk";
207 dmas = <&pdma 8>, <&pdma 9>;
208 dma-names = "tx", "rx";
209 #address-cells = <1>;
215 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
216 reg = <0x10280000 0x10>;
217 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
219 clock-names = "pwm", "pclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&pwm4_pin>;
227 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
228 reg = <0x10280010 0x10>;
229 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
231 clock-names = "pwm", "pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pwm5_pin>;
239 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
240 reg = <0x10280020 0x10>;
241 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
243 clock-names = "pwm", "pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&pwm6_pin>;
251 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
252 reg = <0x10280030 0x10>;
253 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
255 clock-names = "pwm", "pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pwm7_pin>;
262 grf: syscon@10300000 {
263 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
264 reg = <0x10300000 0x1000>;
265 #address-cells = <1>;
268 u2phy: usb2-phy@100 {
269 compatible = "rockchip,rv1108-usb2phy";
271 clocks = <&cru SCLK_USBPHY>;
272 clock-names = "phyclk";
274 clock-output-names = "usbphy";
275 rockchip,usbgrf = <&usbgrf>;
278 u2phy_otg: otg-port {
279 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "otg-mux";
285 u2phy_host: host-port {
286 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-names = "linestate";
294 timer: timer@10350000 {
295 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
296 reg = <0x10350000 0x20>;
297 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&xin24m>, <&cru PCLK_TIMER>;
299 clock-names = "timer", "pclk";
302 watchdog: watchdog@10360000 {
303 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
304 reg = <0x10360000 0x100>;
305 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cru PCLK_WDT>;
311 soc_thermal: soc-thermal {
312 polling-delay-passive = <20>;
313 polling-delay = <1000>;
314 sustainable-power = <50>;
315 thermal-sensors = <&tsadc 0>;
318 threshold: trip-point0 {
319 temperature = <70000>;
323 target: trip-point1 {
324 temperature = <85000>;
329 temperature = <95000>;
338 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 contribution = <4096>;
345 tsadc: tsadc@10370000 {
346 compatible = "rockchip,rv1108-tsadc";
347 reg = <0x10370000 0x100>;
348 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
349 assigned-clocks = <&cru SCLK_TSADC>;
350 assigned-clock-rates = <750000>;
351 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
352 clock-names = "tsadc", "apb_pclk";
353 pinctrl-names = "init", "default", "sleep";
354 pinctrl-0 = <&otp_pin>;
355 pinctrl-1 = <&otp_out>;
356 pinctrl-2 = <&otp_pin>;
357 resets = <&cru SRST_TSADC>;
358 reset-names = "tsadc-apb";
359 rockchip,hw-tshut-temp = <120000>;
360 #thermal-sensor-cells = <1>;
365 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
366 reg = <0x1038c000 0x100>;
367 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
368 #io-channel-cells = <1>;
369 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
370 clock-names = "saradc", "apb_pclk";
375 compatible = "rockchip,rv1108-i2c";
376 reg = <0x20000000 0x1000>;
377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
381 clock-names = "i2c", "pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c0_xfer>;
384 rockchip,grf = <&grf>;
389 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
390 reg = <0x20040000 0x10>;
391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
393 clock-names = "pwm", "pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&pwm0_pin>;
401 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
402 reg = <0x20040010 0x10>;
403 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
405 clock-names = "pwm", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm1_pin>;
413 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
414 reg = <0x20040020 0x10>;
415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
417 clock-names = "pwm", "pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&pwm2_pin>;
425 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
426 reg = <0x20040030 0x10>;
427 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
429 clock-names = "pwm", "pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pwm3_pin>;
436 pmugrf: syscon@20060000 {
437 compatible = "rockchip,rv1108-pmugrf", "syscon";
438 reg = <0x20060000 0x1000>;
441 usbgrf: syscon@202a0000 {
442 compatible = "rockchip,rv1108-usbgrf", "syscon";
443 reg = <0x202a0000 0x1000>;
446 cru: clock-controller@20200000 {
447 compatible = "rockchip,rv1108-cru";
448 reg = <0x20200000 0x1000>;
449 rockchip,grf = <&grf>;
454 nfc: nand-controller@30100000 {
455 compatible = "rockchip,rv1108-nfc";
456 reg = <0x30100000 0x1000>;
457 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
459 clock-names = "ahb", "nfc";
460 assigned-clocks = <&cru SCLK_NANDC>;
461 assigned-clock-rates = <150000000>;
466 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
467 reg = <0x30110000 0x4000>;
468 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
470 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
471 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
472 fifo-depth = <0x100>;
473 max-frequency = <150000000>;
478 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
479 reg = <0x30120000 0x4000>;
480 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
482 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
483 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
484 fifo-depth = <0x100>;
485 max-frequency = <150000000>;
489 sdmmc: mmc@30130000 {
490 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
491 reg = <0x30130000 0x4000>;
492 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
494 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
495 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
496 fifo-depth = <0x100>;
497 max-frequency = <100000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
503 usb_host_ehci: usb@30140000 {
504 compatible = "generic-ehci";
505 reg = <0x30140000 0x20000>;
506 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&cru HCLK_HOST0>, <&u2phy>;
508 phys = <&u2phy_host>;
513 usb_host_ohci: usb@30160000 {
514 compatible = "generic-ohci";
515 reg = <0x30160000 0x20000>;
516 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru HCLK_HOST0>, <&u2phy>;
518 phys = <&u2phy_host>;
523 usb_otg: usb@30180000 {
524 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
526 reg = <0x30180000 0x40000>;
527 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cru HCLK_OTG>;
531 g-np-tx-fifo-size = <16>;
532 g-rx-fifo-size = <280>;
533 g-tx-fifo-size = <256 128 128 64 32 16>;
535 phy-names = "usb2-phy";
540 compatible = "rockchip,rv1108-gmac";
541 reg = <0x30200000 0x10000>;
542 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
544 interrupt-names = "macirq", "eth_wake_irq";
545 clocks = <&cru SCLK_MAC>,
546 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
547 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
548 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
549 clock-names = "stmmaceth",
550 "mac_clk_rx", "mac_clk_tx",
551 "clk_mac_ref", "clk_mac_refout",
552 "aclk_mac", "pclk_mac";
553 /* rv1108 only supports an rmii interface */
555 pinctrl-names = "default";
556 pinctrl-0 = <&rmii_pins>;
557 rockchip,grf = <&grf>;
561 gic: interrupt-controller@32010000 {
562 compatible = "arm,gic-400";
563 interrupt-controller;
564 #interrupt-cells = <3>;
565 #address-cells = <0>;
567 reg = <0x32011000 0x1000>,
571 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
575 compatible = "rockchip,rv1108-pinctrl";
576 rockchip,grf = <&grf>;
577 rockchip,pmu = <&pmugrf>;
578 #address-cells = <1>;
582 gpio0: gpio0@20030000 {
583 compatible = "rockchip,gpio-bank";
584 reg = <0x20030000 0x100>;
585 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&cru PCLK_GPIO0_PMU>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
595 gpio1: gpio1@10310000 {
596 compatible = "rockchip,gpio-bank";
597 reg = <0x10310000 0x100>;
598 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cru PCLK_GPIO1>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
608 gpio2: gpio2@10320000 {
609 compatible = "rockchip,gpio-bank";
610 reg = <0x10320000 0x100>;
611 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&cru PCLK_GPIO2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
621 gpio3: gpio3@10330000 {
622 compatible = "rockchip,gpio-bank";
623 reg = <0x10330000 0x100>;
624 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&cru PCLK_GPIO3>;
630 interrupt-controller;
631 #interrupt-cells = <2>;
634 pcfg_pull_up: pcfg-pull-up {
638 pcfg_pull_down: pcfg-pull-down {
642 pcfg_pull_none: pcfg-pull-none {
646 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
647 drive-strength = <8>;
650 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
651 drive-strength = <12>;
654 pcfg_pull_none_smt: pcfg-pull-none-smt {
656 input-schmitt-enable;
659 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
661 drive-strength = <8>;
664 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
665 drive-strength = <4>;
668 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
670 drive-strength = <4>;
673 pcfg_output_high: pcfg-output-high {
677 pcfg_output_low: pcfg-output-low {
681 pcfg_input_high: pcfg-input-high {
687 emmc_bus8: emmc-bus8 {
688 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
689 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
690 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
691 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
692 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
693 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
694 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
695 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
699 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
703 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
708 rmii_pins: rmii-pins {
709 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
710 <1 RK_PC3 2 &pcfg_pull_none>,
711 <1 RK_PC4 2 &pcfg_pull_none>,
712 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
713 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
714 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
715 <1 RK_PB5 3 &pcfg_pull_none>,
716 <1 RK_PB6 3 &pcfg_pull_none>,
717 <1 RK_PB7 3 &pcfg_pull_none>,
718 <1 RK_PC2 3 &pcfg_pull_none>;
723 i2c0_xfer: i2c0-xfer {
724 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
725 <0 RK_PB2 1 &pcfg_pull_none_smt>;
730 i2c1_xfer: i2c1-xfer {
731 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
732 <2 RK_PD4 1 &pcfg_pull_up>;
737 i2c2m1_xfer: i2c2m1-xfer {
738 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
739 <0 RK_PC6 3 &pcfg_pull_none>;
742 i2c2m1_pins: i2c2m1-pins {
743 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
744 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
749 i2c2m05v_xfer: i2c2m05v-xfer {
750 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
751 <1 RK_PD4 2 &pcfg_pull_none>;
754 i2c2m05v_pins: i2c2m05v-pins {
755 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
756 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
761 i2c3_xfer: i2c3-xfer {
762 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
763 <0 RK_PC4 2 &pcfg_pull_none>;
769 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
775 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
781 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
787 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
793 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
799 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
805 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
811 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
816 sdmmc_clk: sdmmc-clk {
817 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
820 sdmmc_cmd: sdmmc-cmd {
821 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
825 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
828 sdmmc_bus1: sdmmc-bus1 {
829 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
832 sdmmc_bus4: sdmmc-bus4 {
833 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
834 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
835 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
836 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
841 spim0_clk: spim0-clk {
842 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
845 spim0_cs0: spim0-cs0 {
846 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
850 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
854 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
859 spim1_clk: spim1-clk {
860 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
863 spim1_cs0: spim1-cs0 {
864 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
868 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
872 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
878 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
882 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
887 uart0_xfer: uart0-xfer {
888 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
889 <3 RK_PA5 1 &pcfg_pull_none>;
892 uart0_cts: uart0-cts {
893 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
896 uart0_rts: uart0-rts {
897 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
900 uart0_rts_pin: uart0-rts-pin {
901 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
906 uart1_xfer: uart1-xfer {
907 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
908 <1 RK_PD2 1 &pcfg_pull_none>;
911 uart1_cts: uart1-cts {
912 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
915 uart1_rts: uart1-rts {
916 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
921 uart2m0_xfer: uart2m0-xfer {
922 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
923 <2 RK_PD1 1 &pcfg_pull_none>;
928 uart2m1_xfer: uart2m1-xfer {
929 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
930 <3 RK_PC2 2 &pcfg_pull_none>;
935 uart2_5v_cts: uart2_5v-cts {
936 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
939 uart2_5v_rts: uart2_5v-rts {
940 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;