1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
13 compatible = "rockchip,rv1108";
15 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
35 clocks = <&cru ARMCLK>;
36 #cooling-cells = <2>; /* min followed by max */
37 dynamic-power-coefficient = <75>;
38 operating-points-v2 = <&cpu_opp_table>;
42 cpu_opp_table: opp_table {
43 compatible = "operating-points-v2";
46 opp-hz = /bits/ 64 <408000000>;
47 opp-microvolt = <975000>;
48 clock-latency-ns = <40000>;
51 opp-hz = /bits/ 64 <600000000>;
52 opp-microvolt = <975000>;
53 clock-latency-ns = <40000>;
56 opp-hz = /bits/ 64 <816000000>;
57 opp-microvolt = <1025000>;
58 clock-latency-ns = <40000>;
61 opp-hz = /bits/ 64 <1008000000>;
62 opp-microvolt = <1150000>;
63 clock-latency-ns = <40000>;
68 compatible = "arm,cortex-a7-pmu";
69 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
76 clock-frequency = <24000000>;
80 compatible = "fixed-clock";
81 clock-frequency = <24000000>;
82 clock-output-names = "xin24m";
87 compatible = "simple-bus";
93 compatible = "arm,pl330", "arm,primecell";
94 reg = <0x102a0000 0x4000>;
95 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
97 arm,pl330-broken-no-flushp;
98 clocks = <&cru ACLK_DMAC>;
99 clock-names = "apb_pclk";
103 bus_intmem@10080000 {
104 compatible = "mmio-sram";
105 reg = <0x10080000 0x2000>;
106 #address-cells = <1>;
108 ranges = <0 0x10080000 0x2000>;
111 uart2: serial@10210000 {
112 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
113 reg = <0x10210000 0x100>;
114 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
117 clock-frequency = <24000000>;
118 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
119 clock-names = "baudclk", "apb_pclk";
120 pinctrl-names = "default";
121 pinctrl-0 = <&uart2m0_xfer>;
125 uart1: serial@10220000 {
126 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
127 reg = <0x10220000 0x100>;
128 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
131 clock-frequency = <24000000>;
132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
133 clock-names = "baudclk", "apb_pclk";
134 pinctrl-names = "default";
135 pinctrl-0 = <&uart1_xfer>;
139 uart0: serial@10230000 {
140 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
141 reg = <0x10230000 0x100>;
142 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
145 clock-frequency = <24000000>;
146 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
147 clock-names = "baudclk", "apb_pclk";
148 pinctrl-names = "default";
149 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
154 compatible = "rockchip,rv1108-i2c";
155 reg = <0x10240000 0x1000>;
156 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
157 #address-cells = <1>;
159 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
160 clock-names = "i2c", "pclk";
161 pinctrl-names = "default";
162 pinctrl-0 = <&i2c1_xfer>;
163 rockchip,grf = <&grf>;
168 compatible = "rockchip,rv1108-i2c";
169 reg = <0x10250000 0x1000>;
170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
171 #address-cells = <1>;
173 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
174 clock-names = "i2c", "pclk";
175 pinctrl-names = "default";
176 pinctrl-0 = <&i2c2m1_xfer>;
177 rockchip,grf = <&grf>;
182 compatible = "rockchip,rv1108-i2c";
183 reg = <0x10260000 0x1000>;
184 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
185 #address-cells = <1>;
187 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
188 clock-names = "i2c", "pclk";
189 pinctrl-names = "default";
190 pinctrl-0 = <&i2c3_xfer>;
191 rockchip,grf = <&grf>;
196 compatible = "rockchip,rv1108-spi";
197 reg = <0x10270000 0x1000>;
198 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
200 clock-names = "spiclk", "apb_pclk";
201 dmas = <&pdma 8>, <&pdma 9>;
203 #address-cells = <1>;
209 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
210 reg = <0x10280000 0x10>;
211 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
213 clock-names = "pwm", "pclk";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pwm4_pin>;
221 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
222 reg = <0x10280010 0x10>;
223 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
225 clock-names = "pwm", "pclk";
226 pinctrl-names = "default";
227 pinctrl-0 = <&pwm5_pin>;
233 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
234 reg = <0x10280020 0x10>;
235 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
237 clock-names = "pwm", "pclk";
238 pinctrl-names = "default";
239 pinctrl-0 = <&pwm6_pin>;
245 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
246 reg = <0x10280030 0x10>;
247 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
249 clock-names = "pwm", "pclk";
250 pinctrl-names = "default";
251 pinctrl-0 = <&pwm7_pin>;
256 grf: syscon@10300000 {
257 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
258 reg = <0x10300000 0x1000>;
259 #address-cells = <1>;
262 u2phy: usb2-phy@100 {
263 compatible = "rockchip,rv1108-usb2phy";
265 clocks = <&cru SCLK_USBPHY>;
266 clock-names = "phyclk";
268 clock-output-names = "usbphy";
269 rockchip,usbgrf = <&usbgrf>;
272 u2phy_otg: otg-port {
273 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-names = "otg-mux";
279 u2phy_host: host-port {
280 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-names = "linestate";
288 watchdog: wdt@10360000 {
289 compatible = "snps,dw-wdt";
290 reg = <0x10360000 0x100>;
291 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_WDT>;
293 clock-names = "pclk_wdt";
298 soc_thermal: soc-thermal {
299 polling-delay-passive = <20>;
300 polling-delay = <1000>;
301 sustainable-power = <50>;
302 thermal-sensors = <&tsadc 0>;
305 threshold: trip-point0 {
306 temperature = <70000>;
310 target: trip-point1 {
311 temperature = <85000>;
316 temperature = <95000>;
325 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
326 contribution = <4096>;
332 tsadc: tsadc@10370000 {
333 compatible = "rockchip,rv1108-tsadc";
334 reg = <0x10370000 0x100>;
335 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
336 assigned-clocks = <&cru SCLK_TSADC>;
337 assigned-clock-rates = <750000>;
338 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
339 clock-names = "tsadc", "apb_pclk";
340 pinctrl-names = "init", "default", "sleep";
341 pinctrl-0 = <&otp_gpio>;
342 pinctrl-1 = <&otp_out>;
343 pinctrl-2 = <&otp_gpio>;
344 resets = <&cru SRST_TSADC>;
345 reset-names = "tsadc-apb";
346 rockchip,hw-tshut-temp = <120000>;
347 #thermal-sensor-cells = <1>;
352 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
353 reg = <0x1038c000 0x100>;
354 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
355 #io-channel-cells = <1>;
356 clock-frequency = <1000000>;
357 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
358 clock-names = "saradc", "apb_pclk";
363 compatible = "rockchip,rv1108-i2c";
364 reg = <0x20000000 0x1000>;
365 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>;
368 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
369 clock-names = "i2c", "pclk";
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c0_xfer>;
372 rockchip,grf = <&grf>;
377 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
378 reg = <0x20040000 0x10>;
379 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
381 clock-names = "pwm", "pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&pwm0_pin>;
389 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
390 reg = <0x20040010 0x10>;
391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
393 clock-names = "pwm", "pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&pwm1_pin>;
401 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
402 reg = <0x20040020 0x10>;
403 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
405 clock-names = "pwm", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm2_pin>;
413 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
414 reg = <0x20040030 0x10>;
415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
417 clock-names = "pwm", "pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&pwm3_pin>;
424 pmugrf: syscon@20060000 {
425 compatible = "rockchip,rv1108-pmugrf", "syscon";
426 reg = <0x20060000 0x1000>;
429 usbgrf: syscon@202a0000 {
430 compatible = "rockchip,rv1108-usbgrf", "syscon";
431 reg = <0x202a0000 0x1000>;
434 cru: clock-controller@20200000 {
435 compatible = "rockchip,rv1108-cru";
436 reg = <0x20200000 0x1000>;
437 rockchip,grf = <&grf>;
442 emmc: dwmmc@30110000 {
443 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
444 reg = <0x30110000 0x4000>;
445 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
447 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
448 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
449 fifo-depth = <0x100>;
450 max-frequency = <150000000>;
454 sdio: dwmmc@30120000 {
455 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
456 reg = <0x30120000 0x4000>;
457 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
459 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
460 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
461 fifo-depth = <0x100>;
462 max-frequency = <150000000>;
466 sdmmc: dwmmc@30130000 {
467 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
468 reg = <0x30130000 0x4000>;
469 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
471 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
472 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
473 fifo-depth = <0x100>;
474 max-frequency = <100000000>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
480 usb_host_ehci: usb@30140000 {
481 compatible = "generic-ehci";
482 reg = <0x30140000 0x20000>;
483 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru HCLK_HOST0>, <&u2phy>;
485 clock-names = "usbhost", "utmi";
486 phys = <&u2phy_host>;
491 usb_host_ohci: usb@30160000 {
492 compatible = "generic-ohci";
493 reg = <0x30160000 0x20000>;
494 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&cru HCLK_HOST0>, <&u2phy>;
496 clock-names = "usbhost", "utmi";
497 phys = <&u2phy_host>;
502 usb_otg: usb@30180000 {
503 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
505 reg = <0x30180000 0x40000>;
506 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&cru HCLK_OTG>;
510 g-np-tx-fifo-size = <16>;
511 g-rx-fifo-size = <280>;
512 g-tx-fifo-size = <256 128 128 64 32 16>;
515 phy-names = "usb2-phy";
520 compatible = "rockchip,rv1108-gmac";
521 reg = <0x30200000 0x10000>;
522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
524 interrupt-names = "macirq", "eth_wake_irq";
525 clocks = <&cru SCLK_MAC>,
526 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
527 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
528 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
529 clock-names = "stmmaceth",
530 "mac_clk_rx", "mac_clk_tx",
531 "clk_mac_ref", "clk_mac_refout",
532 "aclk_mac", "pclk_mac";
533 /* rv1108 only supports an rmii interface */
535 pinctrl-names = "default";
536 pinctrl-0 = <&rmii_pins>;
537 rockchip,grf = <&grf>;
541 gic: interrupt-controller@32010000 {
542 compatible = "arm,gic-400";
543 interrupt-controller;
544 #interrupt-cells = <3>;
545 #address-cells = <0>;
547 reg = <0x32011000 0x1000>,
551 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
555 compatible = "rockchip,rv1108-pinctrl";
556 rockchip,grf = <&grf>;
557 rockchip,pmu = <&pmugrf>;
558 #address-cells = <1>;
562 gpio0: gpio0@20030000 {
563 compatible = "rockchip,gpio-bank";
564 reg = <0x20030000 0x100>;
565 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
575 gpio1: gpio1@10310000 {
576 compatible = "rockchip,gpio-bank";
577 reg = <0x10310000 0x100>;
578 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
588 gpio2: gpio2@10320000 {
589 compatible = "rockchip,gpio-bank";
590 reg = <0x10320000 0x100>;
591 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
601 gpio3: gpio3@10330000 {
602 compatible = "rockchip,gpio-bank";
603 reg = <0x10330000 0x100>;
604 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
614 pcfg_pull_up: pcfg-pull-up {
618 pcfg_pull_down: pcfg-pull-down {
622 pcfg_pull_none: pcfg-pull-none {
626 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
627 drive-strength = <8>;
630 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
631 drive-strength = <12>;
634 pcfg_pull_none_smt: pcfg-pull-none-smt {
636 input-schmitt-enable;
639 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
641 drive-strength = <8>;
644 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
645 drive-strength = <4>;
648 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
650 drive-strength = <4>;
653 pcfg_output_high: pcfg-output-high {
657 pcfg_output_low: pcfg-output-low {
661 pcfg_input_high: pcfg-input-high {
667 emmc_bus8: emmc-bus8 {
668 rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
669 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
670 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
671 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
672 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
673 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
674 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
675 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
679 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
683 rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
688 rmii_pins: rmii-pins {
689 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
690 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
691 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
692 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
693 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
694 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
695 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
696 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
697 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
698 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
703 i2c0_xfer: i2c0-xfer {
704 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
705 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
710 i2c1_xfer: i2c1-xfer {
711 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
712 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
717 i2c2m1_xfer: i2c2m1-xfer {
718 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
719 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
722 i2c2m1_gpio: i2c2m1-gpio {
723 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
724 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
729 i2c2m05v_xfer: i2c2m05v-xfer {
730 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
731 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
734 i2c2m05v_gpio: i2c2m05v-gpio {
735 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
736 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
741 i2c3_xfer: i2c3-xfer {
742 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
743 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
749 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
755 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
761 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
767 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
773 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
779 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
785 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
791 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
796 sdmmc_clk: sdmmc-clk {
797 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
800 sdmmc_cmd: sdmmc-cmd {
801 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
805 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
808 sdmmc_bus1: sdmmc-bus1 {
809 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
812 sdmmc_bus4: sdmmc-bus4 {
813 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
814 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
815 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
816 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
822 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
826 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
831 uart0_xfer: uart0-xfer {
832 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
833 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
836 uart0_cts: uart0-cts {
837 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
840 uart0_rts: uart0-rts {
841 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
844 uart0_rts_gpio: uart0-rts-gpio {
845 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
850 uart1_xfer: uart1-xfer {
851 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
852 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
855 uart1_cts: uart1-cts {
856 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
859 uart1_rts: uart1-rts {
860 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
865 uart2m0_xfer: uart2m0-xfer {
866 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
867 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
872 uart2m1_xfer: uart2m1-xfer {
873 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
874 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
879 uart2_5v_cts: uart2_5v-cts {
880 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
883 uart2_5v_rts: uart2_5v-rts {
884 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;