1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
13 compatible = "rockchip,rv1108";
15 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
89 compatible = "simple-bus";
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
99 arm,pl330-broken-no-flushp;
100 arm,pl330-periph-burst;
101 clocks = <&cru ACLK_DMAC>;
102 clock-names = "apb_pclk";
106 bus_intmem: sram@10080000 {
107 compatible = "mmio-sram";
108 reg = <0x10080000 0x2000>;
109 #address-cells = <1>;
111 ranges = <0 0x10080000 0x2000>;
114 uart2: serial@10210000 {
115 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
116 reg = <0x10210000 0x100>;
117 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
120 clock-frequency = <24000000>;
121 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
122 clock-names = "baudclk", "apb_pclk";
123 dmas = <&pdma 6>, <&pdma 7>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
129 uart1: serial@10220000 {
130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
131 reg = <0x10220000 0x100>;
132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
135 clock-frequency = <24000000>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 clock-names = "baudclk", "apb_pclk";
138 dmas = <&pdma 4>, <&pdma 5>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&uart1_xfer>;
144 uart0: serial@10230000 {
145 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
146 reg = <0x10230000 0x100>;
147 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
150 clock-frequency = <24000000>;
151 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
152 clock-names = "baudclk", "apb_pclk";
153 dmas = <&pdma 2>, <&pdma 3>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
160 compatible = "rockchip,rv1108-i2c";
161 reg = <0x10240000 0x1000>;
162 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
163 #address-cells = <1>;
165 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
166 clock-names = "i2c", "pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&i2c1_xfer>;
169 rockchip,grf = <&grf>;
174 compatible = "rockchip,rv1108-i2c";
175 reg = <0x10250000 0x1000>;
176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
177 #address-cells = <1>;
179 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
180 clock-names = "i2c", "pclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c2m1_xfer>;
183 rockchip,grf = <&grf>;
188 compatible = "rockchip,rv1108-i2c";
189 reg = <0x10260000 0x1000>;
190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
191 #address-cells = <1>;
193 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
194 clock-names = "i2c", "pclk";
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2c3_xfer>;
197 rockchip,grf = <&grf>;
202 compatible = "rockchip,rv1108-spi";
203 reg = <0x10270000 0x1000>;
204 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
206 clock-names = "spiclk", "apb_pclk";
207 dmas = <&pdma 8>, <&pdma 9>;
208 dma-names = "tx", "rx";
209 #address-cells = <1>;
215 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
216 reg = <0x10280000 0x10>;
217 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
219 clock-names = "pwm", "pclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&pwm4_pin>;
227 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
228 reg = <0x10280010 0x10>;
229 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
231 clock-names = "pwm", "pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pwm5_pin>;
239 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
240 reg = <0x10280020 0x10>;
241 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
243 clock-names = "pwm", "pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&pwm6_pin>;
251 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
252 reg = <0x10280030 0x10>;
253 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
255 clock-names = "pwm", "pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pwm7_pin>;
262 grf: syscon@10300000 {
263 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
264 reg = <0x10300000 0x1000>;
265 #address-cells = <1>;
268 io_domains: io-domains {
269 compatible = "rockchip,rv1108-io-voltage-domain";
274 compatible = "rockchip,rv1108-usb2phy";
276 clocks = <&cru SCLK_USBPHY>;
277 clock-names = "phyclk";
279 clock-output-names = "usbphy";
280 rockchip,usbgrf = <&usbgrf>;
283 u2phy_otg: otg-port {
284 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-names = "otg-mux";
290 u2phy_host: host-port {
291 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-names = "linestate";
299 timer: timer@10350000 {
300 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
301 reg = <0x10350000 0x20>;
302 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&xin24m>, <&cru PCLK_TIMER>;
304 clock-names = "timer", "pclk";
307 watchdog: watchdog@10360000 {
308 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
309 reg = <0x10360000 0x100>;
310 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cru PCLK_WDT>;
316 soc_thermal: soc-thermal {
317 polling-delay-passive = <20>;
318 polling-delay = <1000>;
319 sustainable-power = <50>;
320 thermal-sensors = <&tsadc 0>;
323 threshold: trip-point0 {
324 temperature = <70000>;
328 target: trip-point1 {
329 temperature = <85000>;
334 temperature = <95000>;
343 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
344 contribution = <4096>;
350 tsadc: tsadc@10370000 {
351 compatible = "rockchip,rv1108-tsadc";
352 reg = <0x10370000 0x100>;
353 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
354 assigned-clocks = <&cru SCLK_TSADC>;
355 assigned-clock-rates = <750000>;
356 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
357 clock-names = "tsadc", "apb_pclk";
358 pinctrl-names = "init", "default", "sleep";
359 pinctrl-0 = <&otp_pin>;
360 pinctrl-1 = <&otp_out>;
361 pinctrl-2 = <&otp_pin>;
362 resets = <&cru SRST_TSADC>;
363 reset-names = "tsadc-apb";
364 rockchip,hw-tshut-temp = <120000>;
365 #thermal-sensor-cells = <1>;
370 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
371 reg = <0x1038c000 0x100>;
372 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
373 #io-channel-cells = <1>;
374 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
375 clock-names = "saradc", "apb_pclk";
380 compatible = "rockchip,rv1108-i2c";
381 reg = <0x20000000 0x1000>;
382 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
385 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c0_xfer>;
389 rockchip,grf = <&grf>;
394 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
395 reg = <0x20040000 0x10>;
396 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
398 clock-names = "pwm", "pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm0_pin>;
406 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
407 reg = <0x20040010 0x10>;
408 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
410 clock-names = "pwm", "pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&pwm1_pin>;
418 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
419 reg = <0x20040020 0x10>;
420 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
422 clock-names = "pwm", "pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
430 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
431 reg = <0x20040030 0x10>;
432 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
441 pmugrf: syscon@20060000 {
442 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
443 reg = <0x20060000 0x1000>;
445 pmu_io_domains: io-domains {
446 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
451 usbgrf: syscon@202a0000 {
452 compatible = "rockchip,rv1108-usbgrf", "syscon";
453 reg = <0x202a0000 0x1000>;
456 cru: clock-controller@20200000 {
457 compatible = "rockchip,rv1108-cru";
458 reg = <0x20200000 0x1000>;
459 rockchip,grf = <&grf>;
464 nfc: nand-controller@30100000 {
465 compatible = "rockchip,rv1108-nfc";
466 reg = <0x30100000 0x1000>;
467 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
469 clock-names = "ahb", "nfc";
470 assigned-clocks = <&cru SCLK_NANDC>;
471 assigned-clock-rates = <150000000>;
476 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
477 reg = <0x30110000 0x4000>;
478 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
480 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
481 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
482 fifo-depth = <0x100>;
483 max-frequency = <150000000>;
488 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
489 reg = <0x30120000 0x4000>;
490 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
492 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
493 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
494 fifo-depth = <0x100>;
495 max-frequency = <150000000>;
499 sdmmc: mmc@30130000 {
500 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
501 reg = <0x30130000 0x4000>;
502 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
504 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
505 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
506 fifo-depth = <0x100>;
507 max-frequency = <100000000>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
513 usb_host_ehci: usb@30140000 {
514 compatible = "generic-ehci";
515 reg = <0x30140000 0x20000>;
516 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru HCLK_HOST0>, <&u2phy>;
518 phys = <&u2phy_host>;
523 usb_host_ohci: usb@30160000 {
524 compatible = "generic-ohci";
525 reg = <0x30160000 0x20000>;
526 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cru HCLK_HOST0>, <&u2phy>;
528 phys = <&u2phy_host>;
533 usb_otg: usb@30180000 {
534 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
536 reg = <0x30180000 0x40000>;
537 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&cru HCLK_OTG>;
541 g-np-tx-fifo-size = <16>;
542 g-rx-fifo-size = <280>;
543 g-tx-fifo-size = <256 128 128 64 32 16>;
545 phy-names = "usb2-phy";
550 compatible = "rockchip,sfc";
551 reg = <0x301c0000 0x4000>;
552 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
554 clock-names = "clk_sfc", "hclk_sfc";
555 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
556 pinctrl-names = "default";
561 compatible = "rockchip,rv1108-gmac";
562 reg = <0x30200000 0x10000>;
563 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "macirq", "eth_wake_irq";
566 clocks = <&cru SCLK_MAC>,
567 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
568 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
569 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
570 clock-names = "stmmaceth",
571 "mac_clk_rx", "mac_clk_tx",
572 "clk_mac_ref", "clk_mac_refout",
573 "aclk_mac", "pclk_mac";
574 /* rv1108 only supports an rmii interface */
576 pinctrl-names = "default";
577 pinctrl-0 = <&rmii_pins>;
578 rockchip,grf = <&grf>;
582 gic: interrupt-controller@32010000 {
583 compatible = "arm,gic-400";
584 interrupt-controller;
585 #interrupt-cells = <3>;
586 #address-cells = <0>;
588 reg = <0x32011000 0x1000>,
592 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
596 compatible = "rockchip,rv1108-pinctrl";
597 rockchip,grf = <&grf>;
598 rockchip,pmu = <&pmugrf>;
599 #address-cells = <1>;
603 gpio0: gpio0@20030000 {
604 compatible = "rockchip,gpio-bank";
605 reg = <0x20030000 0x100>;
606 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cru PCLK_GPIO0_PMU>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
616 gpio1: gpio1@10310000 {
617 compatible = "rockchip,gpio-bank";
618 reg = <0x10310000 0x100>;
619 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&cru PCLK_GPIO1>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
629 gpio2: gpio2@10320000 {
630 compatible = "rockchip,gpio-bank";
631 reg = <0x10320000 0x100>;
632 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cru PCLK_GPIO2>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
642 gpio3: gpio3@10330000 {
643 compatible = "rockchip,gpio-bank";
644 reg = <0x10330000 0x100>;
645 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru PCLK_GPIO3>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
655 pcfg_pull_up: pcfg-pull-up {
659 pcfg_pull_down: pcfg-pull-down {
663 pcfg_pull_none: pcfg-pull-none {
667 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
668 drive-strength = <8>;
671 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
672 drive-strength = <12>;
675 pcfg_pull_none_smt: pcfg-pull-none-smt {
677 input-schmitt-enable;
680 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
682 drive-strength = <8>;
685 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
686 drive-strength = <4>;
689 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
691 drive-strength = <4>;
694 pcfg_output_high: pcfg-output-high {
698 pcfg_output_low: pcfg-output-low {
702 pcfg_input_high: pcfg-input-high {
708 emmc_bus8: emmc-bus8 {
709 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
710 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
711 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
712 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
713 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
714 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
715 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
716 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
720 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
724 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
731 <2 RK_PA0 3 &pcfg_pull_none>,
732 <2 RK_PA1 3 &pcfg_pull_none>,
733 <2 RK_PA2 3 &pcfg_pull_none>,
734 <2 RK_PA3 3 &pcfg_pull_none>;
739 <2 RK_PA0 3 &pcfg_pull_none>,
740 <2 RK_PA1 3 &pcfg_pull_none>;
745 <2 RK_PB4 3 &pcfg_pull_none>;
750 <2 RK_PB7 2 &pcfg_pull_none>;
755 rmii_pins: rmii-pins {
756 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
757 <1 RK_PC3 2 &pcfg_pull_none>,
758 <1 RK_PC4 2 &pcfg_pull_none>,
759 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
760 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
761 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
762 <1 RK_PB5 3 &pcfg_pull_none>,
763 <1 RK_PB6 3 &pcfg_pull_none>,
764 <1 RK_PB7 3 &pcfg_pull_none>,
765 <1 RK_PC2 3 &pcfg_pull_none>;
770 i2c0_xfer: i2c0-xfer {
771 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
772 <0 RK_PB2 1 &pcfg_pull_none_smt>;
777 i2c1_xfer: i2c1-xfer {
778 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
779 <2 RK_PD4 1 &pcfg_pull_up>;
784 i2c2m1_xfer: i2c2m1-xfer {
785 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
786 <0 RK_PC6 3 &pcfg_pull_none>;
789 i2c2m1_pins: i2c2m1-pins {
790 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
791 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
796 i2c2m05v_xfer: i2c2m05v-xfer {
797 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
798 <1 RK_PD4 2 &pcfg_pull_none>;
801 i2c2m05v_pins: i2c2m05v-pins {
802 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
803 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
808 i2c3_xfer: i2c3-xfer {
809 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
810 <0 RK_PC4 2 &pcfg_pull_none>;
816 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
822 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
828 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
834 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
840 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
846 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
852 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
858 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
863 sdmmc_clk: sdmmc-clk {
864 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
867 sdmmc_cmd: sdmmc-cmd {
868 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
872 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
875 sdmmc_bus1: sdmmc-bus1 {
876 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
879 sdmmc_bus4: sdmmc-bus4 {
880 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
881 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
882 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
883 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
888 spim0_clk: spim0-clk {
889 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
892 spim0_cs0: spim0-cs0 {
893 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
897 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
901 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
906 spim1_clk: spim1-clk {
907 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
910 spim1_cs0: spim1-cs0 {
911 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
915 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
919 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
925 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
929 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
934 uart0_xfer: uart0-xfer {
935 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
936 <3 RK_PA5 1 &pcfg_pull_none>;
939 uart0_cts: uart0-cts {
940 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
943 uart0_rts: uart0-rts {
944 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
947 uart0_rts_pin: uart0-rts-pin {
948 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
953 uart1_xfer: uart1-xfer {
954 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
955 <1 RK_PD2 1 &pcfg_pull_none>;
958 uart1_cts: uart1-cts {
959 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
962 uart1_rts: uart1-rts {
963 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
968 uart2m0_xfer: uart2m0-xfer {
969 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
970 <2 RK_PD1 1 &pcfg_pull_none>;
975 uart2m1_xfer: uart2m1-xfer {
976 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
977 <3 RK_PC2 2 &pcfg_pull_none>;
982 uart2_5v_cts: uart2_5v-cts {
983 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
986 uart2_5v_rts: uart2_5v-rts {
987 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;