arch/arm/boot/dts/rk3xxx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/soc/rockchip,boot-mode.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 ethernet0 = &emac;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 serial0 = &uart0;
  25                 serial1 = &uart1;
  26                 serial2 = &uart2;
  27                 serial3 = &uart3;
  28                 spi0 = &spi0;
  29                 spi1 = &spi1;
  30         };
  31
  32         xin24m: oscillator {
  33                 compatible = "fixed-clock";
  34                 clock-frequency = <24000000>;
  35                 #clock-cells = <0>;
  36                 clock-output-names = "xin24m";
  37         };
  38
  39         gpu: gpu@10090000 {
  40                 compatible = "arm,mali-400";
  41                 reg = <0x10090000 0x10000>;
  42                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
  43                 clock-names = "bus", "core";
  44                 assigned-clocks = <&cru ACLK_GPU>;
  45                 assigned-clock-rates = <100000000>;
  46                 resets = <&cru SRST_GPU>;
  47                 status = "disabled";
  48         };
  49
  50         vpu: video-codec@10104000 {
  51                 compatible = "rockchip,rk3066-vpu";
  52                 reg = <0x10104000 0x800>;
  53                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
  54                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  55                 interrupt-names = "vepu", "vdpu";
  56                 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
  57                          <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
  58                 clock-names = "aclk_vdpu", "hclk_vdpu",
  59                               "aclk_vepu", "hclk_vepu";
  60         };
  61
  62         L2: cache-controller@10138000 {
  63                 compatible = "arm,pl310-cache";
  64                 reg = <0x10138000 0x1000>;
  65                 cache-unified;
  66                 cache-level = <2>;
  67         };
  68
  69         scu@1013c000 {
  70                 compatible = "arm,cortex-a9-scu";
  71                 reg = <0x1013c000 0x100>;
  72         };
  73
  74         global_timer: global-timer@1013c200 {
  75                 compatible = "arm,cortex-a9-global-timer";
  76                 reg = <0x1013c200 0x20>;
  77                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  78                 clocks = <&cru CORE_PERI>;
  79         };
  80
  81         local_timer: local-timer@1013c600 {
  82                 compatible = "arm,cortex-a9-twd-timer";
  83                 reg = <0x1013c600 0x20>;
  84                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  85                 clocks = <&cru CORE_PERI>;
  86         };
  87
  88         gic: interrupt-controller@1013d000 {
  89                 compatible = "arm,cortex-a9-gic";
  90                 interrupt-controller;
  91                 #interrupt-cells = <3>;
  92                 reg = <0x1013d000 0x1000>,
  93                       <0x1013c100 0x0100>;
  94         };
  95
  96         uart0: serial@10124000 {
  97                 compatible = "snps,dw-apb-uart";
  98                 reg = <0x10124000 0x400>;
  99                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 100                 reg-shift = <2>;
 101                 reg-io-width = <1>;
 102                 clock-names = "baudclk", "apb_pclk";
 103                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 104                 status = "disabled";
 105         };
 106
 107         uart1: serial@10126000 {
 108                 compatible = "snps,dw-apb-uart";
 109                 reg = <0x10126000 0x400>;
 110                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 111                 reg-shift = <2>;
 112                 reg-io-width = <1>;
 113                 clock-names = "baudclk", "apb_pclk";
 114                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 115                 status = "disabled";
 116         };
 117
 118         qos_gpu: qos@1012d000 {
 119                 compatible = "rockchip,rk3066-qos", "syscon";
 120                 reg = <0x1012d000 0x20>;
 121         };
 122
 123         qos_vpu: qos@1012e000 {
 124                 compatible = "rockchip,rk3066-qos", "syscon";
 125                 reg = <0x1012e000 0x20>;
 126         };
 127
 128         qos_lcdc0: qos@1012f000 {
 129                 compatible = "rockchip,rk3066-qos", "syscon";
 130                 reg = <0x1012f000 0x20>;
 131         };
 132
 133         qos_cif0: qos@1012f080 {
 134                 compatible = "rockchip,rk3066-qos", "syscon";
 135                 reg = <0x1012f080 0x20>;
 136         };
 137
 138         qos_ipp: qos@1012f100 {
 139                 compatible = "rockchip,rk3066-qos", "syscon";
 140                 reg = <0x1012f100 0x20>;
 141         };
 142
 143         qos_lcdc1: qos@1012f180 {
 144                 compatible = "rockchip,rk3066-qos", "syscon";
 145                 reg = <0x1012f180 0x20>;
 146         };
 147
 148         qos_cif1: qos@1012f200 {
 149                 compatible = "rockchip,rk3066-qos", "syscon";
 150                 reg = <0x1012f200 0x20>;
 151         };
 152
 153         qos_rga: qos@1012f280 {
 154                 compatible = "rockchip,rk3066-qos", "syscon";
 155                 reg = <0x1012f280 0x20>;
 156         };
 157
 158         usb_otg: usb@10180000 {
 159                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 160                 reg = <0x10180000 0x40000>;
 161                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 162                 clocks = <&cru HCLK_OTG0>;
 163                 clock-names = "otg";
 164                 dr_mode = "otg";
 165                 g-np-tx-fifo-size = <16>;
 166                 g-rx-fifo-size = <275>;
 167                 g-tx-fifo-size = <256 128 128 64 64 32>;
 168                 phys = <&usbphy0>;
 169                 phy-names = "usb2-phy";
 170                 status = "disabled";
 171         };
 172
 173         usb_host: usb@101c0000 {
 174                 compatible = "snps,dwc2";
 175                 reg = <0x101c0000 0x40000>;
 176                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&cru HCLK_OTG1>;
 178                 clock-names = "otg";
 179                 dr_mode = "host";
 180                 phys = <&usbphy1>;
 181                 phy-names = "usb2-phy";
 182                 status = "disabled";
 183         };
 184
 185         emac: ethernet@10204000 {
 186                 compatible = "snps,arc-emac";
 187                 reg = <0x10204000 0x3c>;
 188                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 189
 190                 rockchip,grf = <&grf>;
 191
 192                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 193                 clock-names = "hclk", "macref";
 194                 max-speed = <100>;
 195                 phy-mode = "rmii";
 196
 197                 status = "disabled";
 198         };
 199
 200         mmc0: mmc@10214000 {
 201                 compatible = "rockchip,rk2928-dw-mshc";
 202                 reg = <0x10214000 0x1000>;
 203                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 205                 clock-names = "biu", "ciu";
 206                 dmas = <&dmac2 1>;
 207                 dma-names = "rx-tx";
 208                 fifo-depth = <256>;
 209                 resets = <&cru SRST_SDMMC>;
 210                 reset-names = "reset";
 211                 status = "disabled";
 212         };
 213
 214         mmc1: mmc@10218000 {
 215                 compatible = "rockchip,rk2928-dw-mshc";
 216                 reg = <0x10218000 0x1000>;
 217                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 219                 clock-names = "biu", "ciu";
 220                 dmas = <&dmac2 3>;
 221                 dma-names = "rx-tx";
 222                 fifo-depth = <256>;
 223                 resets = <&cru SRST_SDIO>;
 224                 reset-names = "reset";
 225                 status = "disabled";
 226         };
 227
 228         emmc: mmc@1021c000 {
 229                 compatible = "rockchip,rk2928-dw-mshc";
 230                 reg = <0x1021c000 0x1000>;
 231                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 233                 clock-names = "biu", "ciu";
 234                 dmas = <&dmac2 4>;
 235                 dma-names = "rx-tx";
 236                 fifo-depth = <256>;
 237                 resets = <&cru SRST_EMMC>;
 238                 reset-names = "reset";
 239                 status = "disabled";
 240         };
 241
 242         nfc: nand-controller@10500000 {
 243                 compatible = "rockchip,rk2928-nfc";
 244                 reg = <0x10500000 0x4000>;
 245                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&cru HCLK_NANDC0>;
 247                 clock-names = "ahb";
 248                 status = "disabled";
 249         };
 250
 251         pmu: pmu@20004000 {
 252                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 253                 reg = <0x20004000 0x100>;
 254
 255                 reboot-mode {
 256                         compatible = "syscon-reboot-mode";
 257                         offset = <0x40>;
 258                         mode-normal = <BOOT_NORMAL>;
 259                         mode-recovery = <BOOT_RECOVERY>;
 260                         mode-bootloader = <BOOT_FASTBOOT>;
 261                         mode-loader = <BOOT_BL_DOWNLOAD>;
 262                 };
 263         };
 264
 265         grf: grf@20008000 {
 266                 compatible = "syscon", "simple-mfd";
 267                 reg = <0x20008000 0x200>;
 268         };
 269
 270         dmac1_s: dma-controller@20018000 {
 271                 compatible = "arm,pl330", "arm,primecell";
 272                 reg = <0x20018000 0x4000>;
 273                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 275                 #dma-cells = <1>;
 276                 arm,pl330-broken-no-flushp;
 277                 arm,pl330-periph-burst;
 278                 clocks = <&cru ACLK_DMA1>;
 279                 clock-names = "apb_pclk";
 280         };
 281
 282         dmac1_ns: dma-controller@2001c000 {
 283                 compatible = "arm,pl330", "arm,primecell";
 284                 reg = <0x2001c000 0x4000>;
 285                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 287                 #dma-cells = <1>;
 288                 arm,pl330-broken-no-flushp;
 289                 arm,pl330-periph-burst;
 290                 clocks = <&cru ACLK_DMA1>;
 291                 clock-names = "apb_pclk";
 292                 status = "disabled";
 293         };
 294
 295         i2c0: i2c@2002d000 {
 296                 compatible = "rockchip,rk3066-i2c";
 297                 reg = <0x2002d000 0x1000>;
 298                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301
 302                 rockchip,grf = <&grf>;
 303
 304                 clock-names = "i2c";
 305                 clocks = <&cru PCLK_I2C0>;
 306
 307                 status = "disabled";
 308         };
 309
 310         i2c1: i2c@2002f000 {
 311                 compatible = "rockchip,rk3066-i2c";
 312                 reg = <0x2002f000 0x1000>;
 313                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316
 317                 rockchip,grf = <&grf>;
 318
 319                 clocks = <&cru PCLK_I2C1>;
 320                 clock-names = "i2c";
 321
 322                 status = "disabled";
 323         };
 324
 325         pwm0: pwm@20030000 {
 326                 compatible = "rockchip,rk2928-pwm";
 327                 reg = <0x20030000 0x10>;
 328                 #pwm-cells = <2>;
 329                 clocks = <&cru PCLK_PWM01>;
 330                 status = "disabled";
 331         };
 332
 333         pwm1: pwm@20030010 {
 334                 compatible = "rockchip,rk2928-pwm";
 335                 reg = <0x20030010 0x10>;
 336                 #pwm-cells = <2>;
 337                 clocks = <&cru PCLK_PWM01>;
 338                 status = "disabled";
 339         };
 340
 341         wdt: watchdog@2004c000 {
 342                 compatible = "snps,dw-wdt";
 343                 reg = <0x2004c000 0x100>;
 344                 clocks = <&cru PCLK_WDT>;
 345                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 346                 status = "disabled";
 347         };
 348
 349         pwm2: pwm@20050020 {
 350                 compatible = "rockchip,rk2928-pwm";
 351                 reg = <0x20050020 0x10>;
 352                 #pwm-cells = <2>;
 353                 clocks = <&cru PCLK_PWM23>;
 354                 status = "disabled";
 355         };
 356
 357         pwm3: pwm@20050030 {
 358                 compatible = "rockchip,rk2928-pwm";
 359                 reg = <0x20050030 0x10>;
 360                 #pwm-cells = <2>;
 361                 clocks = <&cru PCLK_PWM23>;
 362                 status = "disabled";
 363         };
 364
 365         i2c2: i2c@20056000 {
 366                 compatible = "rockchip,rk3066-i2c";
 367                 reg = <0x20056000 0x1000>;
 368                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371
 372                 rockchip,grf = <&grf>;
 373
 374                 clocks = <&cru PCLK_I2C2>;
 375                 clock-names = "i2c";
 376
 377                 status = "disabled";
 378         };
 379
 380         i2c3: i2c@2005a000 {
 381                 compatible = "rockchip,rk3066-i2c";
 382                 reg = <0x2005a000 0x1000>;
 383                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386
 387                 rockchip,grf = <&grf>;
 388
 389                 clocks = <&cru PCLK_I2C3>;
 390                 clock-names = "i2c";
 391
 392                 status = "disabled";
 393         };
 394
 395         i2c4: i2c@2005e000 {
 396                 compatible = "rockchip,rk3066-i2c";
 397                 reg = <0x2005e000 0x1000>;
 398                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401
 402                 rockchip,grf = <&grf>;
 403
 404                 clocks = <&cru PCLK_I2C4>;
 405                 clock-names = "i2c";
 406
 407                 status = "disabled";
 408         };
 409
 410         uart2: serial@20064000 {
 411                 compatible = "snps,dw-apb-uart";
 412                 reg = <0x20064000 0x400>;
 413                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <1>;
 416                 clock-names = "baudclk", "apb_pclk";
 417                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 418                 status = "disabled";
 419         };
 420
 421         uart3: serial@20068000 {
 422                 compatible = "snps,dw-apb-uart";
 423                 reg = <0x20068000 0x400>;
 424                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 425                 reg-shift = <2>;
 426                 reg-io-width = <1>;
 427                 clock-names = "baudclk", "apb_pclk";
 428                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 429                 status = "disabled";
 430         };
 431
 432         saradc: saradc@2006c000 {
 433                 compatible = "rockchip,saradc";
 434                 reg = <0x2006c000 0x100>;
 435                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 436                 #io-channel-cells = <1>;
 437                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 438                 clock-names = "saradc", "apb_pclk";
 439                 resets = <&cru SRST_SARADC>;
 440                 reset-names = "saradc-apb";
 441                 status = "disabled";
 442         };
 443
 444         spi0: spi@20070000 {
 445                 compatible = "rockchip,rk3066-spi";
 446                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 447                 clock-names = "spiclk", "apb_pclk";
 448                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 449                 reg = <0x20070000 0x1000>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 dmas = <&dmac2 10>, <&dmac2 11>;
 453                 dma-names = "tx", "rx";
 454                 status = "disabled";
 455         };
 456
 457         spi1: spi@20074000 {
 458                 compatible = "rockchip,rk3066-spi";
 459                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 460                 clock-names = "spiclk", "apb_pclk";
 461                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 462                 reg = <0x20074000 0x1000>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 dmas = <&dmac2 12>, <&dmac2 13>;
 466                 dma-names = "tx", "rx";
 467                 status = "disabled";
 468         };
 469
 470         dmac2: dma-controller@20078000 {
 471                 compatible = "arm,pl330", "arm,primecell";
 472                 reg = <0x20078000 0x4000>;
 473                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 474                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 475                 #dma-cells = <1>;
 476                 arm,pl330-broken-no-flushp;
 477                 arm,pl330-periph-burst;
 478                 clocks = <&cru ACLK_DMA2>;
 479                 clock-names = "apb_pclk";
 480         };
 481 };