1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
36 clock-output-names = "xin24m";
40 compatible = "arm,mali-400";
41 reg = <0x10090000 0x10000>;
42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
43 clock-names = "bus", "core";
44 assigned-clocks = <&cru ACLK_GPU>;
45 assigned-clock-rates = <100000000>;
46 resets = <&cru SRST_GPU>;
50 vpu: video-codec@10104000 {
51 compatible = "rockchip,rk3066-vpu";
52 reg = <0x10104000 0x800>;
53 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-names = "vepu", "vdpu";
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
58 clock-names = "aclk_vdpu", "hclk_vdpu",
59 "aclk_vepu", "hclk_vepu";
62 L2: cache-controller@10138000 {
63 compatible = "arm,pl310-cache";
64 reg = <0x10138000 0x1000>;
70 compatible = "arm,cortex-a9-scu";
71 reg = <0x1013c000 0x100>;
74 global_timer: global-timer@1013c200 {
75 compatible = "arm,cortex-a9-global-timer";
76 reg = <0x1013c200 0x20>;
77 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
78 clocks = <&cru CORE_PERI>;
81 local_timer: local-timer@1013c600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 reg = <0x1013c600 0x20>;
84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
85 clocks = <&cru CORE_PERI>;
88 gic: interrupt-controller@1013d000 {
89 compatible = "arm,cortex-a9-gic";
91 #interrupt-cells = <3>;
92 reg = <0x1013d000 0x1000>,
96 uart0: serial@10124000 {
97 compatible = "snps,dw-apb-uart";
98 reg = <0x10124000 0x400>;
99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
102 clock-names = "baudclk", "apb_pclk";
103 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
107 uart1: serial@10126000 {
108 compatible = "snps,dw-apb-uart";
109 reg = <0x10126000 0x400>;
110 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
113 clock-names = "baudclk", "apb_pclk";
114 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
118 qos_gpu: qos@1012d000 {
119 compatible = "rockchip,rk3066-qos", "syscon";
120 reg = <0x1012d000 0x20>;
123 qos_vpu: qos@1012e000 {
124 compatible = "rockchip,rk3066-qos", "syscon";
125 reg = <0x1012e000 0x20>;
128 qos_lcdc0: qos@1012f000 {
129 compatible = "rockchip,rk3066-qos", "syscon";
130 reg = <0x1012f000 0x20>;
133 qos_cif0: qos@1012f080 {
134 compatible = "rockchip,rk3066-qos", "syscon";
135 reg = <0x1012f080 0x20>;
138 qos_ipp: qos@1012f100 {
139 compatible = "rockchip,rk3066-qos", "syscon";
140 reg = <0x1012f100 0x20>;
143 qos_lcdc1: qos@1012f180 {
144 compatible = "rockchip,rk3066-qos", "syscon";
145 reg = <0x1012f180 0x20>;
148 qos_cif1: qos@1012f200 {
149 compatible = "rockchip,rk3066-qos", "syscon";
150 reg = <0x1012f200 0x20>;
153 qos_rga: qos@1012f280 {
154 compatible = "rockchip,rk3066-qos", "syscon";
155 reg = <0x1012f280 0x20>;
158 usb_otg: usb@10180000 {
159 compatible = "rockchip,rk3066-usb", "snps,dwc2";
160 reg = <0x10180000 0x40000>;
161 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&cru HCLK_OTG0>;
165 g-np-tx-fifo-size = <16>;
166 g-rx-fifo-size = <275>;
167 g-tx-fifo-size = <256 128 128 64 64 32>;
169 phy-names = "usb2-phy";
173 usb_host: usb@101c0000 {
174 compatible = "snps,dwc2";
175 reg = <0x101c0000 0x40000>;
176 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&cru HCLK_OTG1>;
181 phy-names = "usb2-phy";
185 emac: ethernet@10204000 {
186 compatible = "snps,arc-emac";
187 reg = <0x10204000 0x3c>;
188 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
189 #address-cells = <1>;
192 rockchip,grf = <&grf>;
194 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
195 clock-names = "hclk", "macref";
203 compatible = "rockchip,rk2928-dw-mshc";
204 reg = <0x10214000 0x1000>;
205 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
207 clock-names = "biu", "ciu";
211 resets = <&cru SRST_SDMMC>;
212 reset-names = "reset";
217 compatible = "rockchip,rk2928-dw-mshc";
218 reg = <0x10218000 0x1000>;
219 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
221 clock-names = "biu", "ciu";
225 resets = <&cru SRST_SDIO>;
226 reset-names = "reset";
231 compatible = "rockchip,rk2928-dw-mshc";
232 reg = <0x1021c000 0x1000>;
233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
235 clock-names = "biu", "ciu";
239 resets = <&cru SRST_EMMC>;
240 reset-names = "reset";
244 nfc: nand-controller@10500000 {
245 compatible = "rockchip,rk2928-nfc";
246 reg = <0x10500000 0x4000>;
247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru HCLK_NANDC0>;
254 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
255 reg = <0x20004000 0x100>;
258 compatible = "syscon-reboot-mode";
260 mode-normal = <BOOT_NORMAL>;
261 mode-recovery = <BOOT_RECOVERY>;
262 mode-bootloader = <BOOT_FASTBOOT>;
263 mode-loader = <BOOT_BL_DOWNLOAD>;
268 compatible = "syscon", "simple-mfd";
269 reg = <0x20008000 0x200>;
272 dmac1_s: dma-controller@20018000 {
273 compatible = "arm,pl330", "arm,primecell";
274 reg = <0x20018000 0x4000>;
275 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
278 arm,pl330-broken-no-flushp;
279 arm,pl330-periph-burst;
280 clocks = <&cru ACLK_DMA1>;
281 clock-names = "apb_pclk";
284 dmac1_ns: dma-controller@2001c000 {
285 compatible = "arm,pl330", "arm,primecell";
286 reg = <0x2001c000 0x4000>;
287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
290 arm,pl330-broken-no-flushp;
291 arm,pl330-periph-burst;
292 clocks = <&cru ACLK_DMA1>;
293 clock-names = "apb_pclk";
298 compatible = "rockchip,rk3066-i2c";
299 reg = <0x2002d000 0x1000>;
300 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
304 rockchip,grf = <&grf>;
307 clocks = <&cru PCLK_I2C0>;
313 compatible = "rockchip,rk3066-i2c";
314 reg = <0x2002f000 0x1000>;
315 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;
319 rockchip,grf = <&grf>;
321 clocks = <&cru PCLK_I2C1>;
328 compatible = "rockchip,rk2928-pwm";
329 reg = <0x20030000 0x10>;
331 clocks = <&cru PCLK_PWM01>;
336 compatible = "rockchip,rk2928-pwm";
337 reg = <0x20030010 0x10>;
339 clocks = <&cru PCLK_PWM01>;
343 wdt: watchdog@2004c000 {
344 compatible = "snps,dw-wdt";
345 reg = <0x2004c000 0x100>;
346 clocks = <&cru PCLK_WDT>;
347 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
352 compatible = "rockchip,rk2928-pwm";
353 reg = <0x20050020 0x10>;
355 clocks = <&cru PCLK_PWM23>;
360 compatible = "rockchip,rk2928-pwm";
361 reg = <0x20050030 0x10>;
363 clocks = <&cru PCLK_PWM23>;
368 compatible = "rockchip,rk3066-i2c";
369 reg = <0x20056000 0x1000>;
370 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
374 rockchip,grf = <&grf>;
376 clocks = <&cru PCLK_I2C2>;
383 compatible = "rockchip,rk3066-i2c";
384 reg = <0x2005a000 0x1000>;
385 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
389 rockchip,grf = <&grf>;
391 clocks = <&cru PCLK_I2C3>;
398 compatible = "rockchip,rk3066-i2c";
399 reg = <0x2005e000 0x1000>;
400 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
404 rockchip,grf = <&grf>;
406 clocks = <&cru PCLK_I2C4>;
412 uart2: serial@20064000 {
413 compatible = "snps,dw-apb-uart";
414 reg = <0x20064000 0x400>;
415 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
418 clock-names = "baudclk", "apb_pclk";
419 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
423 uart3: serial@20068000 {
424 compatible = "snps,dw-apb-uart";
425 reg = <0x20068000 0x400>;
426 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
429 clock-names = "baudclk", "apb_pclk";
430 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
434 saradc: saradc@2006c000 {
435 compatible = "rockchip,saradc";
436 reg = <0x2006c000 0x100>;
437 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
438 #io-channel-cells = <1>;
439 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
440 clock-names = "saradc", "apb_pclk";
441 resets = <&cru SRST_SARADC>;
442 reset-names = "saradc-apb";
447 compatible = "rockchip,rk3066-spi";
448 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
449 clock-names = "spiclk", "apb_pclk";
450 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
451 reg = <0x20070000 0x1000>;
452 #address-cells = <1>;
454 dmas = <&dmac2 10>, <&dmac2 11>;
455 dma-names = "tx", "rx";
460 compatible = "rockchip,rk3066-spi";
461 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
462 clock-names = "spiclk", "apb_pclk";
463 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
464 reg = <0x20074000 0x1000>;
465 #address-cells = <1>;
467 dmas = <&dmac2 12>, <&dmac2 13>;
468 dma-names = "tx", "rx";
472 dmac2: dma-controller@20078000 {
473 compatible = "arm,pl330", "arm,primecell";
474 reg = <0x20078000 0x4000>;
475 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
478 arm,pl330-broken-no-flushp;
479 arm,pl330-periph-burst;
480 clocks = <&cru ACLK_DMA2>;
481 clock-names = "apb_pclk";