2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
54 compatible = "rockchip,rk3288";
56 interrupt-parent = <&gic>;
81 compatible = "arm,cortex-a12-pmu";
82 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
92 enable-method = "rockchip,rk3066-smp";
93 rockchip,pmu = <&pmu>;
97 compatible = "arm,cortex-a12";
99 resets = <&cru SRST_CORE0>;
115 #cooling-cells = <2>; /* min followed by max */
116 clock-latency = <40000>;
117 clocks = <&cru ARMCLK>;
121 compatible = "arm,cortex-a12";
123 resets = <&cru SRST_CORE1>;
127 compatible = "arm,cortex-a12";
129 resets = <&cru SRST_CORE2>;
133 compatible = "arm,cortex-a12";
135 resets = <&cru SRST_CORE3>;
140 compatible = "simple-bus";
141 #address-cells = <1>;
145 dmac_peri: dma-controller@ff250000 {
146 compatible = "arm,pl330", "arm,primecell";
147 reg = <0xff250000 0x4000>;
148 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
151 arm,pl330-broken-no-flushp;
152 clocks = <&cru ACLK_DMAC2>;
153 clock-names = "apb_pclk";
156 dmac_bus_ns: dma-controller@ff600000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0xff600000 0x4000>;
159 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 arm,pl330-broken-no-flushp;
163 clocks = <&cru ACLK_DMAC1>;
164 clock-names = "apb_pclk";
168 dmac_bus_s: dma-controller@ffb20000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0xffb20000 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 arm,pl330-broken-no-flushp;
175 clocks = <&cru ACLK_DMAC1>;
176 clock-names = "apb_pclk";
181 #address-cells = <1>;
186 * The rk3288 cannot use the memory area above 0xfe000000
187 * for dma operations for some reason. While there is
188 * probably a better solution available somewhere, we
189 * haven't found it yet and while devices with 2GB of ram
190 * are not affected, this issue prevents 4GB from booting.
191 * So to make these devices at least bootable, block
192 * this area for the time being until the real solution
195 dma-unusable@fe000000 {
196 reg = <0xfe000000 0x1000000>;
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
208 compatible = "arm,armv7-timer";
209 arm,cpu-registers-not-fw-configured;
210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
214 clock-frequency = <24000000>;
217 timer: timer@ff810000 {
218 compatible = "rockchip,rk3288-timer";
219 reg = <0xff810000 0x20>;
220 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&xin24m>, <&cru PCLK_TIMER>;
222 clock-names = "timer", "pclk";
226 compatible = "rockchip,display-subsystem";
227 ports = <&vopl_out>, <&vopb_out>;
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3288-dw-mshc";
232 max-frequency = <150000000>;
233 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
234 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0xff0c0000 0x4000>;
239 resets = <&cru SRST_MMC0>;
240 reset-names = "reset";
244 sdio0: dwmmc@ff0d0000 {
245 compatible = "rockchip,rk3288-dw-mshc";
246 max-frequency = <150000000>;
247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
252 reg = <0xff0d0000 0x4000>;
253 resets = <&cru SRST_SDIO0>;
254 reset-names = "reset";
258 sdio1: dwmmc@ff0e0000 {
259 compatible = "rockchip,rk3288-dw-mshc";
260 max-frequency = <150000000>;
261 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
262 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
263 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
264 fifo-depth = <0x100>;
265 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
266 reg = <0xff0e0000 0x4000>;
267 resets = <&cru SRST_SDIO1>;
268 reset-names = "reset";
272 emmc: dwmmc@ff0f0000 {
273 compatible = "rockchip,rk3288-dw-mshc";
274 max-frequency = <150000000>;
275 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
276 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
277 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
278 fifo-depth = <0x100>;
279 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
280 reg = <0xff0f0000 0x4000>;
281 resets = <&cru SRST_EMMC>;
282 reset-names = "reset";
286 saradc: saradc@ff100000 {
287 compatible = "rockchip,saradc";
288 reg = <0xff100000 0x100>;
289 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
290 #io-channel-cells = <1>;
291 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
292 clock-names = "saradc", "apb_pclk";
293 resets = <&cru SRST_SARADC>;
294 reset-names = "saradc-apb";
299 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
300 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
301 clock-names = "spiclk", "apb_pclk";
302 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
303 dma-names = "tx", "rx";
304 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
307 reg = <0xff110000 0x1000>;
308 #address-cells = <1>;
314 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
315 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
316 clock-names = "spiclk", "apb_pclk";
317 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
318 dma-names = "tx", "rx";
319 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
322 reg = <0xff120000 0x1000>;
323 #address-cells = <1>;
329 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
330 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
331 clock-names = "spiclk", "apb_pclk";
332 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
333 dma-names = "tx", "rx";
334 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
337 reg = <0xff130000 0x1000>;
338 #address-cells = <1>;
344 compatible = "rockchip,rk3288-i2c";
345 reg = <0xff140000 0x1000>;
346 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
350 clocks = <&cru PCLK_I2C1>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c1_xfer>;
357 compatible = "rockchip,rk3288-i2c";
358 reg = <0xff150000 0x1000>;
359 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
363 clocks = <&cru PCLK_I2C3>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c3_xfer>;
370 compatible = "rockchip,rk3288-i2c";
371 reg = <0xff160000 0x1000>;
372 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
376 clocks = <&cru PCLK_I2C4>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c4_xfer>;
383 compatible = "rockchip,rk3288-i2c";
384 reg = <0xff170000 0x1000>;
385 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
389 clocks = <&cru PCLK_I2C5>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c5_xfer>;
395 uart0: serial@ff180000 {
396 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
397 reg = <0xff180000 0x100>;
398 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
402 clock-names = "baudclk", "apb_pclk";
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart0_xfer>;
408 uart1: serial@ff190000 {
409 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
410 reg = <0xff190000 0x100>;
411 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
415 clock-names = "baudclk", "apb_pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&uart1_xfer>;
421 uart2: serial@ff690000 {
422 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
423 reg = <0xff690000 0x100>;
424 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
428 clock-names = "baudclk", "apb_pclk";
429 pinctrl-names = "default";
430 pinctrl-0 = <&uart2_xfer>;
434 uart3: serial@ff1b0000 {
435 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
436 reg = <0xff1b0000 0x100>;
437 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
441 clock-names = "baudclk", "apb_pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart3_xfer>;
447 uart4: serial@ff1c0000 {
448 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
449 reg = <0xff1c0000 0x100>;
450 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
454 clock-names = "baudclk", "apb_pclk";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart4_xfer>;
461 reserve_thermal: reserve_thermal {
462 polling-delay-passive = <1000>; /* milliseconds */
463 polling-delay = <5000>; /* milliseconds */
465 thermal-sensors = <&tsadc 0>;
468 cpu_thermal: cpu_thermal {
469 polling-delay-passive = <100>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
472 thermal-sensors = <&tsadc 1>;
475 cpu_alert0: cpu_alert0 {
476 temperature = <70000>; /* millicelsius */
477 hysteresis = <2000>; /* millicelsius */
480 cpu_alert1: cpu_alert1 {
481 temperature = <75000>; /* millicelsius */
482 hysteresis = <2000>; /* millicelsius */
486 temperature = <90000>; /* millicelsius */
487 hysteresis = <2000>; /* millicelsius */
494 trip = <&cpu_alert0>;
496 <&cpu0 THERMAL_NO_LIMIT 6>;
499 trip = <&cpu_alert1>;
501 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
506 gpu_thermal: gpu_thermal {
507 polling-delay-passive = <100>; /* milliseconds */
508 polling-delay = <5000>; /* milliseconds */
510 thermal-sensors = <&tsadc 2>;
513 gpu_alert0: gpu_alert0 {
514 temperature = <70000>; /* millicelsius */
515 hysteresis = <2000>; /* millicelsius */
519 temperature = <90000>; /* millicelsius */
520 hysteresis = <2000>; /* millicelsius */
527 trip = <&gpu_alert0>;
529 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
535 tsadc: tsadc@ff280000 {
536 compatible = "rockchip,rk3288-tsadc";
537 reg = <0xff280000 0x100>;
538 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
540 clock-names = "tsadc", "apb_pclk";
541 resets = <&cru SRST_TSADC>;
542 reset-names = "tsadc-apb";
543 pinctrl-names = "init", "default", "sleep";
544 pinctrl-0 = <&otp_gpio>;
545 pinctrl-1 = <&otp_out>;
546 pinctrl-2 = <&otp_gpio>;
547 #thermal-sensor-cells = <1>;
548 rockchip,hw-tshut-temp = <95000>;
552 gmac: ethernet@ff290000 {
553 compatible = "rockchip,rk3288-gmac";
554 reg = <0xff290000 0x10000>;
555 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "macirq", "eth_wake_irq";
558 rockchip,grf = <&grf>;
559 clocks = <&cru SCLK_MAC>,
560 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
561 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
562 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
563 clock-names = "stmmaceth",
564 "mac_clk_rx", "mac_clk_tx",
565 "clk_mac_ref", "clk_mac_refout",
566 "aclk_mac", "pclk_mac";
567 resets = <&cru SRST_MAC>;
568 reset-names = "stmmaceth";
572 usb_host0_ehci: usb@ff500000 {
573 compatible = "generic-ehci";
574 reg = <0xff500000 0x100>;
575 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cru HCLK_USBHOST0>;
577 clock-names = "usbhost";
583 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
585 usb_host1: usb@ff540000 {
586 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
588 reg = <0xff540000 0x40000>;
589 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cru HCLK_USBHOST1>;
594 phy-names = "usb2-phy";
598 usb_otg: usb@ff580000 {
599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
601 reg = <0xff580000 0x40000>;
602 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru HCLK_OTG0>;
606 g-np-tx-fifo-size = <16>;
607 g-rx-fifo-size = <275>;
608 g-tx-fifo-size = <256 128 128 64 64 32>;
610 phy-names = "usb2-phy";
614 usb_hsic: usb@ff5c0000 {
615 compatible = "generic-ehci";
616 reg = <0xff5c0000 0x100>;
617 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&cru HCLK_HSIC>;
619 clock-names = "usbhost";
624 compatible = "rockchip,rk3288-i2c";
625 reg = <0xff650000 0x1000>;
626 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
627 #address-cells = <1>;
630 clocks = <&cru PCLK_I2C0>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&i2c0_xfer>;
637 compatible = "rockchip,rk3288-i2c";
638 reg = <0xff660000 0x1000>;
639 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
640 #address-cells = <1>;
643 clocks = <&cru PCLK_I2C2>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&i2c2_xfer>;
650 compatible = "rockchip,rk3288-pwm";
651 reg = <0xff680000 0x10>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&pwm0_pin>;
655 clocks = <&cru PCLK_PWM>;
661 compatible = "rockchip,rk3288-pwm";
662 reg = <0xff680010 0x10>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&pwm1_pin>;
666 clocks = <&cru PCLK_PWM>;
672 compatible = "rockchip,rk3288-pwm";
673 reg = <0xff680020 0x10>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&pwm2_pin>;
677 clocks = <&cru PCLK_PWM>;
683 compatible = "rockchip,rk3288-pwm";
684 reg = <0xff680030 0x10>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pwm3_pin>;
688 clocks = <&cru PCLK_PWM>;
693 bus_intmem@ff700000 {
694 compatible = "mmio-sram";
695 reg = <0xff700000 0x18000>;
696 #address-cells = <1>;
698 ranges = <0 0xff700000 0x18000>;
700 compatible = "rockchip,rk3066-smp-sram";
706 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
707 reg = <0xff720000 0x1000>;
710 pmu: power-management@ff730000 {
711 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
712 reg = <0xff730000 0x100>;
714 power: power-controller {
715 compatible = "rockchip,rk3288-power-controller";
716 #power-domain-cells = <1>;
717 #address-cells = <1>;
720 assigned-clocks = <&cru SCLK_EDP_24M>;
721 assigned-clock-parents = <&xin24m>;
724 * Note: Although SCLK_* are the working clocks
725 * of device without including on the NOC, needed for
728 * The clocks on the which NOC:
729 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
730 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
731 * ACLK_RGA is on ACLK_RGA_NIU.
732 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
734 * Which clock are device clocks:
736 * *_IEP IEP:Image Enhancement Processor
737 * *_ISP ISP:Image Signal Processing
738 * *_VIP VIP:Video Input Processor
739 * *_VOP* VOP:Visual Output Processor
746 pd_vio@RK3288_PD_VIO {
747 reg = <RK3288_PD_VIO>;
748 clocks = <&cru ACLK_IEP>,
762 <&cru PCLK_EDP_CTRL>,
763 <&cru PCLK_HDMI_CTRL>,
764 <&cru PCLK_LVDS_PHY>,
765 <&cru PCLK_MIPI_CSI>,
766 <&cru PCLK_MIPI_DSI0>,
767 <&cru PCLK_MIPI_DSI1>,
773 pm_qos = <&qos_vio0_iep>,
785 * Note: The following 3 are HEVC(H.265) clocks,
786 * and on the ACLK_HEVC_NIU (NOC).
788 pd_hevc@RK3288_PD_HEVC {
789 reg = <RK3288_PD_HEVC>;
790 clocks = <&cru ACLK_HEVC>,
791 <&cru SCLK_HEVC_CABAC>,
792 <&cru SCLK_HEVC_CORE>;
793 pm_qos = <&qos_hevc_r>,
798 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
799 * (video endecoder & decoder) clocks that on the
800 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
802 pd_video@RK3288_PD_VIDEO {
803 reg = <RK3288_PD_VIDEO>;
804 clocks = <&cru ACLK_VCODEC>,
806 pm_qos = <&qos_video>;
810 * Note: ACLK_GPU is the GPU clock,
811 * and on the ACLK_GPU_NIU (NOC).
813 pd_gpu@RK3288_PD_GPU {
814 reg = <RK3288_PD_GPU>;
815 clocks = <&cru ACLK_GPU>;
816 pm_qos = <&qos_gpu_r>,
822 compatible = "syscon-reboot-mode";
824 mode-normal = <BOOT_NORMAL>;
825 mode-recovery = <BOOT_RECOVERY>;
826 mode-bootloader = <BOOT_FASTBOOT>;
827 mode-loader = <BOOT_BL_DOWNLOAD>;
831 sgrf: syscon@ff740000 {
832 compatible = "rockchip,rk3288-sgrf", "syscon";
833 reg = <0xff740000 0x1000>;
836 cru: clock-controller@ff760000 {
837 compatible = "rockchip,rk3288-cru";
838 reg = <0xff760000 0x1000>;
839 rockchip,grf = <&grf>;
842 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
843 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
844 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
845 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
847 assigned-clock-rates = <594000000>, <400000000>,
848 <500000000>, <300000000>,
849 <150000000>, <75000000>,
850 <300000000>, <150000000>,
854 grf: syscon@ff770000 {
855 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
856 reg = <0xff770000 0x1000>;
859 compatible = "rockchip,rk3288-dp-phy";
860 clocks = <&cru SCLK_EDP_24M>;
866 io_domains: io-domains {
867 compatible = "rockchip,rk3288-io-voltage-domain";
872 compatible = "rockchip,rk3288-usb-phy";
873 #address-cells = <1>;
877 usbphy0: usb-phy@320 {
880 clocks = <&cru SCLK_OTGPHY0>;
881 clock-names = "phyclk";
885 usbphy1: usb-phy@334 {
888 clocks = <&cru SCLK_OTGPHY1>;
889 clock-names = "phyclk";
893 usbphy2: usb-phy@348 {
896 clocks = <&cru SCLK_OTGPHY2>;
897 clock-names = "phyclk";
903 wdt: watchdog@ff800000 {
904 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
905 reg = <0xff800000 0x100>;
906 clocks = <&cru PCLK_WDT>;
907 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
911 spdif: sound@ff88b0000 {
912 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
913 reg = <0xff8b0000 0x10000>;
914 #sound-dai-cells = <0>;
915 clock-names = "hclk", "mclk";
916 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
917 dmas = <&dmac_bus_s 3>;
919 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
920 pinctrl-names = "default";
921 pinctrl-0 = <&spdif_tx>;
922 rockchip,grf = <&grf>;
927 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
928 reg = <0xff890000 0x10000>;
929 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
930 #address-cells = <1>;
932 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
933 dma-names = "tx", "rx";
934 clock-names = "i2s_hclk", "i2s_clk";
935 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&i2s0_bus>;
938 rockchip,playback-channels = <8>;
939 rockchip,capture-channels = <2>;
943 crypto: cypto-controller@ff8a0000 {
944 compatible = "rockchip,rk3288-crypto";
945 reg = <0xff8a0000 0x4000>;
946 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
948 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
949 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
950 resets = <&cru SRST_CRYPTO>;
951 reset-names = "crypto-rst";
956 compatible = "rockchip,rk3288-vop";
957 reg = <0xff930000 0x19c>;
958 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
960 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
961 power-domains = <&power RK3288_PD_VIO>;
962 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
963 reset-names = "axi", "ahb", "dclk";
964 iommus = <&vopb_mmu>;
968 #address-cells = <1>;
971 vopb_out_hdmi: endpoint@0 {
973 remote-endpoint = <&hdmi_in_vopb>;
976 vopb_out_edp: endpoint@1 {
978 remote-endpoint = <&edp_in_vopb>;
981 vopb_out_mipi: endpoint@2 {
983 remote-endpoint = <&mipi_in_vopb>;
988 vopb_mmu: iommu@ff930300 {
989 compatible = "rockchip,iommu";
990 reg = <0xff930300 0x100>;
991 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
992 interrupt-names = "vopb_mmu";
993 power-domains = <&power RK3288_PD_VIO>;
999 compatible = "rockchip,rk3288-vop";
1000 reg = <0xff940000 0x19c>;
1001 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1003 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1004 power-domains = <&power RK3288_PD_VIO>;
1005 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1006 reset-names = "axi", "ahb", "dclk";
1007 iommus = <&vopl_mmu>;
1008 status = "disabled";
1011 #address-cells = <1>;
1014 vopl_out_hdmi: endpoint@0 {
1016 remote-endpoint = <&hdmi_in_vopl>;
1019 vopl_out_edp: endpoint@1 {
1021 remote-endpoint = <&edp_in_vopl>;
1024 vopl_out_mipi: endpoint@2 {
1026 remote-endpoint = <&mipi_in_vopl>;
1031 vopl_mmu: iommu@ff940300 {
1032 compatible = "rockchip,iommu";
1033 reg = <0xff940300 0x100>;
1034 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1035 interrupt-names = "vopl_mmu";
1036 power-domains = <&power RK3288_PD_VIO>;
1038 status = "disabled";
1041 mipi_dsi: mipi@ff960000 {
1042 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1043 reg = <0xff960000 0x4000>;
1044 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1046 clock-names = "ref", "pclk";
1047 power-domains = <&power RK3288_PD_VIO>;
1048 rockchip,grf = <&grf>;
1049 #address-cells = <1>;
1051 status = "disabled";
1055 #address-cells = <1>;
1057 mipi_in_vopb: endpoint@0 {
1059 remote-endpoint = <&vopb_out_mipi>;
1061 mipi_in_vopl: endpoint@1 {
1063 remote-endpoint = <&vopl_out_mipi>;
1070 compatible = "rockchip,rk3288-dp";
1071 reg = <0xff970000 0x4000>;
1072 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1074 clock-names = "dp", "pclk";
1077 resets = <&cru SRST_EDP>;
1079 rockchip,grf = <&grf>;
1080 status = "disabled";
1083 #address-cells = <1>;
1087 #address-cells = <1>;
1089 edp_in_vopb: endpoint@0 {
1091 remote-endpoint = <&vopb_out_edp>;
1093 edp_in_vopl: endpoint@1 {
1095 remote-endpoint = <&vopl_out_edp>;
1101 hdmi: hdmi@ff980000 {
1102 compatible = "rockchip,rk3288-dw-hdmi";
1103 reg = <0xff980000 0x20000>;
1105 rockchip,grf = <&grf>;
1106 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1108 clock-names = "iahb", "isfr";
1109 power-domains = <&power RK3288_PD_VIO>;
1110 status = "disabled";
1114 #address-cells = <1>;
1116 hdmi_in_vopb: endpoint@0 {
1118 remote-endpoint = <&vopb_out_hdmi>;
1120 hdmi_in_vopl: endpoint@1 {
1122 remote-endpoint = <&vopl_out_hdmi>;
1128 qos_gpu_r: qos@ffaa0000 {
1129 compatible = "syscon";
1130 reg = <0xffaa0000 0x20>;
1133 qos_gpu_w: qos@ffaa0080 {
1134 compatible = "syscon";
1135 reg = <0xffaa0080 0x20>;
1138 qos_vio1_vop: qos@ffad0000 {
1139 compatible = "syscon";
1140 reg = <0xffad0000 0x20>;
1143 qos_vio1_isp_w0: qos@ffad0100 {
1144 compatible = "syscon";
1145 reg = <0xffad0100 0x20>;
1148 qos_vio1_isp_w1: qos@ffad0180 {
1149 compatible = "syscon";
1150 reg = <0xffad0180 0x20>;
1153 qos_vio0_vop: qos@ffad0400 {
1154 compatible = "syscon";
1155 reg = <0xffad0400 0x20>;
1158 qos_vio0_vip: qos@ffad0480 {
1159 compatible = "syscon";
1160 reg = <0xffad0480 0x20>;
1163 qos_vio0_iep: qos@ffad0500 {
1164 compatible = "syscon";
1165 reg = <0xffad0500 0x20>;
1168 qos_vio2_rga_r: qos@ffad0800 {
1169 compatible = "syscon";
1170 reg = <0xffad0800 0x20>;
1173 qos_vio2_rga_w: qos@ffad0880 {
1174 compatible = "syscon";
1175 reg = <0xffad0880 0x20>;
1178 qos_vio1_isp_r: qos@ffad0900 {
1179 compatible = "syscon";
1180 reg = <0xffad0900 0x20>;
1183 qos_video: qos@ffae0000 {
1184 compatible = "syscon";
1185 reg = <0xffae0000 0x20>;
1188 qos_hevc_r: qos@ffaf0000 {
1189 compatible = "syscon";
1190 reg = <0xffaf0000 0x20>;
1193 qos_hevc_w: qos@ffaf0080 {
1194 compatible = "syscon";
1195 reg = <0xffaf0080 0x20>;
1198 gic: interrupt-controller@ffc01000 {
1199 compatible = "arm,gic-400";
1200 interrupt-controller;
1201 #interrupt-cells = <3>;
1202 #address-cells = <0>;
1204 reg = <0xffc01000 0x1000>,
1205 <0xffc02000 0x2000>,
1206 <0xffc04000 0x2000>,
1207 <0xffc06000 0x2000>;
1208 interrupts = <GIC_PPI 9 0xf04>;
1211 efuse: efuse@ffb40000 {
1212 compatible = "rockchip,rk3288-efuse";
1213 reg = <0xffb40000 0x20>;
1214 #address-cells = <1>;
1216 clocks = <&cru PCLK_EFUSE256>;
1217 clock-names = "pclk_efuse";
1219 cpu_leakage: cpu_leakage@17 {
1225 compatible = "rockchip,rk3288-pinctrl";
1226 rockchip,grf = <&grf>;
1227 rockchip,pmu = <&pmu>;
1228 #address-cells = <1>;
1232 gpio0: gpio0@ff750000 {
1233 compatible = "rockchip,gpio-bank";
1234 reg = <0xff750000 0x100>;
1235 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&cru PCLK_GPIO0>;
1241 interrupt-controller;
1242 #interrupt-cells = <2>;
1245 gpio1: gpio1@ff780000 {
1246 compatible = "rockchip,gpio-bank";
1247 reg = <0xff780000 0x100>;
1248 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&cru PCLK_GPIO1>;
1254 interrupt-controller;
1255 #interrupt-cells = <2>;
1258 gpio2: gpio2@ff790000 {
1259 compatible = "rockchip,gpio-bank";
1260 reg = <0xff790000 0x100>;
1261 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cru PCLK_GPIO2>;
1267 interrupt-controller;
1268 #interrupt-cells = <2>;
1271 gpio3: gpio3@ff7a0000 {
1272 compatible = "rockchip,gpio-bank";
1273 reg = <0xff7a0000 0x100>;
1274 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&cru PCLK_GPIO3>;
1280 interrupt-controller;
1281 #interrupt-cells = <2>;
1284 gpio4: gpio4@ff7b0000 {
1285 compatible = "rockchip,gpio-bank";
1286 reg = <0xff7b0000 0x100>;
1287 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cru PCLK_GPIO4>;
1293 interrupt-controller;
1294 #interrupt-cells = <2>;
1297 gpio5: gpio5@ff7c0000 {
1298 compatible = "rockchip,gpio-bank";
1299 reg = <0xff7c0000 0x100>;
1300 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1301 clocks = <&cru PCLK_GPIO5>;
1306 interrupt-controller;
1307 #interrupt-cells = <2>;
1310 gpio6: gpio6@ff7d0000 {
1311 compatible = "rockchip,gpio-bank";
1312 reg = <0xff7d0000 0x100>;
1313 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&cru PCLK_GPIO6>;
1319 interrupt-controller;
1320 #interrupt-cells = <2>;
1323 gpio7: gpio7@ff7e0000 {
1324 compatible = "rockchip,gpio-bank";
1325 reg = <0xff7e0000 0x100>;
1326 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1327 clocks = <&cru PCLK_GPIO7>;
1332 interrupt-controller;
1333 #interrupt-cells = <2>;
1336 gpio8: gpio8@ff7f0000 {
1337 compatible = "rockchip,gpio-bank";
1338 reg = <0xff7f0000 0x100>;
1339 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&cru PCLK_GPIO8>;
1345 interrupt-controller;
1346 #interrupt-cells = <2>;
1350 hdmi_ddc: hdmi-ddc {
1351 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1352 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1356 pcfg_pull_up: pcfg-pull-up {
1360 pcfg_pull_down: pcfg-pull-down {
1364 pcfg_pull_none: pcfg-pull-none {
1368 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1370 drive-strength = <12>;
1374 global_pwroff: global-pwroff {
1375 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1378 ddrio_pwroff: ddrio-pwroff {
1379 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1382 ddr0_retention: ddr0-retention {
1383 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1386 ddr1_retention: ddr1-retention {
1387 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1393 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1398 i2c0_xfer: i2c0-xfer {
1399 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1400 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1405 i2c1_xfer: i2c1-xfer {
1406 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1407 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1412 i2c2_xfer: i2c2-xfer {
1413 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1414 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1419 i2c3_xfer: i2c3-xfer {
1420 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1421 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1426 i2c4_xfer: i2c4-xfer {
1427 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1428 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1433 i2c5_xfer: i2c5-xfer {
1434 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1435 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1440 i2s0_bus: i2s0-bus {
1441 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1442 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1443 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1444 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1445 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1446 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1451 sdmmc_clk: sdmmc-clk {
1452 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1455 sdmmc_cmd: sdmmc-cmd {
1456 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1459 sdmmc_cd: sdmmc-cd {
1460 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1463 sdmmc_bus1: sdmmc-bus1 {
1464 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1467 sdmmc_bus4: sdmmc-bus4 {
1468 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1469 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1470 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1471 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1476 sdio0_bus1: sdio0-bus1 {
1477 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1480 sdio0_bus4: sdio0-bus4 {
1481 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1482 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1483 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1484 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1487 sdio0_cmd: sdio0-cmd {
1488 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1491 sdio0_clk: sdio0-clk {
1492 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1495 sdio0_cd: sdio0-cd {
1496 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1499 sdio0_wp: sdio0-wp {
1500 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1503 sdio0_pwr: sdio0-pwr {
1504 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1507 sdio0_bkpwr: sdio0-bkpwr {
1508 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1511 sdio0_int: sdio0-int {
1512 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1517 sdio1_bus1: sdio1-bus1 {
1518 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1521 sdio1_bus4: sdio1-bus4 {
1522 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1523 <3 25 4 &pcfg_pull_up>,
1524 <3 26 4 &pcfg_pull_up>,
1525 <3 27 4 &pcfg_pull_up>;
1528 sdio1_cd: sdio1-cd {
1529 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1532 sdio1_wp: sdio1-wp {
1533 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1536 sdio1_bkpwr: sdio1-bkpwr {
1537 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1540 sdio1_int: sdio1-int {
1541 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1544 sdio1_cmd: sdio1-cmd {
1545 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1548 sdio1_clk: sdio1-clk {
1549 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1552 sdio1_pwr: sdio1-pwr {
1553 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1558 emmc_clk: emmc-clk {
1559 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1562 emmc_cmd: emmc-cmd {
1563 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1566 emmc_pwr: emmc-pwr {
1567 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1570 emmc_bus1: emmc-bus1 {
1571 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1574 emmc_bus4: emmc-bus4 {
1575 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1576 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1577 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1578 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1581 emmc_bus8: emmc-bus8 {
1582 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1583 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1584 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1585 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1586 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1587 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1588 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1589 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1594 spi0_clk: spi0-clk {
1595 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1597 spi0_cs0: spi0-cs0 {
1598 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1601 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1604 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1606 spi0_cs1: spi0-cs1 {
1607 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1611 spi1_clk: spi1-clk {
1612 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1614 spi1_cs0: spi1-cs0 {
1615 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1618 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1621 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1626 spi2_cs1: spi2-cs1 {
1627 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1629 spi2_clk: spi2-clk {
1630 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1632 spi2_cs0: spi2-cs0 {
1633 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1636 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1639 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1644 uart0_xfer: uart0-xfer {
1645 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1646 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1649 uart0_cts: uart0-cts {
1650 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1653 uart0_rts: uart0-rts {
1654 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1659 uart1_xfer: uart1-xfer {
1660 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1661 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1664 uart1_cts: uart1-cts {
1665 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1668 uart1_rts: uart1-rts {
1669 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1674 uart2_xfer: uart2-xfer {
1675 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1676 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1678 /* no rts / cts for uart2 */
1682 uart3_xfer: uart3-xfer {
1683 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1684 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1687 uart3_cts: uart3-cts {
1688 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1691 uart3_rts: uart3-rts {
1692 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1697 uart4_xfer: uart4-xfer {
1698 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1699 <5 13 3 &pcfg_pull_none>;
1702 uart4_cts: uart4-cts {
1703 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1706 uart4_rts: uart4-rts {
1707 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1712 otp_gpio: otp-gpio {
1713 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1717 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1722 pwm0_pin: pwm0-pin {
1723 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1728 pwm1_pin: pwm1-pin {
1729 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1734 pwm2_pin: pwm2-pin {
1735 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1740 pwm3_pin: pwm3-pin {
1741 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1746 rgmii_pins: rgmii-pins {
1747 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1748 <3 31 3 &pcfg_pull_none>,
1749 <3 26 3 &pcfg_pull_none>,
1750 <3 27 3 &pcfg_pull_none>,
1751 <3 28 3 &pcfg_pull_none_12ma>,
1752 <3 29 3 &pcfg_pull_none_12ma>,
1753 <3 24 3 &pcfg_pull_none_12ma>,
1754 <3 25 3 &pcfg_pull_none_12ma>,
1755 <4 0 3 &pcfg_pull_none>,
1756 <4 5 3 &pcfg_pull_none>,
1757 <4 6 3 &pcfg_pull_none>,
1758 <4 9 3 &pcfg_pull_none_12ma>,
1759 <4 4 3 &pcfg_pull_none_12ma>,
1760 <4 1 3 &pcfg_pull_none>,
1761 <4 3 3 &pcfg_pull_none>;
1764 rmii_pins: rmii-pins {
1765 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1766 <3 31 3 &pcfg_pull_none>,
1767 <3 28 3 &pcfg_pull_none>,
1768 <3 29 3 &pcfg_pull_none>,
1769 <4 0 3 &pcfg_pull_none>,
1770 <4 5 3 &pcfg_pull_none>,
1771 <4 4 3 &pcfg_pull_none>,
1772 <4 1 3 &pcfg_pull_none>,
1773 <4 2 3 &pcfg_pull_none>,
1774 <4 3 3 &pcfg_pull_none>;
1779 spdif_tx: spdif-tx {
1780 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;