1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
16 compatible = "rockchip,rk3288";
18 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a12-pmu";
44 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
54 enable-method = "rockchip,rk3066-smp";
55 rockchip,pmu = <&pmu>;
59 compatible = "arm,cortex-a12";
61 resets = <&cru SRST_CORE0>;
62 operating-points-v2 = <&cpu_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
65 clocks = <&cru ARMCLK>;
66 dynamic-power-coefficient = <370>;
70 compatible = "arm,cortex-a12";
72 resets = <&cru SRST_CORE1>;
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
76 clocks = <&cru ARMCLK>;
77 dynamic-power-coefficient = <370>;
81 compatible = "arm,cortex-a12";
83 resets = <&cru SRST_CORE2>;
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>; /* min followed by max */
86 clock-latency = <40000>;
87 clocks = <&cru ARMCLK>;
88 dynamic-power-coefficient = <370>;
92 compatible = "arm,cortex-a12";
94 resets = <&cru SRST_CORE3>;
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>; /* min followed by max */
97 clock-latency = <40000>;
98 clocks = <&cru ARMCLK>;
99 dynamic-power-coefficient = <370>;
103 cpu_opp_table: cpu-opp-table {
104 compatible = "operating-points-v2";
108 opp-hz = /bits/ 64 <126000000>;
109 opp-microvolt = <900000>;
112 opp-hz = /bits/ 64 <216000000>;
113 opp-microvolt = <900000>;
116 opp-hz = /bits/ 64 <312000000>;
117 opp-microvolt = <900000>;
120 opp-hz = /bits/ 64 <408000000>;
121 opp-microvolt = <900000>;
124 opp-hz = /bits/ 64 <600000000>;
125 opp-microvolt = <900000>;
128 opp-hz = /bits/ 64 <696000000>;
129 opp-microvolt = <950000>;
132 opp-hz = /bits/ 64 <816000000>;
133 opp-microvolt = <1000000>;
136 opp-hz = /bits/ 64 <1008000000>;
137 opp-microvolt = <1050000>;
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1100000>;
144 opp-hz = /bits/ 64 <1416000000>;
145 opp-microvolt = <1200000>;
148 opp-hz = /bits/ 64 <1512000000>;
149 opp-microvolt = <1300000>;
152 opp-hz = /bits/ 64 <1608000000>;
153 opp-microvolt = <1350000>;
158 #address-cells = <2>;
163 * The rk3288 cannot use the memory area above 0xfe000000
164 * for dma operations for some reason. While there is
165 * probably a better solution available somewhere, we
166 * haven't found it yet and while devices with 2GB of ram
167 * are not affected, this issue prevents 4GB from booting.
168 * So to make these devices at least bootable, block
169 * this area for the time being until the real solution
172 dma-unusable@fe000000 {
173 reg = <0x0 0xfe000000 0x0 0x1000000>;
178 compatible = "fixed-clock";
179 clock-frequency = <24000000>;
180 clock-output-names = "xin24m";
185 compatible = "arm,armv7-timer";
186 arm,cpu-registers-not-fw-configured;
187 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
188 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
189 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
190 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
191 clock-frequency = <24000000>;
192 arm,no-tick-in-suspend;
195 timer: timer@ff810000 {
196 compatible = "rockchip,rk3288-timer";
197 reg = <0x0 0xff810000 0x0 0x20>;
198 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
200 clock-names = "pclk", "timer";
204 compatible = "rockchip,display-subsystem";
205 ports = <&vopl_out>, <&vopb_out>;
208 sdmmc: mmc@ff0c0000 {
209 compatible = "rockchip,rk3288-dw-mshc";
210 max-frequency = <150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
216 reg = <0x0 0xff0c0000 0x0 0x4000>;
217 resets = <&cru SRST_MMC0>;
218 reset-names = "reset";
222 sdio0: mmc@ff0d0000 {
223 compatible = "rockchip,rk3288-dw-mshc";
224 max-frequency = <150000000>;
225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
230 reg = <0x0 0xff0d0000 0x0 0x4000>;
231 resets = <&cru SRST_SDIO0>;
232 reset-names = "reset";
236 sdio1: mmc@ff0e0000 {
237 compatible = "rockchip,rk3288-dw-mshc";
238 max-frequency = <150000000>;
239 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
240 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
244 reg = <0x0 0xff0e0000 0x0 0x4000>;
245 resets = <&cru SRST_SDIO1>;
246 reset-names = "reset";
251 compatible = "rockchip,rk3288-dw-mshc";
252 max-frequency = <150000000>;
253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0x0 0xff0f0000 0x0 0x4000>;
259 resets = <&cru SRST_EMMC>;
260 reset-names = "reset";
264 saradc: saradc@ff100000 {
265 compatible = "rockchip,saradc";
266 reg = <0x0 0xff100000 0x0 0x100>;
267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
268 #io-channel-cells = <1>;
269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
270 clock-names = "saradc", "apb_pclk";
271 resets = <&cru SRST_SARADC>;
272 reset-names = "saradc-apb";
277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
279 clock-names = "spiclk", "apb_pclk";
280 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
281 dma-names = "tx", "rx";
282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
285 reg = <0x0 0xff110000 0x0 0x1000>;
286 #address-cells = <1>;
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
294 clock-names = "spiclk", "apb_pclk";
295 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
296 dma-names = "tx", "rx";
297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
300 reg = <0x0 0xff120000 0x0 0x1000>;
301 #address-cells = <1>;
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
311 dma-names = "tx", "rx";
312 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
315 reg = <0x0 0xff130000 0x0 0x1000>;
316 #address-cells = <1>;
322 compatible = "rockchip,rk3288-i2c";
323 reg = <0x0 0xff140000 0x0 0x1000>;
324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
328 clocks = <&cru PCLK_I2C1>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c1_xfer>;
335 compatible = "rockchip,rk3288-i2c";
336 reg = <0x0 0xff150000 0x0 0x1000>;
337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
341 clocks = <&cru PCLK_I2C3>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c3_xfer>;
348 compatible = "rockchip,rk3288-i2c";
349 reg = <0x0 0xff160000 0x0 0x1000>;
350 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
354 clocks = <&cru PCLK_I2C4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c4_xfer>;
361 compatible = "rockchip,rk3288-i2c";
362 reg = <0x0 0xff170000 0x0 0x1000>;
363 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
367 clocks = <&cru PCLK_I2C5>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c5_xfer>;
373 uart0: serial@ff180000 {
374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff180000 0x0 0x100>;
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
380 clock-names = "baudclk", "apb_pclk";
381 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
382 dma-names = "tx", "rx";
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer>;
388 uart1: serial@ff190000 {
389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
390 reg = <0x0 0xff190000 0x0 0x100>;
391 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
395 clock-names = "baudclk", "apb_pclk";
396 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
397 dma-names = "tx", "rx";
398 pinctrl-names = "default";
399 pinctrl-0 = <&uart1_xfer>;
403 uart2: serial@ff690000 {
404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
405 reg = <0x0 0xff690000 0x0 0x100>;
406 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
410 clock-names = "baudclk", "apb_pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&uart2_xfer>;
416 uart3: serial@ff1b0000 {
417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
418 reg = <0x0 0xff1b0000 0x0 0x100>;
419 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
423 clock-names = "baudclk", "apb_pclk";
424 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
425 dma-names = "tx", "rx";
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer>;
431 uart4: serial@ff1c0000 {
432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
433 reg = <0x0 0xff1c0000 0x0 0x100>;
434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
438 clock-names = "baudclk", "apb_pclk";
439 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&uart4_xfer>;
446 dmac_peri: dma-controller@ff250000 {
447 compatible = "arm,pl330", "arm,primecell";
448 reg = <0x0 0xff250000 0x0 0x4000>;
449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
452 arm,pl330-broken-no-flushp;
453 arm,pl330-periph-burst;
454 clocks = <&cru ACLK_DMAC2>;
455 clock-names = "apb_pclk";
459 reserve_thermal: reserve-thermal {
460 polling-delay-passive = <1000>; /* milliseconds */
461 polling-delay = <5000>; /* milliseconds */
463 thermal-sensors = <&tsadc 0>;
466 cpu_thermal: cpu-thermal {
467 polling-delay-passive = <100>; /* milliseconds */
468 polling-delay = <5000>; /* milliseconds */
470 thermal-sensors = <&tsadc 1>;
473 cpu_alert0: cpu_alert0 {
474 temperature = <70000>; /* millicelsius */
475 hysteresis = <2000>; /* millicelsius */
478 cpu_alert1: cpu_alert1 {
479 temperature = <75000>; /* millicelsius */
480 hysteresis = <2000>; /* millicelsius */
484 temperature = <90000>; /* millicelsius */
485 hysteresis = <2000>; /* millicelsius */
492 trip = <&cpu_alert0>;
494 <&cpu0 THERMAL_NO_LIMIT 6>,
495 <&cpu1 THERMAL_NO_LIMIT 6>,
496 <&cpu2 THERMAL_NO_LIMIT 6>,
497 <&cpu3 THERMAL_NO_LIMIT 6>;
500 trip = <&cpu_alert1>;
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
503 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
504 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
505 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
510 gpu_thermal: gpu-thermal {
511 polling-delay-passive = <100>; /* milliseconds */
512 polling-delay = <5000>; /* milliseconds */
514 thermal-sensors = <&tsadc 2>;
517 gpu_alert0: gpu_alert0 {
518 temperature = <70000>; /* millicelsius */
519 hysteresis = <2000>; /* millicelsius */
523 temperature = <90000>; /* millicelsius */
524 hysteresis = <2000>; /* millicelsius */
531 trip = <&gpu_alert0>;
533 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
539 tsadc: tsadc@ff280000 {
540 compatible = "rockchip,rk3288-tsadc";
541 reg = <0x0 0xff280000 0x0 0x100>;
542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
544 clock-names = "tsadc", "apb_pclk";
545 resets = <&cru SRST_TSADC>;
546 reset-names = "tsadc-apb";
547 pinctrl-names = "init", "default", "sleep";
548 pinctrl-0 = <&otp_pin>;
549 pinctrl-1 = <&otp_out>;
550 pinctrl-2 = <&otp_pin>;
551 #thermal-sensor-cells = <1>;
552 rockchip,grf = <&grf>;
553 rockchip,hw-tshut-temp = <95000>;
557 gmac: ethernet@ff290000 {
558 compatible = "rockchip,rk3288-gmac";
559 reg = <0x0 0xff290000 0x0 0x10000>;
560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "macirq", "eth_wake_irq";
563 rockchip,grf = <&grf>;
564 clocks = <&cru SCLK_MAC>,
565 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
566 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
567 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
568 clock-names = "stmmaceth",
569 "mac_clk_rx", "mac_clk_tx",
570 "clk_mac_ref", "clk_mac_refout",
571 "aclk_mac", "pclk_mac";
572 resets = <&cru SRST_MAC>;
573 reset-names = "stmmaceth";
577 usb_host0_ehci: usb@ff500000 {
578 compatible = "generic-ehci";
579 reg = <0x0 0xff500000 0x0 0x100>;
580 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cru HCLK_USBHOST0>;
587 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
588 usb_host0_ohci: usb@ff520000 {
589 compatible = "generic-ohci";
590 reg = <0x0 0xff520000 0x0 0x100>;
591 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cru HCLK_USBHOST0>;
598 usb_host1: usb@ff540000 {
599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
601 reg = <0x0 0xff540000 0x0 0x40000>;
602 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru HCLK_USBHOST1>;
607 phy-names = "usb2-phy";
608 snps,reset-phy-on-wake;
612 usb_otg: usb@ff580000 {
613 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
615 reg = <0x0 0xff580000 0x0 0x40000>;
616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cru HCLK_OTG0>;
620 g-np-tx-fifo-size = <16>;
621 g-rx-fifo-size = <275>;
622 g-tx-fifo-size = <256 128 128 64 64 32>;
624 phy-names = "usb2-phy";
628 usb_hsic: usb@ff5c0000 {
629 compatible = "generic-ehci";
630 reg = <0x0 0xff5c0000 0x0 0x100>;
631 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru HCLK_HSIC>;
636 dmac_bus_ns: dma-controller@ff600000 {
637 compatible = "arm,pl330", "arm,primecell";
638 reg = <0x0 0xff600000 0x0 0x4000>;
639 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
642 arm,pl330-broken-no-flushp;
643 arm,pl330-periph-burst;
644 clocks = <&cru ACLK_DMAC1>;
645 clock-names = "apb_pclk";
650 compatible = "rockchip,rk3288-i2c";
651 reg = <0x0 0xff650000 0x0 0x1000>;
652 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
656 clocks = <&cru PCLK_I2C0>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&i2c0_xfer>;
663 compatible = "rockchip,rk3288-i2c";
664 reg = <0x0 0xff660000 0x0 0x1000>;
665 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666 #address-cells = <1>;
669 clocks = <&cru PCLK_I2C2>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c2_xfer>;
676 compatible = "rockchip,rk3288-pwm";
677 reg = <0x0 0xff680000 0x0 0x10>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm0_pin>;
681 clocks = <&cru PCLK_RKPWM>;
686 compatible = "rockchip,rk3288-pwm";
687 reg = <0x0 0xff680010 0x0 0x10>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm1_pin>;
691 clocks = <&cru PCLK_RKPWM>;
696 compatible = "rockchip,rk3288-pwm";
697 reg = <0x0 0xff680020 0x0 0x10>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pwm2_pin>;
701 clocks = <&cru PCLK_RKPWM>;
706 compatible = "rockchip,rk3288-pwm";
707 reg = <0x0 0xff680030 0x0 0x10>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pwm3_pin>;
711 clocks = <&cru PCLK_RKPWM>;
715 bus_intmem: sram@ff700000 {
716 compatible = "mmio-sram";
717 reg = <0x0 0xff700000 0x0 0x18000>;
718 #address-cells = <1>;
720 ranges = <0 0x0 0xff700000 0x18000>;
722 compatible = "rockchip,rk3066-smp-sram";
727 pmu_sram: sram@ff720000 {
728 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
729 reg = <0x0 0xff720000 0x0 0x1000>;
732 pmu: power-management@ff730000 {
733 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
734 reg = <0x0 0xff730000 0x0 0x100>;
736 power: power-controller {
737 compatible = "rockchip,rk3288-power-controller";
738 #power-domain-cells = <1>;
739 #address-cells = <1>;
742 assigned-clocks = <&cru SCLK_EDP_24M>;
743 assigned-clock-parents = <&xin24m>;
746 * Note: Although SCLK_* are the working clocks
747 * of device without including on the NOC, needed for
750 * The clocks on the which NOC:
751 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
752 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
753 * ACLK_RGA is on ACLK_RGA_NIU.
754 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
756 * Which clock are device clocks:
758 * *_IEP IEP:Image Enhancement Processor
759 * *_ISP ISP:Image Signal Processing
760 * *_VIP VIP:Video Input Processor
761 * *_VOP* VOP:Visual Output Processor
768 power-domain@RK3288_PD_VIO {
769 reg = <RK3288_PD_VIO>;
770 clocks = <&cru ACLK_IEP>,
784 <&cru PCLK_EDP_CTRL>,
785 <&cru PCLK_HDMI_CTRL>,
786 <&cru PCLK_LVDS_PHY>,
787 <&cru PCLK_MIPI_CSI>,
788 <&cru PCLK_MIPI_DSI0>,
789 <&cru PCLK_MIPI_DSI1>,
795 pm_qos = <&qos_vio0_iep>,
804 #power-domain-cells = <0>;
808 * Note: The following 3 are HEVC(H.265) clocks,
809 * and on the ACLK_HEVC_NIU (NOC).
811 power-domain@RK3288_PD_HEVC {
812 reg = <RK3288_PD_HEVC>;
813 clocks = <&cru ACLK_HEVC>,
814 <&cru SCLK_HEVC_CABAC>,
815 <&cru SCLK_HEVC_CORE>;
816 pm_qos = <&qos_hevc_r>,
818 #power-domain-cells = <0>;
822 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
823 * (video endecoder & decoder) clocks that on the
824 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
826 power-domain@RK3288_PD_VIDEO {
827 reg = <RK3288_PD_VIDEO>;
828 clocks = <&cru ACLK_VCODEC>,
830 pm_qos = <&qos_video>;
831 #power-domain-cells = <0>;
835 * Note: ACLK_GPU is the GPU clock,
836 * and on the ACLK_GPU_NIU (NOC).
838 power-domain@RK3288_PD_GPU {
839 reg = <RK3288_PD_GPU>;
840 clocks = <&cru ACLK_GPU>;
841 pm_qos = <&qos_gpu_r>,
843 #power-domain-cells = <0>;
848 compatible = "syscon-reboot-mode";
850 mode-normal = <BOOT_NORMAL>;
851 mode-recovery = <BOOT_RECOVERY>;
852 mode-bootloader = <BOOT_FASTBOOT>;
853 mode-loader = <BOOT_BL_DOWNLOAD>;
857 sgrf: syscon@ff740000 {
858 compatible = "rockchip,rk3288-sgrf", "syscon";
859 reg = <0x0 0xff740000 0x0 0x1000>;
862 cru: clock-controller@ff760000 {
863 compatible = "rockchip,rk3288-cru";
864 reg = <0x0 0xff760000 0x0 0x1000>;
865 rockchip,grf = <&grf>;
868 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
869 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
870 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
871 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
873 assigned-clock-rates = <594000000>, <400000000>,
874 <500000000>, <300000000>,
875 <150000000>, <75000000>,
876 <300000000>, <150000000>,
880 grf: syscon@ff770000 {
881 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
882 reg = <0x0 0xff770000 0x0 0x1000>;
885 compatible = "rockchip,rk3288-dp-phy";
886 clocks = <&cru SCLK_EDP_24M>;
892 io_domains: io-domains {
893 compatible = "rockchip,rk3288-io-voltage-domain";
898 compatible = "rockchip,rk3288-usb-phy";
899 #address-cells = <1>;
903 usbphy0: usb-phy@320 {
906 clocks = <&cru SCLK_OTGPHY0>;
907 clock-names = "phyclk";
909 resets = <&cru SRST_USBOTG_PHY>;
910 reset-names = "phy-reset";
913 usbphy1: usb-phy@334 {
916 clocks = <&cru SCLK_OTGPHY1>;
917 clock-names = "phyclk";
919 resets = <&cru SRST_USBHOST0_PHY>;
920 reset-names = "phy-reset";
923 usbphy2: usb-phy@348 {
926 clocks = <&cru SCLK_OTGPHY2>;
927 clock-names = "phyclk";
929 resets = <&cru SRST_USBHOST1_PHY>;
930 reset-names = "phy-reset";
935 wdt: watchdog@ff800000 {
936 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
937 reg = <0x0 0xff800000 0x0 0x100>;
938 clocks = <&cru PCLK_WDT>;
939 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
943 spdif: sound@ff88b0000 {
944 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
945 reg = <0x0 0xff8b0000 0x0 0x10000>;
946 #sound-dai-cells = <0>;
947 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
948 clock-names = "mclk", "hclk";
949 dmas = <&dmac_bus_s 3>;
951 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&spdif_tx>;
954 rockchip,grf = <&grf>;
959 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
960 reg = <0x0 0xff890000 0x0 0x10000>;
961 #sound-dai-cells = <0>;
962 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
964 clock-names = "i2s_clk", "i2s_hclk";
965 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
966 dma-names = "tx", "rx";
967 pinctrl-names = "default";
968 pinctrl-0 = <&i2s0_bus>;
969 rockchip,playback-channels = <8>;
970 rockchip,capture-channels = <2>;
974 crypto: cypto-controller@ff8a0000 {
975 compatible = "rockchip,rk3288-crypto";
976 reg = <0x0 0xff8a0000 0x0 0x4000>;
977 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
979 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
980 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
981 resets = <&cru SRST_CRYPTO>;
982 reset-names = "crypto-rst";
986 iep_mmu: iommu@ff900800 {
987 compatible = "rockchip,iommu";
988 reg = <0x0 0xff900800 0x0 0x40>;
989 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
991 clock-names = "aclk", "iface";
996 isp_mmu: iommu@ff914000 {
997 compatible = "rockchip,iommu";
998 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
999 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1001 clock-names = "aclk", "iface";
1003 rockchip,disable-mmu-reset;
1004 status = "disabled";
1008 compatible = "rockchip,rk3288-rga";
1009 reg = <0x0 0xff920000 0x0 0x180>;
1010 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1012 clock-names = "aclk", "hclk", "sclk";
1013 power-domains = <&power RK3288_PD_VIO>;
1014 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1015 reset-names = "core", "axi", "ahb";
1018 vopb: vop@ff930000 {
1019 compatible = "rockchip,rk3288-vop";
1020 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1021 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1023 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1024 power-domains = <&power RK3288_PD_VIO>;
1025 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1026 reset-names = "axi", "ahb", "dclk";
1027 iommus = <&vopb_mmu>;
1028 status = "disabled";
1031 #address-cells = <1>;
1034 vopb_out_hdmi: endpoint@0 {
1036 remote-endpoint = <&hdmi_in_vopb>;
1039 vopb_out_edp: endpoint@1 {
1041 remote-endpoint = <&edp_in_vopb>;
1044 vopb_out_mipi: endpoint@2 {
1046 remote-endpoint = <&mipi_in_vopb>;
1049 vopb_out_lvds: endpoint@3 {
1051 remote-endpoint = <&lvds_in_vopb>;
1056 vopb_mmu: iommu@ff930300 {
1057 compatible = "rockchip,iommu";
1058 reg = <0x0 0xff930300 0x0 0x100>;
1059 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1061 clock-names = "aclk", "iface";
1062 power-domains = <&power RK3288_PD_VIO>;
1064 status = "disabled";
1067 vopl: vop@ff940000 {
1068 compatible = "rockchip,rk3288-vop";
1069 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1070 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1072 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1073 power-domains = <&power RK3288_PD_VIO>;
1074 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1075 reset-names = "axi", "ahb", "dclk";
1076 iommus = <&vopl_mmu>;
1077 status = "disabled";
1080 #address-cells = <1>;
1083 vopl_out_hdmi: endpoint@0 {
1085 remote-endpoint = <&hdmi_in_vopl>;
1088 vopl_out_edp: endpoint@1 {
1090 remote-endpoint = <&edp_in_vopl>;
1093 vopl_out_mipi: endpoint@2 {
1095 remote-endpoint = <&mipi_in_vopl>;
1098 vopl_out_lvds: endpoint@3 {
1100 remote-endpoint = <&lvds_in_vopl>;
1105 vopl_mmu: iommu@ff940300 {
1106 compatible = "rockchip,iommu";
1107 reg = <0x0 0xff940300 0x0 0x100>;
1108 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1110 clock-names = "aclk", "iface";
1111 power-domains = <&power RK3288_PD_VIO>;
1113 status = "disabled";
1116 mipi_dsi: mipi@ff960000 {
1117 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1118 reg = <0x0 0xff960000 0x0 0x4000>;
1119 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1121 clock-names = "ref", "pclk";
1122 power-domains = <&power RK3288_PD_VIO>;
1123 rockchip,grf = <&grf>;
1124 status = "disabled";
1128 #address-cells = <1>;
1130 mipi_in_vopb: endpoint@0 {
1132 remote-endpoint = <&vopb_out_mipi>;
1134 mipi_in_vopl: endpoint@1 {
1136 remote-endpoint = <&vopl_out_mipi>;
1142 lvds: lvds@ff96c000 {
1143 compatible = "rockchip,rk3288-lvds";
1144 reg = <0x0 0xff96c000 0x0 0x4000>;
1145 clocks = <&cru PCLK_LVDS_PHY>;
1146 clock-names = "pclk_lvds";
1147 pinctrl-names = "lcdc";
1148 pinctrl-0 = <&lcdc_ctl>;
1149 power-domains = <&power RK3288_PD_VIO>;
1150 rockchip,grf = <&grf>;
1151 status = "disabled";
1154 #address-cells = <1>;
1160 #address-cells = <1>;
1163 lvds_in_vopb: endpoint@0 {
1165 remote-endpoint = <&vopb_out_lvds>;
1167 lvds_in_vopl: endpoint@1 {
1169 remote-endpoint = <&vopl_out_lvds>;
1176 compatible = "rockchip,rk3288-dp";
1177 reg = <0x0 0xff970000 0x0 0x4000>;
1178 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1179 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1180 clock-names = "dp", "pclk";
1183 resets = <&cru SRST_EDP>;
1185 rockchip,grf = <&grf>;
1186 status = "disabled";
1189 #address-cells = <1>;
1193 #address-cells = <1>;
1195 edp_in_vopb: endpoint@0 {
1197 remote-endpoint = <&vopb_out_edp>;
1199 edp_in_vopl: endpoint@1 {
1201 remote-endpoint = <&vopl_out_edp>;
1207 hdmi: hdmi@ff980000 {
1208 compatible = "rockchip,rk3288-dw-hdmi";
1209 reg = <0x0 0xff980000 0x0 0x20000>;
1211 #sound-dai-cells = <0>;
1212 rockchip,grf = <&grf>;
1213 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1215 clock-names = "iahb", "isfr", "cec";
1216 power-domains = <&power RK3288_PD_VIO>;
1217 status = "disabled";
1221 #address-cells = <1>;
1223 hdmi_in_vopb: endpoint@0 {
1225 remote-endpoint = <&vopb_out_hdmi>;
1227 hdmi_in_vopl: endpoint@1 {
1229 remote-endpoint = <&vopl_out_hdmi>;
1235 vpu: video-codec@ff9a0000 {
1236 compatible = "rockchip,rk3288-vpu";
1237 reg = <0x0 0xff9a0000 0x0 0x800>;
1238 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1240 interrupt-names = "vepu", "vdpu";
1241 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1242 clock-names = "aclk", "hclk";
1243 iommus = <&vpu_mmu>;
1244 power-domains = <&power RK3288_PD_VIDEO>;
1247 vpu_mmu: iommu@ff9a0800 {
1248 compatible = "rockchip,iommu";
1249 reg = <0x0 0xff9a0800 0x0 0x100>;
1250 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1252 clock-names = "aclk", "iface";
1254 power-domains = <&power RK3288_PD_VIDEO>;
1257 hevc_mmu: iommu@ff9c0440 {
1258 compatible = "rockchip,iommu";
1259 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1260 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1262 clock-names = "aclk", "iface";
1264 status = "disabled";
1268 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1269 reg = <0x0 0xffa30000 0x0 0x10000>;
1270 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1273 interrupt-names = "job", "mmu", "gpu";
1274 clocks = <&cru ACLK_GPU>;
1275 operating-points-v2 = <&gpu_opp_table>;
1276 #cooling-cells = <2>; /* min followed by max */
1277 power-domains = <&power RK3288_PD_GPU>;
1278 status = "disabled";
1281 gpu_opp_table: gpu-opp-table {
1282 compatible = "operating-points-v2";
1285 opp-hz = /bits/ 64 <100000000>;
1286 opp-microvolt = <950000>;
1289 opp-hz = /bits/ 64 <200000000>;
1290 opp-microvolt = <950000>;
1293 opp-hz = /bits/ 64 <300000000>;
1294 opp-microvolt = <1000000>;
1297 opp-hz = /bits/ 64 <400000000>;
1298 opp-microvolt = <1100000>;
1301 opp-hz = /bits/ 64 <600000000>;
1302 opp-microvolt = <1250000>;
1306 qos_gpu_r: qos@ffaa0000 {
1307 compatible = "rockchip,rk3288-qos", "syscon";
1308 reg = <0x0 0xffaa0000 0x0 0x20>;
1311 qos_gpu_w: qos@ffaa0080 {
1312 compatible = "rockchip,rk3288-qos", "syscon";
1313 reg = <0x0 0xffaa0080 0x0 0x20>;
1316 qos_vio1_vop: qos@ffad0000 {
1317 compatible = "rockchip,rk3288-qos", "syscon";
1318 reg = <0x0 0xffad0000 0x0 0x20>;
1321 qos_vio1_isp_w0: qos@ffad0100 {
1322 compatible = "rockchip,rk3288-qos", "syscon";
1323 reg = <0x0 0xffad0100 0x0 0x20>;
1326 qos_vio1_isp_w1: qos@ffad0180 {
1327 compatible = "rockchip,rk3288-qos", "syscon";
1328 reg = <0x0 0xffad0180 0x0 0x20>;
1331 qos_vio0_vop: qos@ffad0400 {
1332 compatible = "rockchip,rk3288-qos", "syscon";
1333 reg = <0x0 0xffad0400 0x0 0x20>;
1336 qos_vio0_vip: qos@ffad0480 {
1337 compatible = "rockchip,rk3288-qos", "syscon";
1338 reg = <0x0 0xffad0480 0x0 0x20>;
1341 qos_vio0_iep: qos@ffad0500 {
1342 compatible = "rockchip,rk3288-qos", "syscon";
1343 reg = <0x0 0xffad0500 0x0 0x20>;
1346 qos_vio2_rga_r: qos@ffad0800 {
1347 compatible = "rockchip,rk3288-qos", "syscon";
1348 reg = <0x0 0xffad0800 0x0 0x20>;
1351 qos_vio2_rga_w: qos@ffad0880 {
1352 compatible = "rockchip,rk3288-qos", "syscon";
1353 reg = <0x0 0xffad0880 0x0 0x20>;
1356 qos_vio1_isp_r: qos@ffad0900 {
1357 compatible = "rockchip,rk3288-qos", "syscon";
1358 reg = <0x0 0xffad0900 0x0 0x20>;
1361 qos_video: qos@ffae0000 {
1362 compatible = "rockchip,rk3288-qos", "syscon";
1363 reg = <0x0 0xffae0000 0x0 0x20>;
1366 qos_hevc_r: qos@ffaf0000 {
1367 compatible = "rockchip,rk3288-qos", "syscon";
1368 reg = <0x0 0xffaf0000 0x0 0x20>;
1371 qos_hevc_w: qos@ffaf0080 {
1372 compatible = "rockchip,rk3288-qos", "syscon";
1373 reg = <0x0 0xffaf0080 0x0 0x20>;
1376 dmac_bus_s: dma-controller@ffb20000 {
1377 compatible = "arm,pl330", "arm,primecell";
1378 reg = <0x0 0xffb20000 0x0 0x4000>;
1379 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1382 arm,pl330-broken-no-flushp;
1383 arm,pl330-periph-burst;
1384 clocks = <&cru ACLK_DMAC1>;
1385 clock-names = "apb_pclk";
1388 efuse: efuse@ffb40000 {
1389 compatible = "rockchip,rk3288-efuse";
1390 reg = <0x0 0xffb40000 0x0 0x20>;
1391 #address-cells = <1>;
1393 clocks = <&cru PCLK_EFUSE256>;
1394 clock-names = "pclk_efuse";
1399 cpu_leakage: cpu_leakage@17 {
1404 gic: interrupt-controller@ffc01000 {
1405 compatible = "arm,gic-400";
1406 interrupt-controller;
1407 #interrupt-cells = <3>;
1408 #address-cells = <0>;
1410 reg = <0x0 0xffc01000 0x0 0x1000>,
1411 <0x0 0xffc02000 0x0 0x2000>,
1412 <0x0 0xffc04000 0x0 0x2000>,
1413 <0x0 0xffc06000 0x0 0x2000>;
1414 interrupts = <GIC_PPI 9 0xf04>;
1418 compatible = "rockchip,rk3288-pinctrl";
1419 rockchip,grf = <&grf>;
1420 rockchip,pmu = <&pmu>;
1421 #address-cells = <2>;
1425 gpio0: gpio0@ff750000 {
1426 compatible = "rockchip,gpio-bank";
1427 reg = <0x0 0xff750000 0x0 0x100>;
1428 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cru PCLK_GPIO0>;
1434 interrupt-controller;
1435 #interrupt-cells = <2>;
1438 gpio1: gpio1@ff780000 {
1439 compatible = "rockchip,gpio-bank";
1440 reg = <0x0 0xff780000 0x0 0x100>;
1441 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1442 clocks = <&cru PCLK_GPIO1>;
1447 interrupt-controller;
1448 #interrupt-cells = <2>;
1451 gpio2: gpio2@ff790000 {
1452 compatible = "rockchip,gpio-bank";
1453 reg = <0x0 0xff790000 0x0 0x100>;
1454 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1455 clocks = <&cru PCLK_GPIO2>;
1460 interrupt-controller;
1461 #interrupt-cells = <2>;
1464 gpio3: gpio3@ff7a0000 {
1465 compatible = "rockchip,gpio-bank";
1466 reg = <0x0 0xff7a0000 0x0 0x100>;
1467 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1468 clocks = <&cru PCLK_GPIO3>;
1473 interrupt-controller;
1474 #interrupt-cells = <2>;
1477 gpio4: gpio4@ff7b0000 {
1478 compatible = "rockchip,gpio-bank";
1479 reg = <0x0 0xff7b0000 0x0 0x100>;
1480 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cru PCLK_GPIO4>;
1486 interrupt-controller;
1487 #interrupt-cells = <2>;
1490 gpio5: gpio5@ff7c0000 {
1491 compatible = "rockchip,gpio-bank";
1492 reg = <0x0 0xff7c0000 0x0 0x100>;
1493 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&cru PCLK_GPIO5>;
1499 interrupt-controller;
1500 #interrupt-cells = <2>;
1503 gpio6: gpio6@ff7d0000 {
1504 compatible = "rockchip,gpio-bank";
1505 reg = <0x0 0xff7d0000 0x0 0x100>;
1506 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&cru PCLK_GPIO6>;
1512 interrupt-controller;
1513 #interrupt-cells = <2>;
1516 gpio7: gpio7@ff7e0000 {
1517 compatible = "rockchip,gpio-bank";
1518 reg = <0x0 0xff7e0000 0x0 0x100>;
1519 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1520 clocks = <&cru PCLK_GPIO7>;
1525 interrupt-controller;
1526 #interrupt-cells = <2>;
1529 gpio8: gpio8@ff7f0000 {
1530 compatible = "rockchip,gpio-bank";
1531 reg = <0x0 0xff7f0000 0x0 0x100>;
1532 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&cru PCLK_GPIO8>;
1538 interrupt-controller;
1539 #interrupt-cells = <2>;
1543 hdmi_cec_c0: hdmi-cec-c0 {
1544 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1547 hdmi_cec_c7: hdmi-cec-c7 {
1548 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1551 hdmi_ddc: hdmi-ddc {
1552 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1553 <7 RK_PC4 2 &pcfg_pull_none>;
1556 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1557 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1558 <7 RK_PC4 2 &pcfg_pull_none>;
1562 pcfg_output_low: pcfg-output-low {
1566 pcfg_pull_up: pcfg-pull-up {
1570 pcfg_pull_down: pcfg-pull-down {
1574 pcfg_pull_none: pcfg-pull-none {
1578 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1580 drive-strength = <12>;
1584 global_pwroff: global-pwroff {
1585 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1588 ddrio_pwroff: ddrio-pwroff {
1589 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1592 ddr0_retention: ddr0-retention {
1593 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1596 ddr1_retention: ddr1-retention {
1597 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1603 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1608 i2c0_xfer: i2c0-xfer {
1609 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1610 <0 RK_PC0 1 &pcfg_pull_none>;
1615 i2c1_xfer: i2c1-xfer {
1616 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1617 <8 RK_PA5 1 &pcfg_pull_none>;
1622 i2c2_xfer: i2c2-xfer {
1623 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1624 <6 RK_PB2 1 &pcfg_pull_none>;
1629 i2c3_xfer: i2c3-xfer {
1630 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1631 <2 RK_PC1 1 &pcfg_pull_none>;
1636 i2c4_xfer: i2c4-xfer {
1637 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1638 <7 RK_PC2 1 &pcfg_pull_none>;
1643 i2c5_xfer: i2c5-xfer {
1644 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1645 <7 RK_PC4 1 &pcfg_pull_none>;
1650 i2s0_bus: i2s0-bus {
1651 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1652 <6 RK_PA1 1 &pcfg_pull_none>,
1653 <6 RK_PA2 1 &pcfg_pull_none>,
1654 <6 RK_PA3 1 &pcfg_pull_none>,
1655 <6 RK_PA4 1 &pcfg_pull_none>,
1656 <6 RK_PB0 1 &pcfg_pull_none>;
1661 lcdc_ctl: lcdc-ctl {
1662 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1663 <1 RK_PD1 1 &pcfg_pull_none>,
1664 <1 RK_PD2 1 &pcfg_pull_none>,
1665 <1 RK_PD3 1 &pcfg_pull_none>;
1670 sdmmc_clk: sdmmc-clk {
1671 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1674 sdmmc_cmd: sdmmc-cmd {
1675 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1678 sdmmc_cd: sdmmc-cd {
1679 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1682 sdmmc_bus1: sdmmc-bus1 {
1683 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1686 sdmmc_bus4: sdmmc-bus4 {
1687 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1688 <6 RK_PC1 1 &pcfg_pull_up>,
1689 <6 RK_PC2 1 &pcfg_pull_up>,
1690 <6 RK_PC3 1 &pcfg_pull_up>;
1695 sdio0_bus1: sdio0-bus1 {
1696 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1699 sdio0_bus4: sdio0-bus4 {
1700 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1701 <4 RK_PC5 1 &pcfg_pull_up>,
1702 <4 RK_PC6 1 &pcfg_pull_up>,
1703 <4 RK_PC7 1 &pcfg_pull_up>;
1706 sdio0_cmd: sdio0-cmd {
1707 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1710 sdio0_clk: sdio0-clk {
1711 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1714 sdio0_cd: sdio0-cd {
1715 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1718 sdio0_wp: sdio0-wp {
1719 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1722 sdio0_pwr: sdio0-pwr {
1723 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1726 sdio0_bkpwr: sdio0-bkpwr {
1727 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1730 sdio0_int: sdio0-int {
1731 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1736 sdio1_bus1: sdio1-bus1 {
1737 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1740 sdio1_bus4: sdio1-bus4 {
1741 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1742 <3 RK_PD1 4 &pcfg_pull_up>,
1743 <3 RK_PD2 4 &pcfg_pull_up>,
1744 <3 RK_PD3 4 &pcfg_pull_up>;
1747 sdio1_cd: sdio1-cd {
1748 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1751 sdio1_wp: sdio1-wp {
1752 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1755 sdio1_bkpwr: sdio1-bkpwr {
1756 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1759 sdio1_int: sdio1-int {
1760 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1763 sdio1_cmd: sdio1-cmd {
1764 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1767 sdio1_clk: sdio1-clk {
1768 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1771 sdio1_pwr: sdio1-pwr {
1772 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1777 emmc_clk: emmc-clk {
1778 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1781 emmc_cmd: emmc-cmd {
1782 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1785 emmc_pwr: emmc-pwr {
1786 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1789 emmc_bus1: emmc-bus1 {
1790 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1793 emmc_bus4: emmc-bus4 {
1794 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1795 <3 RK_PA1 2 &pcfg_pull_up>,
1796 <3 RK_PA2 2 &pcfg_pull_up>,
1797 <3 RK_PA3 2 &pcfg_pull_up>;
1800 emmc_bus8: emmc-bus8 {
1801 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1802 <3 RK_PA1 2 &pcfg_pull_up>,
1803 <3 RK_PA2 2 &pcfg_pull_up>,
1804 <3 RK_PA3 2 &pcfg_pull_up>,
1805 <3 RK_PA4 2 &pcfg_pull_up>,
1806 <3 RK_PA5 2 &pcfg_pull_up>,
1807 <3 RK_PA6 2 &pcfg_pull_up>,
1808 <3 RK_PA7 2 &pcfg_pull_up>;
1813 spi0_clk: spi0-clk {
1814 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1816 spi0_cs0: spi0-cs0 {
1817 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1820 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1823 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1825 spi0_cs1: spi0-cs1 {
1826 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1830 spi1_clk: spi1-clk {
1831 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1833 spi1_cs0: spi1-cs0 {
1834 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1837 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1840 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1845 spi2_cs1: spi2-cs1 {
1846 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1848 spi2_clk: spi2-clk {
1849 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1851 spi2_cs0: spi2-cs0 {
1852 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1855 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1858 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1863 uart0_xfer: uart0-xfer {
1864 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1865 <4 RK_PC1 1 &pcfg_pull_none>;
1868 uart0_cts: uart0-cts {
1869 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1872 uart0_rts: uart0-rts {
1873 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1878 uart1_xfer: uart1-xfer {
1879 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1880 <5 RK_PB1 1 &pcfg_pull_none>;
1883 uart1_cts: uart1-cts {
1884 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1887 uart1_rts: uart1-rts {
1888 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1893 uart2_xfer: uart2-xfer {
1894 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1895 <7 RK_PC7 1 &pcfg_pull_none>;
1897 /* no rts / cts for uart2 */
1901 uart3_xfer: uart3-xfer {
1902 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1903 <7 RK_PB0 1 &pcfg_pull_none>;
1906 uart3_cts: uart3-cts {
1907 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1910 uart3_rts: uart3-rts {
1911 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1916 uart4_xfer: uart4-xfer {
1917 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1918 <5 RK_PB6 3 &pcfg_pull_none>;
1921 uart4_cts: uart4-cts {
1922 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1925 uart4_rts: uart4-rts {
1926 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1932 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1936 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1941 pwm0_pin: pwm0-pin {
1942 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1947 pwm1_pin: pwm1-pin {
1948 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1953 pwm2_pin: pwm2-pin {
1954 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1959 pwm3_pin: pwm3-pin {
1960 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1965 rgmii_pins: rgmii-pins {
1966 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1967 <3 RK_PD7 3 &pcfg_pull_none>,
1968 <3 RK_PD2 3 &pcfg_pull_none>,
1969 <3 RK_PD3 3 &pcfg_pull_none>,
1970 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1971 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1972 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1973 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1974 <4 RK_PA0 3 &pcfg_pull_none>,
1975 <4 RK_PA5 3 &pcfg_pull_none>,
1976 <4 RK_PA6 3 &pcfg_pull_none>,
1977 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1978 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1979 <4 RK_PA1 3 &pcfg_pull_none>,
1980 <4 RK_PA3 3 &pcfg_pull_none>;
1983 rmii_pins: rmii-pins {
1984 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1985 <3 RK_PD7 3 &pcfg_pull_none>,
1986 <3 RK_PD4 3 &pcfg_pull_none>,
1987 <3 RK_PD5 3 &pcfg_pull_none>,
1988 <4 RK_PA0 3 &pcfg_pull_none>,
1989 <4 RK_PA5 3 &pcfg_pull_none>,
1990 <4 RK_PA4 3 &pcfg_pull_none>,
1991 <4 RK_PA1 3 &pcfg_pull_none>,
1992 <4 RK_PA2 3 &pcfg_pull_none>,
1993 <4 RK_PA3 3 &pcfg_pull_none>;
1998 spdif_tx: spdif-tx {
1999 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;