arch/arm/boot/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/power/rk3288-power.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         compatible = "rockchip,rk3288";
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 mshc0 = &emmc;
  30                 mshc1 = &sdmmc;
  31                 mshc2 = &sdio0;
  32                 mshc3 = &sdio1;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &uart2;
  36                 serial3 = &uart3;
  37                 serial4 = &uart4;
  38                 spi0 = &spi0;
  39                 spi1 = &spi1;
  40                 spi2 = &spi2;
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a12-pmu";
  45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         resets = <&cru SRST_CORE0>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clock-latency = <40000>;
  66                         clocks = <&cru ARMCLK>;
  67                         dynamic-power-coefficient = <370>;
  68                 };
  69                 cpu1: cpu@501 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a12";
  72                         reg = <0x501>;
  73                         resets = <&cru SRST_CORE1>;
  74                         operating-points-v2 = <&cpu_opp_table>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                         clock-latency = <40000>;
  77                         clocks = <&cru ARMCLK>;
  78                         dynamic-power-coefficient = <370>;
  79                 };
  80                 cpu2: cpu@502 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a12";
  83                         reg = <0x502>;
  84                         resets = <&cru SRST_CORE2>;
  85                         operating-points-v2 = <&cpu_opp_table>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         clock-latency = <40000>;
  88                         clocks = <&cru ARMCLK>;
  89                         dynamic-power-coefficient = <370>;
  90                 };
  91                 cpu3: cpu@503 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x503>;
  95                         resets = <&cru SRST_CORE3>;
  96                         operating-points-v2 = <&cpu_opp_table>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                         clock-latency = <40000>;
  99                         clocks = <&cru ARMCLK>;
 100                         dynamic-power-coefficient = <370>;
 101                 };
 102         };
 103
 104         cpu_opp_table: cpu-opp-table {
 105                 compatible = "operating-points-v2";
 106                 opp-shared;
 107
 108                 opp-126000000 {
 109                         opp-hz = /bits/ 64 <126000000>;
 110                         opp-microvolt = <900000>;
 111                 };
 112                 opp-216000000 {
 113                         opp-hz = /bits/ 64 <216000000>;
 114                         opp-microvolt = <900000>;
 115                 };
 116                 opp-312000000 {
 117                         opp-hz = /bits/ 64 <312000000>;
 118                         opp-microvolt = <900000>;
 119                 };
 120                 opp-408000000 {
 121                         opp-hz = /bits/ 64 <408000000>;
 122                         opp-microvolt = <900000>;
 123                 };
 124                 opp-600000000 {
 125                         opp-hz = /bits/ 64 <600000000>;
 126                         opp-microvolt = <900000>;
 127                 };
 128                 opp-696000000 {
 129                         opp-hz = /bits/ 64 <696000000>;
 130                         opp-microvolt = <950000>;
 131                 };
 132                 opp-816000000 {
 133                         opp-hz = /bits/ 64 <816000000>;
 134                         opp-microvolt = <1000000>;
 135                 };
 136                 opp-1008000000 {
 137                         opp-hz = /bits/ 64 <1008000000>;
 138                         opp-microvolt = <1050000>;
 139                 };
 140                 opp-1200000000 {
 141                         opp-hz = /bits/ 64 <1200000000>;
 142                         opp-microvolt = <1100000>;
 143                 };
 144                 opp-1416000000 {
 145                         opp-hz = /bits/ 64 <1416000000>;
 146                         opp-microvolt = <1200000>;
 147                 };
 148                 opp-1512000000 {
 149                         opp-hz = /bits/ 64 <1512000000>;
 150                         opp-microvolt = <1300000>;
 151                 };
 152                 opp-1608000000 {
 153                         opp-hz = /bits/ 64 <1608000000>;
 154                         opp-microvolt = <1350000>;
 155                 };
 156         };
 157
 158         amba: bus {
 159                 compatible = "simple-bus";
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163
 164                 dmac_peri: dma-controller@ff250000 {
 165                         compatible = "arm,pl330", "arm,primecell";
 166                         reg = <0x0 0xff250000 0x0 0x4000>;
 167                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 169                         #dma-cells = <1>;
 170                         arm,pl330-broken-no-flushp;
 171                         clocks = <&cru ACLK_DMAC2>;
 172                         clock-names = "apb_pclk";
 173                 };
 174
 175                 dmac_bus_ns: dma-controller@ff600000 {
 176                         compatible = "arm,pl330", "arm,primecell";
 177                         reg = <0x0 0xff600000 0x0 0x4000>;
 178                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 180                         #dma-cells = <1>;
 181                         arm,pl330-broken-no-flushp;
 182                         clocks = <&cru ACLK_DMAC1>;
 183                         clock-names = "apb_pclk";
 184                         status = "disabled";
 185                 };
 186
 187                 dmac_bus_s: dma-controller@ffb20000 {
 188                         compatible = "arm,pl330", "arm,primecell";
 189                         reg = <0x0 0xffb20000 0x0 0x4000>;
 190                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 192                         #dma-cells = <1>;
 193                         arm,pl330-broken-no-flushp;
 194                         clocks = <&cru ACLK_DMAC1>;
 195                         clock-names = "apb_pclk";
 196                 };
 197         };
 198
 199         reserved-memory {
 200                 #address-cells = <2>;
 201                 #size-cells = <2>;
 202                 ranges;
 203
 204                 /*
 205                  * The rk3288 cannot use the memory area above 0xfe000000
 206                  * for dma operations for some reason. While there is
 207                  * probably a better solution available somewhere, we
 208                  * haven't found it yet and while devices with 2GB of ram
 209                  * are not affected, this issue prevents 4GB from booting.
 210                  * So to make these devices at least bootable, block
 211                  * this area for the time being until the real solution
 212                  * is found.
 213                  */
 214                 dma-unusable@fe000000 {
 215                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 216                 };
 217         };
 218
 219         xin24m: oscillator {
 220                 compatible = "fixed-clock";
 221                 clock-frequency = <24000000>;
 222                 clock-output-names = "xin24m";
 223                 #clock-cells = <0>;
 224         };
 225
 226         timer {
 227                 compatible = "arm,armv7-timer";
 228                 arm,cpu-registers-not-fw-configured;
 229                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 230                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 231                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 232                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 233                 clock-frequency = <24000000>;
 234                 arm,no-tick-in-suspend;
 235         };
 236
 237         timer: timer@ff810000 {
 238                 compatible = "rockchip,rk3288-timer";
 239                 reg = <0x0 0xff810000 0x0 0x20>;
 240                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 242                 clock-names = "timer", "pclk";
 243         };
 244
 245         display-subsystem {
 246                 compatible = "rockchip,display-subsystem";
 247                 ports = <&vopl_out>, <&vopb_out>;
 248         };
 249
 250         sdmmc: mmc@ff0c0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 max-frequency = <150000000>;
 253                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 254                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 259                 resets = <&cru SRST_MMC0>;
 260                 reset-names = "reset";
 261                 status = "disabled";
 262         };
 263
 264         sdio0: mmc@ff0d0000 {
 265                 compatible = "rockchip,rk3288-dw-mshc";
 266                 max-frequency = <150000000>;
 267                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 268                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 273                 resets = <&cru SRST_SDIO0>;
 274                 reset-names = "reset";
 275                 status = "disabled";
 276         };
 277
 278         sdio1: mmc@ff0e0000 {
 279                 compatible = "rockchip,rk3288-dw-mshc";
 280                 max-frequency = <150000000>;
 281                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 282                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 283                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 284                 fifo-depth = <0x100>;
 285                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 286                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 287                 resets = <&cru SRST_SDIO1>;
 288                 reset-names = "reset";
 289                 status = "disabled";
 290         };
 291
 292         emmc: mmc@ff0f0000 {
 293                 compatible = "rockchip,rk3288-dw-mshc";
 294                 max-frequency = <150000000>;
 295                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 296                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 300                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 301                 resets = <&cru SRST_EMMC>;
 302                 reset-names = "reset";
 303                 status = "disabled";
 304         };
 305
 306         saradc: saradc@ff100000 {
 307                 compatible = "rockchip,saradc";
 308                 reg = <0x0 0xff100000 0x0 0x100>;
 309                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 310                 #io-channel-cells = <1>;
 311                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 312                 clock-names = "saradc", "apb_pclk";
 313                 resets = <&cru SRST_SARADC>;
 314                 reset-names = "saradc-apb";
 315                 status = "disabled";
 316         };
 317
 318         spi0: spi@ff110000 {
 319                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 320                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 321                 clock-names = "spiclk", "apb_pclk";
 322                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 323                 dma-names = "tx", "rx";
 324                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 327                 reg = <0x0 0xff110000 0x0 0x1000>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         spi1: spi@ff120000 {
 334                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 335                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 336                 clock-names = "spiclk", "apb_pclk";
 337                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 338                 dma-names = "tx", "rx";
 339                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 342                 reg = <0x0 0xff120000 0x0 0x1000>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 status = "disabled";
 346         };
 347
 348         spi2: spi@ff130000 {
 349                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 350                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 351                 clock-names = "spiclk", "apb_pclk";
 352                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 353                 dma-names = "tx", "rx";
 354                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 357                 reg = <0x0 0xff130000 0x0 0x1000>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 status = "disabled";
 361         };
 362
 363         i2c1: i2c@ff140000 {
 364                 compatible = "rockchip,rk3288-i2c";
 365                 reg = <0x0 0xff140000 0x0 0x1000>;
 366                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clock-names = "i2c";
 370                 clocks = <&cru PCLK_I2C1>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c1_xfer>;
 373                 status = "disabled";
 374         };
 375
 376         i2c3: i2c@ff150000 {
 377                 compatible = "rockchip,rk3288-i2c";
 378                 reg = <0x0 0xff150000 0x0 0x1000>;
 379                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clock-names = "i2c";
 383                 clocks = <&cru PCLK_I2C3>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&i2c3_xfer>;
 386                 status = "disabled";
 387         };
 388
 389         i2c4: i2c@ff160000 {
 390                 compatible = "rockchip,rk3288-i2c";
 391                 reg = <0x0 0xff160000 0x0 0x1000>;
 392                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-names = "i2c";
 396                 clocks = <&cru PCLK_I2C4>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c4_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         i2c5: i2c@ff170000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0x0 0xff170000 0x0 0x1000>;
 405                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C5>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c5_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         uart0: serial@ff180000 {
 416                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 417                 reg = <0x0 0xff180000 0x0 0x100>;
 418                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 422                 clock-names = "baudclk", "apb_pclk";
 423                 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
 424                 dma-names = "tx", "rx";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&uart0_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         uart1: serial@ff190000 {
 431                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 432                 reg = <0x0 0xff190000 0x0 0x100>;
 433                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 434                 reg-shift = <2>;
 435                 reg-io-width = <4>;
 436                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 437                 clock-names = "baudclk", "apb_pclk";
 438                 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
 439                 dma-names = "tx", "rx";
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&uart1_xfer>;
 442                 status = "disabled";
 443         };
 444
 445         uart2: serial@ff690000 {
 446                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 447                 reg = <0x0 0xff690000 0x0 0x100>;
 448                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 449                 reg-shift = <2>;
 450                 reg-io-width = <4>;
 451                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 452                 clock-names = "baudclk", "apb_pclk";
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&uart2_xfer>;
 455                 status = "disabled";
 456         };
 457
 458         uart3: serial@ff1b0000 {
 459                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 460                 reg = <0x0 0xff1b0000 0x0 0x100>;
 461                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 462                 reg-shift = <2>;
 463                 reg-io-width = <4>;
 464                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 465                 clock-names = "baudclk", "apb_pclk";
 466                 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
 467                 dma-names = "tx", "rx";
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&uart3_xfer>;
 470                 status = "disabled";
 471         };
 472
 473         uart4: serial@ff1c0000 {
 474                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 475                 reg = <0x0 0xff1c0000 0x0 0x100>;
 476                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 477                 reg-shift = <2>;
 478                 reg-io-width = <4>;
 479                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 480                 clock-names = "baudclk", "apb_pclk";
 481                 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
 482                 dma-names = "tx", "rx";
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&uart4_xfer>;
 485                 status = "disabled";
 486         };
 487
 488         thermal-zones {
 489                 reserve_thermal: reserve_thermal {
 490                         polling-delay-passive = <1000>; /* milliseconds */
 491                         polling-delay = <5000>; /* milliseconds */
 492
 493                         thermal-sensors = <&tsadc 0>;
 494                 };
 495
 496                 cpu_thermal: cpu_thermal {
 497                         polling-delay-passive = <100>; /* milliseconds */
 498                         polling-delay = <5000>; /* milliseconds */
 499
 500                         thermal-sensors = <&tsadc 1>;
 501
 502                         trips {
 503                                 cpu_alert0: cpu_alert0 {
 504                                         temperature = <70000>; /* millicelsius */
 505                                         hysteresis = <2000>; /* millicelsius */
 506                                         type = "passive";
 507                                 };
 508                                 cpu_alert1: cpu_alert1 {
 509                                         temperature = <75000>; /* millicelsius */
 510                                         hysteresis = <2000>; /* millicelsius */
 511                                         type = "passive";
 512                                 };
 513                                 cpu_crit: cpu_crit {
 514                                         temperature = <90000>; /* millicelsius */
 515                                         hysteresis = <2000>; /* millicelsius */
 516                                         type = "critical";
 517                                 };
 518                         };
 519
 520                         cooling-maps {
 521                                 map0 {
 522                                         trip = <&cpu_alert0>;
 523                                         cooling-device =
 524                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 525                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 526                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 527                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 528                                 };
 529                                 map1 {
 530                                         trip = <&cpu_alert1>;
 531                                         cooling-device =
 532                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 533                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 534                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 535                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 536                                 };
 537                         };
 538                 };
 539
 540                 gpu_thermal: gpu_thermal {
 541                         polling-delay-passive = <100>; /* milliseconds */
 542                         polling-delay = <5000>; /* milliseconds */
 543
 544                         thermal-sensors = <&tsadc 2>;
 545
 546                         trips {
 547                                 gpu_alert0: gpu_alert0 {
 548                                         temperature = <70000>; /* millicelsius */
 549                                         hysteresis = <2000>; /* millicelsius */
 550                                         type = "passive";
 551                                 };
 552                                 gpu_crit: gpu_crit {
 553                                         temperature = <90000>; /* millicelsius */
 554                                         hysteresis = <2000>; /* millicelsius */
 555                                         type = "critical";
 556                                 };
 557                         };
 558
 559                         cooling-maps {
 560                                 map0 {
 561                                         trip = <&gpu_alert0>;
 562                                         cooling-device =
 563                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 564                                 };
 565                         };
 566                 };
 567         };
 568
 569         tsadc: tsadc@ff280000 {
 570                 compatible = "rockchip,rk3288-tsadc";
 571                 reg = <0x0 0xff280000 0x0 0x100>;
 572                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 573                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 574                 clock-names = "tsadc", "apb_pclk";
 575                 resets = <&cru SRST_TSADC>;
 576                 reset-names = "tsadc-apb";
 577                 pinctrl-names = "init", "default", "sleep";
 578                 pinctrl-0 = <&otp_gpio>;
 579                 pinctrl-1 = <&otp_out>;
 580                 pinctrl-2 = <&otp_gpio>;
 581                 #thermal-sensor-cells = <1>;
 582                 rockchip,grf = <&grf>;
 583                 rockchip,hw-tshut-temp = <95000>;
 584                 status = "disabled";
 585         };
 586
 587         gmac: ethernet@ff290000 {
 588                 compatible = "rockchip,rk3288-gmac";
 589                 reg = <0x0 0xff290000 0x0 0x10000>;
 590                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 591                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 592                 interrupt-names = "macirq", "eth_wake_irq";
 593                 rockchip,grf = <&grf>;
 594                 clocks = <&cru SCLK_MAC>,
 595                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 596                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 597                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 598                 clock-names = "stmmaceth",
 599                         "mac_clk_rx", "mac_clk_tx",
 600                         "clk_mac_ref", "clk_mac_refout",
 601                         "aclk_mac", "pclk_mac";
 602                 resets = <&cru SRST_MAC>;
 603                 reset-names = "stmmaceth";
 604                 status = "disabled";
 605         };
 606
 607         usb_host0_ehci: usb@ff500000 {
 608                 compatible = "generic-ehci";
 609                 reg = <0x0 0xff500000 0x0 0x100>;
 610                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&cru HCLK_USBHOST0>;
 612                 phys = <&usbphy1>;
 613                 phy-names = "usb";
 614                 status = "disabled";
 615         };
 616
 617         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 618
 619         usb_host1: usb@ff540000 {
 620                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 621                                 "snps,dwc2";
 622                 reg = <0x0 0xff540000 0x0 0x40000>;
 623                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&cru HCLK_USBHOST1>;
 625                 clock-names = "otg";
 626                 dr_mode = "host";
 627                 phys = <&usbphy2>;
 628                 phy-names = "usb2-phy";
 629                 snps,reset-phy-on-wake;
 630                 status = "disabled";
 631         };
 632
 633         usb_otg: usb@ff580000 {
 634                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 635                                 "snps,dwc2";
 636                 reg = <0x0 0xff580000 0x0 0x40000>;
 637                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&cru HCLK_OTG0>;
 639                 clock-names = "otg";
 640                 dr_mode = "otg";
 641                 g-np-tx-fifo-size = <16>;
 642                 g-rx-fifo-size = <275>;
 643                 g-tx-fifo-size = <256 128 128 64 64 32>;
 644                 phys = <&usbphy0>;
 645                 phy-names = "usb2-phy";
 646                 status = "disabled";
 647         };
 648
 649         usb_hsic: usb@ff5c0000 {
 650                 compatible = "generic-ehci";
 651                 reg = <0x0 0xff5c0000 0x0 0x100>;
 652                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&cru HCLK_HSIC>;
 654                 status = "disabled";
 655         };
 656
 657         i2c0: i2c@ff650000 {
 658                 compatible = "rockchip,rk3288-i2c";
 659                 reg = <0x0 0xff650000 0x0 0x1000>;
 660                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 661                 #address-cells = <1>;
 662                 #size-cells = <0>;
 663                 clock-names = "i2c";
 664                 clocks = <&cru PCLK_I2C0>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&i2c0_xfer>;
 667                 status = "disabled";
 668         };
 669
 670         i2c2: i2c@ff660000 {
 671                 compatible = "rockchip,rk3288-i2c";
 672                 reg = <0x0 0xff660000 0x0 0x1000>;
 673                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 clock-names = "i2c";
 677                 clocks = <&cru PCLK_I2C2>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&i2c2_xfer>;
 680                 status = "disabled";
 681         };
 682
 683         pwm0: pwm@ff680000 {
 684                 compatible = "rockchip,rk3288-pwm";
 685                 reg = <0x0 0xff680000 0x0 0x10>;
 686                 #pwm-cells = <3>;
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&pwm0_pin>;
 689                 clocks = <&cru PCLK_RKPWM>;
 690                 clock-names = "pwm";
 691                 status = "disabled";
 692         };
 693
 694         pwm1: pwm@ff680010 {
 695                 compatible = "rockchip,rk3288-pwm";
 696                 reg = <0x0 0xff680010 0x0 0x10>;
 697                 #pwm-cells = <3>;
 698                 pinctrl-names = "default";
 699                 pinctrl-0 = <&pwm1_pin>;
 700                 clocks = <&cru PCLK_RKPWM>;
 701                 clock-names = "pwm";
 702                 status = "disabled";
 703         };
 704
 705         pwm2: pwm@ff680020 {
 706                 compatible = "rockchip,rk3288-pwm";
 707                 reg = <0x0 0xff680020 0x0 0x10>;
 708                 #pwm-cells = <3>;
 709                 pinctrl-names = "default";
 710                 pinctrl-0 = <&pwm2_pin>;
 711                 clocks = <&cru PCLK_RKPWM>;
 712                 clock-names = "pwm";
 713                 status = "disabled";
 714         };
 715
 716         pwm3: pwm@ff680030 {
 717                 compatible = "rockchip,rk3288-pwm";
 718                 reg = <0x0 0xff680030 0x0 0x10>;
 719                 #pwm-cells = <3>;
 720                 pinctrl-names = "default";
 721                 pinctrl-0 = <&pwm3_pin>;
 722                 clocks = <&cru PCLK_RKPWM>;
 723                 clock-names = "pwm";
 724                 status = "disabled";
 725         };
 726
 727         bus_intmem: sram@ff700000 {
 728                 compatible = "mmio-sram";
 729                 reg = <0x0 0xff700000 0x0 0x18000>;
 730                 #address-cells = <1>;
 731                 #size-cells = <1>;
 732                 ranges = <0 0x0 0xff700000 0x18000>;
 733                 smp-sram@0 {
 734                         compatible = "rockchip,rk3066-smp-sram";
 735                         reg = <0x00 0x10>;
 736                 };
 737         };
 738
 739         pmu_sram: sram@ff720000 {
 740                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 741                 reg = <0x0 0xff720000 0x0 0x1000>;
 742         };
 743
 744         pmu: power-management@ff730000 {
 745                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 746                 reg = <0x0 0xff730000 0x0 0x100>;
 747
 748                 power: power-controller {
 749                         compatible = "rockchip,rk3288-power-controller";
 750                         #power-domain-cells = <1>;
 751                         #address-cells = <1>;
 752                         #size-cells = <0>;
 753
 754                         assigned-clocks = <&cru SCLK_EDP_24M>;
 755                         assigned-clock-parents = <&xin24m>;
 756
 757                         /*
 758                          * Note: Although SCLK_* are the working clocks
 759                          * of device without including on the NOC, needed for
 760                          * synchronous reset.
 761                          *
 762                          * The clocks on the which NOC:
 763                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 764                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 765                          * ACLK_RGA is on ACLK_RGA_NIU.
 766                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 767                          *
 768                          * Which clock are device clocks:
 769                          *      clocks          devices
 770                          *      *_IEP           IEP:Image Enhancement Processor
 771                          *      *_ISP           ISP:Image Signal Processing
 772                          *      *_VIP           VIP:Video Input Processor
 773                          *      *_VOP*          VOP:Visual Output Processor
 774                          *      *_RGA           RGA
 775                          *      *_EDP*          EDP
 776                          *      *_LVDS_*        LVDS
 777                          *      *_HDMI          HDMI
 778                          *      *_MIPI_*        MIPI
 779                          */
 780                         pd_vio@RK3288_PD_VIO {
 781                                 reg = <RK3288_PD_VIO>;
 782                                 clocks = <&cru ACLK_IEP>,
 783                                          <&cru ACLK_ISP>,
 784                                          <&cru ACLK_RGA>,
 785                                          <&cru ACLK_VIP>,
 786                                          <&cru ACLK_VOP0>,
 787                                          <&cru ACLK_VOP1>,
 788                                          <&cru DCLK_VOP0>,
 789                                          <&cru DCLK_VOP1>,
 790                                          <&cru HCLK_IEP>,
 791                                          <&cru HCLK_ISP>,
 792                                          <&cru HCLK_RGA>,
 793                                          <&cru HCLK_VIP>,
 794                                          <&cru HCLK_VOP0>,
 795                                          <&cru HCLK_VOP1>,
 796                                          <&cru PCLK_EDP_CTRL>,
 797                                          <&cru PCLK_HDMI_CTRL>,
 798                                          <&cru PCLK_LVDS_PHY>,
 799                                          <&cru PCLK_MIPI_CSI>,
 800                                          <&cru PCLK_MIPI_DSI0>,
 801                                          <&cru PCLK_MIPI_DSI1>,
 802                                          <&cru SCLK_EDP_24M>,
 803                                          <&cru SCLK_EDP>,
 804                                          <&cru SCLK_ISP_JPE>,
 805                                          <&cru SCLK_ISP>,
 806                                          <&cru SCLK_RGA>;
 807                                 pm_qos = <&qos_vio0_iep>,
 808                                          <&qos_vio1_vop>,
 809                                          <&qos_vio1_isp_w0>,
 810                                          <&qos_vio1_isp_w1>,
 811                                          <&qos_vio0_vop>,
 812                                          <&qos_vio0_vip>,
 813                                          <&qos_vio2_rga_r>,
 814                                          <&qos_vio2_rga_w>,
 815                                          <&qos_vio1_isp_r>;
 816                         };
 817
 818                         /*
 819                          * Note: The following 3 are HEVC(H.265) clocks,
 820                          * and on the ACLK_HEVC_NIU (NOC).
 821                          */
 822                         pd_hevc@RK3288_PD_HEVC {
 823                                 reg = <RK3288_PD_HEVC>;
 824                                 clocks = <&cru ACLK_HEVC>,
 825                                          <&cru SCLK_HEVC_CABAC>,
 826                                          <&cru SCLK_HEVC_CORE>;
 827                                 pm_qos = <&qos_hevc_r>,
 828                                          <&qos_hevc_w>;
 829                         };
 830
 831                         /*
 832                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 833                          * (video endecoder & decoder) clocks that on the
 834                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 835                          */
 836                         pd_video@RK3288_PD_VIDEO {
 837                                 reg = <RK3288_PD_VIDEO>;
 838                                 clocks = <&cru ACLK_VCODEC>,
 839                                          <&cru HCLK_VCODEC>;
 840                                 pm_qos = <&qos_video>;
 841                         };
 842
 843                         /*
 844                          * Note: ACLK_GPU is the GPU clock,
 845                          * and on the ACLK_GPU_NIU (NOC).
 846                          */
 847                         pd_gpu@RK3288_PD_GPU {
 848                                 reg = <RK3288_PD_GPU>;
 849                                 clocks = <&cru ACLK_GPU>;
 850                                 pm_qos = <&qos_gpu_r>,
 851                                          <&qos_gpu_w>;
 852                         };
 853                 };
 854
 855                 reboot-mode {
 856                         compatible = "syscon-reboot-mode";
 857                         offset = <0x94>;
 858                         mode-normal = <BOOT_NORMAL>;
 859                         mode-recovery = <BOOT_RECOVERY>;
 860                         mode-bootloader = <BOOT_FASTBOOT>;
 861                         mode-loader = <BOOT_BL_DOWNLOAD>;
 862                 };
 863         };
 864
 865         sgrf: syscon@ff740000 {
 866                 compatible = "rockchip,rk3288-sgrf", "syscon";
 867                 reg = <0x0 0xff740000 0x0 0x1000>;
 868         };
 869
 870         cru: clock-controller@ff760000 {
 871                 compatible = "rockchip,rk3288-cru";
 872                 reg = <0x0 0xff760000 0x0 0x1000>;
 873                 rockchip,grf = <&grf>;
 874                 #clock-cells = <1>;
 875                 #reset-cells = <1>;
 876                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 877                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 878                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 879                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 880                                   <&cru PCLK_PERI>;
 881                 assigned-clock-rates = <594000000>, <400000000>,
 882                                        <500000000>, <300000000>,
 883                                        <150000000>, <75000000>,
 884                                        <300000000>, <150000000>,
 885                                        <75000000>;
 886         };
 887
 888         grf: syscon@ff770000 {
 889                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 890                 reg = <0x0 0xff770000 0x0 0x1000>;
 891
 892                 edp_phy: edp-phy {
 893                         compatible = "rockchip,rk3288-dp-phy";
 894                         clocks = <&cru SCLK_EDP_24M>;
 895                         clock-names = "24m";
 896                         #phy-cells = <0>;
 897                         status = "disabled";
 898                 };
 899
 900                 io_domains: io-domains {
 901                         compatible = "rockchip,rk3288-io-voltage-domain";
 902                         status = "disabled";
 903                 };
 904
 905                 usbphy: usbphy {
 906                         compatible = "rockchip,rk3288-usb-phy";
 907                         #address-cells = <1>;
 908                         #size-cells = <0>;
 909                         status = "disabled";
 910
 911                         usbphy0: usb-phy@320 {
 912                                 #phy-cells = <0>;
 913                                 reg = <0x320>;
 914                                 clocks = <&cru SCLK_OTGPHY0>;
 915                                 clock-names = "phyclk";
 916                                 #clock-cells = <0>;
 917                                 resets = <&cru SRST_USBOTG_PHY>;
 918                                 reset-names = "phy-reset";
 919                         };
 920
 921                         usbphy1: usb-phy@334 {
 922                                 #phy-cells = <0>;
 923                                 reg = <0x334>;
 924                                 clocks = <&cru SCLK_OTGPHY1>;
 925                                 clock-names = "phyclk";
 926                                 #clock-cells = <0>;
 927                                 resets = <&cru SRST_USBHOST0_PHY>;
 928                                 reset-names = "phy-reset";
 929                         };
 930
 931                         usbphy2: usb-phy@348 {
 932                                 #phy-cells = <0>;
 933                                 reg = <0x348>;
 934                                 clocks = <&cru SCLK_OTGPHY2>;
 935                                 clock-names = "phyclk";
 936                                 #clock-cells = <0>;
 937                                 resets = <&cru SRST_USBHOST1_PHY>;
 938                                 reset-names = "phy-reset";
 939                         };
 940                 };
 941         };
 942
 943         wdt: watchdog@ff800000 {
 944                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 945                 reg = <0x0 0xff800000 0x0 0x100>;
 946                 clocks = <&cru PCLK_WDT>;
 947                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 948                 status = "disabled";
 949         };
 950
 951         spdif: sound@ff88b0000 {
 952                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 953                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 954                 #sound-dai-cells = <0>;
 955                 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
 956                 clock-names = "mclk", "hclk";
 957                 dmas = <&dmac_bus_s 3>;
 958                 dma-names = "tx";
 959                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 960                 pinctrl-names = "default";
 961                 pinctrl-0 = <&spdif_tx>;
 962                 rockchip,grf = <&grf>;
 963                 status = "disabled";
 964         };
 965
 966         i2s: i2s@ff890000 {
 967                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 968                 reg = <0x0 0xff890000 0x0 0x10000>;
 969                 #sound-dai-cells = <0>;
 970                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 971                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 972                 clock-names = "i2s_clk", "i2s_hclk";
 973                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 974                 dma-names = "tx", "rx";
 975                 pinctrl-names = "default";
 976                 pinctrl-0 = <&i2s0_bus>;
 977                 rockchip,playback-channels = <8>;
 978                 rockchip,capture-channels = <2>;
 979                 status = "disabled";
 980         };
 981
 982         crypto: cypto-controller@ff8a0000 {
 983                 compatible = "rockchip,rk3288-crypto";
 984                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 985                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 986                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 987                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 988                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 989                 resets = <&cru SRST_CRYPTO>;
 990                 reset-names = "crypto-rst";
 991                 status = "okay";
 992         };
 993
 994         iep_mmu: iommu@ff900800 {
 995                 compatible = "rockchip,iommu";
 996                 reg = <0x0 0xff900800 0x0 0x40>;
 997                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 998                 interrupt-names = "iep_mmu";
 999                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1000                 clock-names = "aclk", "iface";
1001                 #iommu-cells = <0>;
1002                 status = "disabled";
1003         };
1004
1005         isp_mmu: iommu@ff914000 {
1006                 compatible = "rockchip,iommu";
1007                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1008                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1009                 interrupt-names = "isp_mmu";
1010                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1011                 clock-names = "aclk", "iface";
1012                 #iommu-cells = <0>;
1013                 rockchip,disable-mmu-reset;
1014                 status = "disabled";
1015         };
1016
1017         rga: rga@ff920000 {
1018                 compatible = "rockchip,rk3288-rga";
1019                 reg = <0x0 0xff920000 0x0 0x180>;
1020                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1021                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1022                 clock-names = "aclk", "hclk", "sclk";
1023                 power-domains = <&power RK3288_PD_VIO>;
1024                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1025                 reset-names = "core", "axi", "ahb";
1026         };
1027
1028         vopb: vop@ff930000 {
1029                 compatible = "rockchip,rk3288-vop";
1030                 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1031                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1032                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1033                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1034                 power-domains = <&power RK3288_PD_VIO>;
1035                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1036                 reset-names = "axi", "ahb", "dclk";
1037                 iommus = <&vopb_mmu>;
1038                 status = "disabled";
1039
1040                 vopb_out: port {
1041                         #address-cells = <1>;
1042                         #size-cells = <0>;
1043
1044                         vopb_out_hdmi: endpoint@0 {
1045                                 reg = <0>;
1046                                 remote-endpoint = <&hdmi_in_vopb>;
1047                         };
1048
1049                         vopb_out_edp: endpoint@1 {
1050                                 reg = <1>;
1051                                 remote-endpoint = <&edp_in_vopb>;
1052                         };
1053
1054                         vopb_out_mipi: endpoint@2 {
1055                                 reg = <2>;
1056                                 remote-endpoint = <&mipi_in_vopb>;
1057                         };
1058
1059                         vopb_out_lvds: endpoint@3 {
1060                                 reg = <3>;
1061                                 remote-endpoint = <&lvds_in_vopb>;
1062                         };
1063                 };
1064         };
1065
1066         vopb_mmu: iommu@ff930300 {
1067                 compatible = "rockchip,iommu";
1068                 reg = <0x0 0xff930300 0x0 0x100>;
1069                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1070                 interrupt-names = "vopb_mmu";
1071                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1072                 clock-names = "aclk", "iface";
1073                 power-domains = <&power RK3288_PD_VIO>;
1074                 #iommu-cells = <0>;
1075                 status = "disabled";
1076         };
1077
1078         vopl: vop@ff940000 {
1079                 compatible = "rockchip,rk3288-vop";
1080                 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1081                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1082                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1083                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1084                 power-domains = <&power RK3288_PD_VIO>;
1085                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1086                 reset-names = "axi", "ahb", "dclk";
1087                 iommus = <&vopl_mmu>;
1088                 status = "disabled";
1089
1090                 vopl_out: port {
1091                         #address-cells = <1>;
1092                         #size-cells = <0>;
1093
1094                         vopl_out_hdmi: endpoint@0 {
1095                                 reg = <0>;
1096                                 remote-endpoint = <&hdmi_in_vopl>;
1097                         };
1098
1099                         vopl_out_edp: endpoint@1 {
1100                                 reg = <1>;
1101                                 remote-endpoint = <&edp_in_vopl>;
1102                         };
1103
1104                         vopl_out_mipi: endpoint@2 {
1105                                 reg = <2>;
1106                                 remote-endpoint = <&mipi_in_vopl>;
1107                         };
1108
1109                         vopl_out_lvds: endpoint@3 {
1110                                 reg = <3>;
1111                                 remote-endpoint = <&lvds_in_vopl>;
1112                         };
1113                 };
1114         };
1115
1116         vopl_mmu: iommu@ff940300 {
1117                 compatible = "rockchip,iommu";
1118                 reg = <0x0 0xff940300 0x0 0x100>;
1119                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1120                 interrupt-names = "vopl_mmu";
1121                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1122                 clock-names = "aclk", "iface";
1123                 power-domains = <&power RK3288_PD_VIO>;
1124                 #iommu-cells = <0>;
1125                 status = "disabled";
1126         };
1127
1128         mipi_dsi: mipi@ff960000 {
1129                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1130                 reg = <0x0 0xff960000 0x0 0x4000>;
1131                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1132                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1133                 clock-names = "ref", "pclk";
1134                 power-domains = <&power RK3288_PD_VIO>;
1135                 rockchip,grf = <&grf>;
1136                 status = "disabled";
1137
1138                 ports {
1139                         mipi_in: port {
1140                                 #address-cells = <1>;
1141                                 #size-cells = <0>;
1142                                 mipi_in_vopb: endpoint@0 {
1143                                         reg = <0>;
1144                                         remote-endpoint = <&vopb_out_mipi>;
1145                                 };
1146                                 mipi_in_vopl: endpoint@1 {
1147                                         reg = <1>;
1148                                         remote-endpoint = <&vopl_out_mipi>;
1149                                 };
1150                         };
1151                 };
1152         };
1153
1154         lvds: lvds@ff96c000 {
1155                 compatible = "rockchip,rk3288-lvds";
1156                 reg = <0x0 0xff96c000 0x0 0x4000>;
1157                 clocks = <&cru PCLK_LVDS_PHY>;
1158                 clock-names = "pclk_lvds";
1159                 pinctrl-names = "lcdc";
1160                 pinctrl-0 = <&lcdc_ctl>;
1161                 power-domains = <&power RK3288_PD_VIO>;
1162                 rockchip,grf = <&grf>;
1163                 status = "disabled";
1164
1165                 ports {
1166                         #address-cells = <1>;
1167                         #size-cells = <0>;
1168
1169                         lvds_in: port@0 {
1170                                 reg = <0>;
1171
1172                                 #address-cells = <1>;
1173                                 #size-cells = <0>;
1174
1175                                 lvds_in_vopb: endpoint@0 {
1176                                         reg = <0>;
1177                                         remote-endpoint = <&vopb_out_lvds>;
1178                                 };
1179                                 lvds_in_vopl: endpoint@1 {
1180                                         reg = <1>;
1181                                         remote-endpoint = <&vopl_out_lvds>;
1182                                 };
1183                         };
1184                 };
1185         };
1186
1187         edp: dp@ff970000 {
1188                 compatible = "rockchip,rk3288-dp";
1189                 reg = <0x0 0xff970000 0x0 0x4000>;
1190                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1191                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1192                 clock-names = "dp", "pclk";
1193                 phys = <&edp_phy>;
1194                 phy-names = "dp";
1195                 resets = <&cru SRST_EDP>;
1196                 reset-names = "dp";
1197                 rockchip,grf = <&grf>;
1198                 status = "disabled";
1199
1200                 ports {
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203                         edp_in: port@0 {
1204                                 reg = <0>;
1205                                 #address-cells = <1>;
1206                                 #size-cells = <0>;
1207                                 edp_in_vopb: endpoint@0 {
1208                                         reg = <0>;
1209                                         remote-endpoint = <&vopb_out_edp>;
1210                                 };
1211                                 edp_in_vopl: endpoint@1 {
1212                                         reg = <1>;
1213                                         remote-endpoint = <&vopl_out_edp>;
1214                                 };
1215                         };
1216                 };
1217         };
1218
1219         hdmi: hdmi@ff980000 {
1220                 compatible = "rockchip,rk3288-dw-hdmi";
1221                 reg = <0x0 0xff980000 0x0 0x20000>;
1222                 reg-io-width = <4>;
1223                 #sound-dai-cells = <0>;
1224                 rockchip,grf = <&grf>;
1225                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1226                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1227                 clock-names = "iahb", "isfr", "cec";
1228                 power-domains = <&power RK3288_PD_VIO>;
1229                 status = "disabled";
1230
1231                 ports {
1232                         hdmi_in: port {
1233                                 #address-cells = <1>;
1234                                 #size-cells = <0>;
1235                                 hdmi_in_vopb: endpoint@0 {
1236                                         reg = <0>;
1237                                         remote-endpoint = <&vopb_out_hdmi>;
1238                                 };
1239                                 hdmi_in_vopl: endpoint@1 {
1240                                         reg = <1>;
1241                                         remote-endpoint = <&vopl_out_hdmi>;
1242                                 };
1243                         };
1244                 };
1245         };
1246
1247         vpu: video-codec@ff9a0000 {
1248                 compatible = "rockchip,rk3288-vpu";
1249                 reg = <0x0 0xff9a0000 0x0 0x800>;
1250                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1251                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1252                 interrupt-names = "vepu", "vdpu";
1253                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1254                 clock-names = "aclk", "hclk";
1255                 iommus = <&vpu_mmu>;
1256                 power-domains = <&power RK3288_PD_VIDEO>;
1257         };
1258
1259         vpu_mmu: iommu@ff9a0800 {
1260                 compatible = "rockchip,iommu";
1261                 reg = <0x0 0xff9a0800 0x0 0x100>;
1262                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1263                 interrupt-names = "vpu_mmu";
1264                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1265                 clock-names = "aclk", "iface";
1266                 #iommu-cells = <0>;
1267                 power-domains = <&power RK3288_PD_VIDEO>;
1268         };
1269
1270         hevc_mmu: iommu@ff9c0440 {
1271                 compatible = "rockchip,iommu";
1272                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1273                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1274                 interrupt-names = "hevc_mmu";
1275                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1276                 clock-names = "aclk", "iface";
1277                 #iommu-cells = <0>;
1278                 status = "disabled";
1279         };
1280
1281         gpu: gpu@ffa30000 {
1282                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1283                 reg = <0x0 0xffa30000 0x0 0x10000>;
1284                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1285                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1286                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1287                 interrupt-names = "job", "mmu", "gpu";
1288                 clocks = <&cru ACLK_GPU>;
1289                 operating-points-v2 = <&gpu_opp_table>;
1290                 #cooling-cells = <2>; /* min followed by max */
1291                 power-domains = <&power RK3288_PD_GPU>;
1292                 status = "disabled";
1293         };
1294
1295         gpu_opp_table: gpu-opp-table {
1296                 compatible = "operating-points-v2";
1297
1298                 opp-100000000 {
1299                         opp-hz = /bits/ 64 <100000000>;
1300                         opp-microvolt = <950000>;
1301                 };
1302                 opp-200000000 {
1303                         opp-hz = /bits/ 64 <200000000>;
1304                         opp-microvolt = <950000>;
1305                 };
1306                 opp-300000000 {
1307                         opp-hz = /bits/ 64 <300000000>;
1308                         opp-microvolt = <1000000>;
1309                 };
1310                 opp-400000000 {
1311                         opp-hz = /bits/ 64 <400000000>;
1312                         opp-microvolt = <1100000>;
1313                 };
1314                 opp-600000000 {
1315                         opp-hz = /bits/ 64 <600000000>;
1316                         opp-microvolt = <1250000>;
1317                 };
1318         };
1319
1320         qos_gpu_r: qos@ffaa0000 {
1321                 compatible = "syscon";
1322                 reg = <0x0 0xffaa0000 0x0 0x20>;
1323         };
1324
1325         qos_gpu_w: qos@ffaa0080 {
1326                 compatible = "syscon";
1327                 reg = <0x0 0xffaa0080 0x0 0x20>;
1328         };
1329
1330         qos_vio1_vop: qos@ffad0000 {
1331                 compatible = "syscon";
1332                 reg = <0x0 0xffad0000 0x0 0x20>;
1333         };
1334
1335         qos_vio1_isp_w0: qos@ffad0100 {
1336                 compatible = "syscon";
1337                 reg = <0x0 0xffad0100 0x0 0x20>;
1338         };
1339
1340         qos_vio1_isp_w1: qos@ffad0180 {
1341                 compatible = "syscon";
1342                 reg = <0x0 0xffad0180 0x0 0x20>;
1343         };
1344
1345         qos_vio0_vop: qos@ffad0400 {
1346                 compatible = "syscon";
1347                 reg = <0x0 0xffad0400 0x0 0x20>;
1348         };
1349
1350         qos_vio0_vip: qos@ffad0480 {
1351                 compatible = "syscon";
1352                 reg = <0x0 0xffad0480 0x0 0x20>;
1353         };
1354
1355         qos_vio0_iep: qos@ffad0500 {
1356                 compatible = "syscon";
1357                 reg = <0x0 0xffad0500 0x0 0x20>;
1358         };
1359
1360         qos_vio2_rga_r: qos@ffad0800 {
1361                 compatible = "syscon";
1362                 reg = <0x0 0xffad0800 0x0 0x20>;
1363         };
1364
1365         qos_vio2_rga_w: qos@ffad0880 {
1366                 compatible = "syscon";
1367                 reg = <0x0 0xffad0880 0x0 0x20>;
1368         };
1369
1370         qos_vio1_isp_r: qos@ffad0900 {
1371                 compatible = "syscon";
1372                 reg = <0x0 0xffad0900 0x0 0x20>;
1373         };
1374
1375         qos_video: qos@ffae0000 {
1376                 compatible = "syscon";
1377                 reg = <0x0 0xffae0000 0x0 0x20>;
1378         };
1379
1380         qos_hevc_r: qos@ffaf0000 {
1381                 compatible = "syscon";
1382                 reg = <0x0 0xffaf0000 0x0 0x20>;
1383         };
1384
1385         qos_hevc_w: qos@ffaf0080 {
1386                 compatible = "syscon";
1387                 reg = <0x0 0xffaf0080 0x0 0x20>;
1388         };
1389
1390         efuse: efuse@ffb40000 {
1391                 compatible = "rockchip,rk3288-efuse";
1392                 reg = <0x0 0xffb40000 0x0 0x20>;
1393                 #address-cells = <1>;
1394                 #size-cells = <1>;
1395                 clocks = <&cru PCLK_EFUSE256>;
1396                 clock-names = "pclk_efuse";
1397
1398                 cpu_id: cpu-id@7 {
1399                         reg = <0x07 0x10>;
1400                 };
1401                 cpu_leakage: cpu_leakage@17 {
1402                         reg = <0x17 0x1>;
1403                 };
1404         };
1405
1406         gic: interrupt-controller@ffc01000 {
1407                 compatible = "arm,gic-400";
1408                 interrupt-controller;
1409                 #interrupt-cells = <3>;
1410                 #address-cells = <0>;
1411
1412                 reg = <0x0 0xffc01000 0x0 0x1000>,
1413                       <0x0 0xffc02000 0x0 0x2000>,
1414                       <0x0 0xffc04000 0x0 0x2000>,
1415                       <0x0 0xffc06000 0x0 0x2000>;
1416                 interrupts = <GIC_PPI 9 0xf04>;
1417         };
1418
1419         pinctrl: pinctrl {
1420                 compatible = "rockchip,rk3288-pinctrl";
1421                 rockchip,grf = <&grf>;
1422                 rockchip,pmu = <&pmu>;
1423                 #address-cells = <2>;
1424                 #size-cells = <2>;
1425                 ranges;
1426
1427                 gpio0: gpio0@ff750000 {
1428                         compatible = "rockchip,gpio-bank";
1429                         reg = <0x0 0xff750000 0x0 0x100>;
1430                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1431                         clocks = <&cru PCLK_GPIO0>;
1432
1433                         gpio-controller;
1434                         #gpio-cells = <2>;
1435
1436                         interrupt-controller;
1437                         #interrupt-cells = <2>;
1438                 };
1439
1440                 gpio1: gpio1@ff780000 {
1441                         compatible = "rockchip,gpio-bank";
1442                         reg = <0x0 0xff780000 0x0 0x100>;
1443                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1444                         clocks = <&cru PCLK_GPIO1>;
1445
1446                         gpio-controller;
1447                         #gpio-cells = <2>;
1448
1449                         interrupt-controller;
1450                         #interrupt-cells = <2>;
1451                 };
1452
1453                 gpio2: gpio2@ff790000 {
1454                         compatible = "rockchip,gpio-bank";
1455                         reg = <0x0 0xff790000 0x0 0x100>;
1456                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1457                         clocks = <&cru PCLK_GPIO2>;
1458
1459                         gpio-controller;
1460                         #gpio-cells = <2>;
1461
1462                         interrupt-controller;
1463                         #interrupt-cells = <2>;
1464                 };
1465
1466                 gpio3: gpio3@ff7a0000 {
1467                         compatible = "rockchip,gpio-bank";
1468                         reg = <0x0 0xff7a0000 0x0 0x100>;
1469                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1470                         clocks = <&cru PCLK_GPIO3>;
1471
1472                         gpio-controller;
1473                         #gpio-cells = <2>;
1474
1475                         interrupt-controller;
1476                         #interrupt-cells = <2>;
1477                 };
1478
1479                 gpio4: gpio4@ff7b0000 {
1480                         compatible = "rockchip,gpio-bank";
1481                         reg = <0x0 0xff7b0000 0x0 0x100>;
1482                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1483                         clocks = <&cru PCLK_GPIO4>;
1484
1485                         gpio-controller;
1486                         #gpio-cells = <2>;
1487
1488                         interrupt-controller;
1489                         #interrupt-cells = <2>;
1490                 };
1491
1492                 gpio5: gpio5@ff7c0000 {
1493                         compatible = "rockchip,gpio-bank";
1494                         reg = <0x0 0xff7c0000 0x0 0x100>;
1495                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1496                         clocks = <&cru PCLK_GPIO5>;
1497
1498                         gpio-controller;
1499                         #gpio-cells = <2>;
1500
1501                         interrupt-controller;
1502                         #interrupt-cells = <2>;
1503                 };
1504
1505                 gpio6: gpio6@ff7d0000 {
1506                         compatible = "rockchip,gpio-bank";
1507                         reg = <0x0 0xff7d0000 0x0 0x100>;
1508                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1509                         clocks = <&cru PCLK_GPIO6>;
1510
1511                         gpio-controller;
1512                         #gpio-cells = <2>;
1513
1514                         interrupt-controller;
1515                         #interrupt-cells = <2>;
1516                 };
1517
1518                 gpio7: gpio7@ff7e0000 {
1519                         compatible = "rockchip,gpio-bank";
1520                         reg = <0x0 0xff7e0000 0x0 0x100>;
1521                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1522                         clocks = <&cru PCLK_GPIO7>;
1523
1524                         gpio-controller;
1525                         #gpio-cells = <2>;
1526
1527                         interrupt-controller;
1528                         #interrupt-cells = <2>;
1529                 };
1530
1531                 gpio8: gpio8@ff7f0000 {
1532                         compatible = "rockchip,gpio-bank";
1533                         reg = <0x0 0xff7f0000 0x0 0x100>;
1534                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1535                         clocks = <&cru PCLK_GPIO8>;
1536
1537                         gpio-controller;
1538                         #gpio-cells = <2>;
1539
1540                         interrupt-controller;
1541                         #interrupt-cells = <2>;
1542                 };
1543
1544                 hdmi {
1545                         hdmi_cec_c0: hdmi-cec-c0 {
1546                                 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1547                         };
1548
1549                         hdmi_cec_c7: hdmi-cec-c7 {
1550                                 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1551                         };
1552
1553                         hdmi_ddc: hdmi-ddc {
1554                                 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1555                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1556                         };
1557
1558                         hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1559                                 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1560                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1561                         };
1562                 };
1563
1564                 pcfg_output_low: pcfg-output-low {
1565                         output-low;
1566                 };
1567
1568                 pcfg_pull_up: pcfg-pull-up {
1569                         bias-pull-up;
1570                 };
1571
1572                 pcfg_pull_down: pcfg-pull-down {
1573                         bias-pull-down;
1574                 };
1575
1576                 pcfg_pull_none: pcfg-pull-none {
1577                         bias-disable;
1578                 };
1579
1580                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1581                         bias-disable;
1582                         drive-strength = <12>;
1583                 };
1584
1585                 sleep {
1586                         global_pwroff: global-pwroff {
1587                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1588                         };
1589
1590                         ddrio_pwroff: ddrio-pwroff {
1591                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1592                         };
1593
1594                         ddr0_retention: ddr0-retention {
1595                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1596                         };
1597
1598                         ddr1_retention: ddr1-retention {
1599                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1600                         };
1601                 };
1602
1603                 edp {
1604                         edp_hpd: edp-hpd {
1605                                 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1606                         };
1607                 };
1608
1609                 i2c0 {
1610                         i2c0_xfer: i2c0-xfer {
1611                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1612                                                 <0 RK_PC0 1 &pcfg_pull_none>;
1613                         };
1614                 };
1615
1616                 i2c1 {
1617                         i2c1_xfer: i2c1-xfer {
1618                                 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1619                                                 <8 RK_PA5 1 &pcfg_pull_none>;
1620                         };
1621                 };
1622
1623                 i2c2 {
1624                         i2c2_xfer: i2c2-xfer {
1625                                 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1626                                                 <6 RK_PB2 1 &pcfg_pull_none>;
1627                         };
1628                 };
1629
1630                 i2c3 {
1631                         i2c3_xfer: i2c3-xfer {
1632                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1633                                                 <2 RK_PC1 1 &pcfg_pull_none>;
1634                         };
1635                 };
1636
1637                 i2c4 {
1638                         i2c4_xfer: i2c4-xfer {
1639                                 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1640                                                 <7 RK_PC2 1 &pcfg_pull_none>;
1641                         };
1642                 };
1643
1644                 i2c5 {
1645                         i2c5_xfer: i2c5-xfer {
1646                                 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1647                                                 <7 RK_PC4 1 &pcfg_pull_none>;
1648                         };
1649                 };
1650
1651                 i2s0 {
1652                         i2s0_bus: i2s0-bus {
1653                                 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1654                                                 <6 RK_PA1 1 &pcfg_pull_none>,
1655                                                 <6 RK_PA2 1 &pcfg_pull_none>,
1656                                                 <6 RK_PA3 1 &pcfg_pull_none>,
1657                                                 <6 RK_PA4 1 &pcfg_pull_none>,
1658                                                 <6 RK_PB0 1 &pcfg_pull_none>;
1659                         };
1660                 };
1661
1662                 lcdc {
1663                         lcdc_ctl: lcdc-ctl {
1664                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1665                                                 <1 RK_PD1 1 &pcfg_pull_none>,
1666                                                 <1 RK_PD2 1 &pcfg_pull_none>,
1667                                                 <1 RK_PD3 1 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 sdmmc {
1672                         sdmmc_clk: sdmmc-clk {
1673                                 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1674                         };
1675
1676                         sdmmc_cmd: sdmmc-cmd {
1677                                 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1678                         };
1679
1680                         sdmmc_cd: sdmmc-cd {
1681                                 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1682                         };
1683
1684                         sdmmc_bus1: sdmmc-bus1 {
1685                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1686                         };
1687
1688                         sdmmc_bus4: sdmmc-bus4 {
1689                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1690                                                 <6 RK_PC1 1 &pcfg_pull_up>,
1691                                                 <6 RK_PC2 1 &pcfg_pull_up>,
1692                                                 <6 RK_PC3 1 &pcfg_pull_up>;
1693                         };
1694                 };
1695
1696                 sdio0 {
1697                         sdio0_bus1: sdio0-bus1 {
1698                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1699                         };
1700
1701                         sdio0_bus4: sdio0-bus4 {
1702                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1703                                                 <4 RK_PC5 1 &pcfg_pull_up>,
1704                                                 <4 RK_PC6 1 &pcfg_pull_up>,
1705                                                 <4 RK_PC7 1 &pcfg_pull_up>;
1706                         };
1707
1708                         sdio0_cmd: sdio0-cmd {
1709                                 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1710                         };
1711
1712                         sdio0_clk: sdio0-clk {
1713                                 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1714                         };
1715
1716                         sdio0_cd: sdio0-cd {
1717                                 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1718                         };
1719
1720                         sdio0_wp: sdio0-wp {
1721                                 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1722                         };
1723
1724                         sdio0_pwr: sdio0-pwr {
1725                                 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1726                         };
1727
1728                         sdio0_bkpwr: sdio0-bkpwr {
1729                                 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1730                         };
1731
1732                         sdio0_int: sdio0-int {
1733                                 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1734                         };
1735                 };
1736
1737                 sdio1 {
1738                         sdio1_bus1: sdio1-bus1 {
1739                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1740                         };
1741
1742                         sdio1_bus4: sdio1-bus4 {
1743                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1744                                                 <3 RK_PD1 4 &pcfg_pull_up>,
1745                                                 <3 RK_PD2 4 &pcfg_pull_up>,
1746                                                 <3 RK_PD3 4 &pcfg_pull_up>;
1747                         };
1748
1749                         sdio1_cd: sdio1-cd {
1750                                 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1751                         };
1752
1753                         sdio1_wp: sdio1-wp {
1754                                 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1755                         };
1756
1757                         sdio1_bkpwr: sdio1-bkpwr {
1758                                 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1759                         };
1760
1761                         sdio1_int: sdio1-int {
1762                                 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1763                         };
1764
1765                         sdio1_cmd: sdio1-cmd {
1766                                 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1767                         };
1768
1769                         sdio1_clk: sdio1-clk {
1770                                 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1771                         };
1772
1773                         sdio1_pwr: sdio1-pwr {
1774                                 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1775                         };
1776                 };
1777
1778                 emmc {
1779                         emmc_clk: emmc-clk {
1780                                 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1781                         };
1782
1783                         emmc_cmd: emmc-cmd {
1784                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1785                         };
1786
1787                         emmc_pwr: emmc-pwr {
1788                                 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1789                         };
1790
1791                         emmc_bus1: emmc-bus1 {
1792                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1793                         };
1794
1795                         emmc_bus4: emmc-bus4 {
1796                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1797                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1798                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1799                                                 <3 RK_PA3 2 &pcfg_pull_up>;
1800                         };
1801
1802                         emmc_bus8: emmc-bus8 {
1803                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1804                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1805                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1806                                                 <3 RK_PA3 2 &pcfg_pull_up>,
1807                                                 <3 RK_PA4 2 &pcfg_pull_up>,
1808                                                 <3 RK_PA5 2 &pcfg_pull_up>,
1809                                                 <3 RK_PA6 2 &pcfg_pull_up>,
1810                                                 <3 RK_PA7 2 &pcfg_pull_up>;
1811                         };
1812                 };
1813
1814                 spi0 {
1815                         spi0_clk: spi0-clk {
1816                                 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1817                         };
1818                         spi0_cs0: spi0-cs0 {
1819                                 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1820                         };
1821                         spi0_tx: spi0-tx {
1822                                 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1823                         };
1824                         spi0_rx: spi0-rx {
1825                                 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1826                         };
1827                         spi0_cs1: spi0-cs1 {
1828                                 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1829                         };
1830                 };
1831                 spi1 {
1832                         spi1_clk: spi1-clk {
1833                                 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1834                         };
1835                         spi1_cs0: spi1-cs0 {
1836                                 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1837                         };
1838                         spi1_rx: spi1-rx {
1839                                 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1840                         };
1841                         spi1_tx: spi1-tx {
1842                                 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1843                         };
1844                 };
1845
1846                 spi2 {
1847                         spi2_cs1: spi2-cs1 {
1848                                 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1849                         };
1850                         spi2_clk: spi2-clk {
1851                                 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1852                         };
1853                         spi2_cs0: spi2-cs0 {
1854                                 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1855                         };
1856                         spi2_rx: spi2-rx {
1857                                 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1858                         };
1859                         spi2_tx: spi2-tx {
1860                                 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1861                         };
1862                 };
1863
1864                 uart0 {
1865                         uart0_xfer: uart0-xfer {
1866                                 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1867                                                 <4 RK_PC1 1 &pcfg_pull_none>;
1868                         };
1869
1870                         uart0_cts: uart0-cts {
1871                                 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1872                         };
1873
1874                         uart0_rts: uart0-rts {
1875                                 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1876                         };
1877                 };
1878
1879                 uart1 {
1880                         uart1_xfer: uart1-xfer {
1881                                 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1882                                                 <5 RK_PB1 1 &pcfg_pull_none>;
1883                         };
1884
1885                         uart1_cts: uart1-cts {
1886                                 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1887                         };
1888
1889                         uart1_rts: uart1-rts {
1890                                 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1891                         };
1892                 };
1893
1894                 uart2 {
1895                         uart2_xfer: uart2-xfer {
1896                                 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1897                                                 <7 RK_PC7 1 &pcfg_pull_none>;
1898                         };
1899                         /* no rts / cts for uart2 */
1900                 };
1901
1902                 uart3 {
1903                         uart3_xfer: uart3-xfer {
1904                                 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1905                                                 <7 RK_PB0 1 &pcfg_pull_none>;
1906                         };
1907
1908                         uart3_cts: uart3-cts {
1909                                 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1910                         };
1911
1912                         uart3_rts: uart3-rts {
1913                                 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1914                         };
1915                 };
1916
1917                 uart4 {
1918                         uart4_xfer: uart4-xfer {
1919                                 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1920                                                 <5 RK_PB6 3 &pcfg_pull_none>;
1921                         };
1922
1923                         uart4_cts: uart4-cts {
1924                                 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1925                         };
1926
1927                         uart4_rts: uart4-rts {
1928                                 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 tsadc {
1933                         otp_gpio: otp-gpio {
1934                                 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1935                         };
1936
1937                         otp_out: otp-out {
1938                                 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1939                         };
1940                 };
1941
1942                 pwm0 {
1943                         pwm0_pin: pwm0-pin {
1944                                 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1945                         };
1946                 };
1947
1948                 pwm1 {
1949                         pwm1_pin: pwm1-pin {
1950                                 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1951                         };
1952                 };
1953
1954                 pwm2 {
1955                         pwm2_pin: pwm2-pin {
1956                                 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1957                         };
1958                 };
1959
1960                 pwm3 {
1961                         pwm3_pin: pwm3-pin {
1962                                 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1963                         };
1964                 };
1965
1966                 gmac {
1967                         rgmii_pins: rgmii-pins {
1968                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1969                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1970                                                 <3 RK_PD2 3 &pcfg_pull_none>,
1971                                                 <3 RK_PD3 3 &pcfg_pull_none>,
1972                                                 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1973                                                 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1974                                                 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1975                                                 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1976                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1977                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1978                                                 <4 RK_PA6 3 &pcfg_pull_none>,
1979                                                 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1980                                                 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1981                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1982                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1983                         };
1984
1985                         rmii_pins: rmii-pins {
1986                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1987                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1988                                                 <3 RK_PD4 3 &pcfg_pull_none>,
1989                                                 <3 RK_PD5 3 &pcfg_pull_none>,
1990                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1991                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1992                                                 <4 RK_PA4 3 &pcfg_pull_none>,
1993                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1994                                                 <4 RK_PA2 3 &pcfg_pull_none>,
1995                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1996                         };
1997                 };
1998
1999                 spdif {
2000                         spdif_tx: spdif-tx {
2001                                 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2002                         };
2003                 };
2004         };
2005 };