1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Veyron (and derivatives) board device tree source
5 * Copyright 2015 Google, Inc
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288.dtsi"
14 stdout-path = "serial2:115200n8";
18 * The default coreboot on veyron devices ignores memory@0 nodes
19 * and would instead create another memory node.
22 device_type = "memory";
23 reg = <0x0 0x0 0x0 0x80000000>;
27 power_button: power-button {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pwr_key_l>;
34 gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_POWER>;
36 debounce-interval = <100>;
42 compatible = "gpio-restart";
43 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&ap_warm_reset_h>;
49 emmc_pwrseq: emmc-pwrseq {
50 compatible = "mmc-pwrseq-emmc";
51 pinctrl-0 = <&emmc_reset>;
52 pinctrl-names = "default";
53 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
56 sdio_pwrseq: sdio-pwrseq {
57 compatible = "mmc-pwrseq-simple";
58 clocks = <&rk808 RK808_CLKOUT1>;
59 clock-names = "ext_clock";
60 pinctrl-names = "default";
61 pinctrl-0 = <&wifi_enable_h>;
64 * Depending on the actual card populated GPIO4 D4
65 * correspond to one of these signals on the module:
68 * - SDIO_RESET_L_WL_REG_ON
69 * - PDN (power down when low)
71 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
75 compatible = "regulator-fixed";
76 regulator-name = "vcc_5v";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
83 vcc33_sys: vcc33-sys {
84 compatible = "regulator-fixed";
85 regulator-name = "vcc33_sys";
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
92 vcc50_hdmi: vcc50-hdmi {
93 compatible = "regulator-fixed";
94 regulator-name = "vcc50_hdmi";
97 vin-supply = <&vcc_5v>;
100 vdd_logic: vdd-logic {
101 compatible = "pwm-regulator";
102 regulator-name = "vdd_logic";
104 pwms = <&pwm1 0 1994 0>;
105 pwm-supply = <&vcc33_sys>;
107 pwm-dutycycle-range = <0x7b 0>;
108 pwm-dutycycle-unit = <0x94>;
112 regulator-min-microvolt = <950000>;
113 regulator-max-microvolt = <1350000>;
114 regulator-ramp-delay = <4000>;
119 cpu0-supply = <&vdd_cpu>;
123 temperature = <100000>;
126 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
128 /delete-node/ opp-312000000;
131 opp-microvolt = <1250000>;
134 opp-microvolt = <1300000>;
137 opp-hz = /bits/ 64 <1704000000>;
138 opp-microvolt = <1350000>;
141 opp-hz = /bits/ 64 <1800000000>;
142 opp-microvolt = <1400000>;
151 rockchip,default-sample-phase = <158>;
154 mmc-pwrseq = <&emmc_pwrseq>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
161 mali-supply = <&vdd_gpu>;
166 temperature = <72500>;
170 temperature = <100000>;
174 pinctrl-names = "default", "unwedge";
175 pinctrl-0 = <&hdmi_ddc>;
176 pinctrl-1 = <&hdmi_ddc_unwedge>;
183 clock-frequency = <400000>;
184 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
185 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
188 compatible = "rockchip,rk808";
190 clock-output-names = "xin32k", "wifibt_32kin";
191 interrupt-parent = <&gpio0>;
192 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pmic_int_l>;
195 rockchip,system-power-controller;
199 vcc1-supply = <&vcc33_sys>;
200 vcc2-supply = <&vcc33_sys>;
201 vcc3-supply = <&vcc33_sys>;
202 vcc4-supply = <&vcc33_sys>;
203 vcc6-supply = <&vcc_5v>;
204 vcc7-supply = <&vcc33_sys>;
205 vcc8-supply = <&vcc33_sys>;
206 vcc12-supply = <&vcc_18>;
207 vddio-supply = <&vcc33_io>;
211 regulator-name = "vdd_arm";
214 regulator-min-microvolt = <750000>;
215 regulator-max-microvolt = <1450000>;
216 regulator-ramp-delay = <6001>;
217 regulator-state-mem {
218 regulator-off-in-suspend;
223 regulator-name = "vdd_gpu";
226 regulator-min-microvolt = <800000>;
227 regulator-max-microvolt = <1250000>;
228 regulator-ramp-delay = <6001>;
229 regulator-state-mem {
230 regulator-off-in-suspend;
234 vcc135_ddr: DCDC_REG3 {
235 regulator-name = "vcc135_ddr";
238 regulator-state-mem {
239 regulator-on-in-suspend;
244 * vcc_18 has several aliases. (vcc18_flashio and
245 * vcc18_wl). We'll add those aliases here just to
246 * make it easier to follow the schematic. The signals
247 * are actually hooked together and only separated for
248 * power measurement purposes).
250 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
251 regulator-name = "vcc_18";
254 regulator-min-microvolt = <1800000>;
255 regulator-max-microvolt = <1800000>;
256 regulator-state-mem {
257 regulator-on-in-suspend;
258 regulator-suspend-microvolt = <1800000>;
263 * Note that both vcc33_io and vcc33_pmuio are always
264 * powered together. To simplify the logic in the dts
265 * we just refer to vcc33_io every time something is
266 * powered from vcc33_pmuio. In fact, on later boards
267 * (such as danger) they're the same net.
270 regulator-name = "vcc33_io";
273 regulator-min-microvolt = <3300000>;
274 regulator-max-microvolt = <3300000>;
275 regulator-state-mem {
276 regulator-on-in-suspend;
277 regulator-suspend-microvolt = <3300000>;
282 regulator-name = "vdd_10";
285 regulator-min-microvolt = <1000000>;
286 regulator-max-microvolt = <1000000>;
287 regulator-state-mem {
288 regulator-on-in-suspend;
289 regulator-suspend-microvolt = <1000000>;
293 vdd10_lcd_pwren_h: LDO_REG7 {
294 regulator-name = "vdd10_lcd_pwren_h";
297 regulator-min-microvolt = <2500000>;
298 regulator-max-microvolt = <2500000>;
299 regulator-state-mem {
300 regulator-off-in-suspend;
304 vcc33_lcd: SWITCH_REG1 {
305 regulator-name = "vcc33_lcd";
308 regulator-state-mem {
309 regulator-off-in-suspend;
319 clock-frequency = <400000>;
320 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
321 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
324 compatible = "infineon,slb9645tt";
326 powered-while-suspended;
333 /* 100kHz since 4.7k resistors don't rise fast enough */
334 clock-frequency = <100000>;
335 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
336 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
342 clock-frequency = <400000>;
343 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
344 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
350 bb-supply = <&vcc33_io>;
351 dvp-supply = <&vcc_18>;
352 flash0-supply = <&vcc18_flashio>;
353 gpio1830-supply = <&vcc33_io>;
354 gpio30-supply = <&vcc33_io>;
355 lcdc-supply = <&vcc33_lcd>;
356 wifi-supply = <&vcc18_wl>;
369 keep-power-in-suspend;
370 mmc-pwrseq = <&sdio_pwrseq>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
378 vmmc-supply = <&vcc33_sys>;
379 vqmmc-supply = <&vcc18_wl>;
385 rx-sample-delay-ns = <12>;
388 compatible = "jedec,spi-nor";
389 spi-max-frequency = <50000000>;
397 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
398 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
399 rockchip,hw-tshut-temp = <125000>;
405 /* Pins don't include flow control by default; add that in */
406 pinctrl-names = "default";
407 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
425 needs-reset-on-resume;
430 snps,need-phy-for-wake;
436 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
437 assigned-clock-parents = <&usbphy0>;
439 snps,need-phy-for-wake;
455 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
457 drive-strength = <8>;
460 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
462 drive-strength = <8>;
465 pcfg_output_high: pcfg-output-high {
469 pcfg_output_low: pcfg-output-low {
474 pwr_key_l: pwr-key-l {
475 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
480 emmc_reset: emmc-reset {
481 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
485 * We run eMMC at max speed; bump up drive strength.
486 * We also have external pulls, so disable the internal ones.
489 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
493 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
496 emmc_bus8: emmc-bus8 {
497 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
498 <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
499 <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
500 <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
501 <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
502 <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
503 <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
504 <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
509 pmic_int_l: pmic-int-l {
510 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
515 ap_warm_reset_h: ap-warm-reset-h {
516 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
521 rec_mode_l: rec-mode-l {
522 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
527 wifi_enable_h: wifienable-h {
528 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
531 /* NOTE: mislabelled on schematic; should be bt_enable_h */
532 bt_enable_l: bt-enable-l {
533 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
536 bt_host_wake: bt-host-wake {
537 rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
540 bt_host_wake_l: bt-host-wake-l {
541 rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
545 * We run sdio0 at max speed; bump up drive strength.
546 * We also have external pulls, so disable the internal ones.
548 sdio0_bus4: sdio0-bus4 {
549 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
550 <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
551 <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
552 <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
555 sdio0_cmd: sdio0-cmd {
556 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
559 sdio0_clk: sdio0-clk {
560 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
564 * These pins are only present on very new veyron boards; on
565 * older boards bt_dev_wake is simply always high. Note that
566 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
567 * to map this pin everywhere
569 bt_dev_wake_sleep: bt-dev-wake-sleep {
570 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
573 bt_dev_wake_awake: bt-dev-wake-awake {
574 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
577 bt_dev_wake: bt-dev-wake {
578 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
583 tpm_int_h: tpm-int-h {
584 rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
590 rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;