1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Veyron Minnie Rev 0+ board device tree source
5 * Copyright 2015 Google, Inc
9 #include "rk3288-veyron-chromebook.dtsi"
12 model = "Google Minnie";
13 compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
14 "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
15 "google,veyron-minnie-rev0", "google,veyron-minnie",
16 "google,veyron", "rockchip,rk3288";
18 volume_buttons: volume-buttons {
19 compatible = "gpio-keys";
20 pinctrl-names = "default";
21 pinctrl-0 = <&volum_down_l &volum_up_l>;
25 gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
26 linux,code = <KEY_VOLUMEDOWN>;
27 debounce-interval = <100>;
32 gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
33 linux,code = <KEY_VOLUMEUP>;
34 debounce-interval = <100>;
40 /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
44 16 17 18 19 20 21 22 23
45 24 25 26 27 28 29 30 31
46 32 33 34 35 36 37 38 39
47 40 41 42 43 44 45 46 47
48 48 49 50 51 52 53 54 55
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51 72 73 74 75 76 77 78 79
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54 96 97 98 99 100 101 102 103
55 104 105 106 107 108 109 110 111
56 112 113 114 115 116 117 118 119
57 120 121 122 123 124 125 126 127
58 128 129 130 131 132 133 134 135
59 136 137 138 139 140 141 142 143
60 144 145 146 147 148 149 150 151
61 152 153 154 155 156 157 158 159
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63 168 169 170 171 172 173 174 175
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65 184 185 186 187 188 189 190 191
66 192 193 194 195 196 197 198 199
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69 216 217 218 219 220 221 222 223
70 224 225 226 227 228 229 230 231
71 232 233 234 235 236 237 238 239
72 240 241 242 243 244 245 246 247
73 248 249 250 251 252 253 254 255>;
78 compatible = "ti,bq27500";
86 clock-frequency = <400000>;
87 i2c-scl-falling-time-ns = <50>;
88 i2c-scl-rising-time-ns = <300>;
91 compatible = "elan,ekth3500";
93 interrupt-parent = <&gpio2>;
94 interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&touch_int &touch_rst>;
97 reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
98 vcc33-supply = <&vcc33_touch>;
99 vccio-supply = <&vcc33_touch>;
104 compatible = "auo,b101ean01", "simple-panel";
106 /delete-node/ panel-timing;
109 clock-frequency = <66666667>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
126 vcc33_touch: LDO_REG2 {
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
129 regulator-name = "vcc33_touch";
130 regulator-state-mem {
131 regulator-off-in-suspend;
135 vcc5v_touch: SWITCH_REG2 {
136 regulator-name = "vcc5v_touch";
137 regulator-state-mem {
138 regulator-off-in-suspend;
146 pinctrl-names = "default";
147 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
153 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&drv_5v>;
160 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&vcc50_hdmi_en>;
166 gpio-line-names = "PMIC_SLEEP_AP",
177 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
194 gpio-line-names = "CONFIG0",
217 gpio-line-names = "FLASH0_D0",
235 "FLASH0_CS2/EMMC_CMD",
237 "FLASH0_DQS/EMMC_CLKO";
241 gpio-line-names = "",
279 gpio-line-names = "",
304 gpio-line-names = "I2S0_SCLK",
331 gpio-line-names = "LCDC_BL",
338 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
364 gpio-line-names = "RAM_ID0",
380 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
385 volum_down_l: volum-down-l {
386 rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
389 volum_up_l: volum-up-l {
390 rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
395 vcc50_hdmi_en: vcc50-hdmi-en {
396 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
402 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
406 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
411 gpio_prochot: gpio-prochot {
412 rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
417 touch_int: touch-int {
418 rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
421 touch_rst: touch-rst {
422 rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;