arch/arm/boot/dts/rk3288-veyron-jaq.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron Jaq Rev 1+ board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "rk3288-veyron-chromebook.dtsi"
  11 #include "cros-ec-sbs.dtsi"
  12
  13 / {
  14         model = "Google Jaq";
  15         compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
  16                      "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
  17                      "google,veyron-jaq-rev1", "google,veyron-jaq",
  18                      "google,veyron", "rockchip,rk3288";
  19 };
  20
  21 &backlight {
  22         /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
  23         brightness-levels = <0 8 255>;
  24         num-interpolated-steps = <247>;
  25 };
  26
  27 &rk808 {
  28         pinctrl-names = "default";
  29         pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
  30         dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
  31                     <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
  32
  33         regulators {
  34                 mic_vcc: LDO_REG2 {
  35                         regulator-name = "mic_vcc";
  36                         regulator-always-on;
  37                         regulator-boot-on;
  38                         regulator-min-microvolt = <1800000>;
  39                         regulator-max-microvolt = <1800000>;
  40                         regulator-state-mem {
  41                                 regulator-off-in-suspend;
  42                         };
  43                 };
  44         };
  45 };
  46
  47 &sdmmc {
  48         disable-wp;
  49         pinctrl-names = "default";
  50         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
  51                         &sdmmc_bus4>;
  52 };
  53
  54 &vcc_5v {
  55         enable-active-high;
  56         gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
  57         pinctrl-names = "default";
  58         pinctrl-0 = <&drv_5v>;
  59 };
  60
  61 &vcc50_hdmi {
  62         enable-active-high;
  63         gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&vcc50_hdmi_en>;
  66 };
  67
  68 &gpio0 {
  69         gpio-line-names = "PMIC_SLEEP_AP",
  70                           "DDRIO_PWROFF",
  71                           "DDRIO_RETEN",
  72                           "TS3A227E_INT_L",
  73                           "PMIC_INT_L",
  74                           "PWR_KEY_L",
  75                           "AP_LID_INT_L",
  76                           "EC_IN_RW",
  77
  78                           "AC_PRESENT_AP",
  79                           /*
  80                            * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
  81                            * it REC_MODE_L.
  82                            */
  83                           "RECOVERY_SW_L",
  84                           "OTP_OUT",
  85                           "HOST1_PWR_EN",
  86                           "USBOTG_PWREN_H",
  87                           "AP_WARM_RESET_H",
  88                           "nFALUT2",
  89                           "I2C0_SDA_PMIC",
  90
  91                           "I2C0_SCL_PMIC",
  92                           "SUSPEND_L",
  93                           "USB_INT";
  94 };
  95
  96 &gpio2 {
  97         gpio-line-names = "CONFIG0",
  98                           "CONFIG1",
  99                           "CONFIG2",
 100                           "",
 101                           "",
 102                           "",
 103                           "",
 104                           "CONFIG3",
 105
 106                           "",
 107                           "EMMC_RST_L",
 108                           "",
 109                           "",
 110                           "BL_PWR_EN",
 111                           "AVDD_1V8_DISP_EN";
 112 };
 113
 114 &gpio3 {
 115         gpio-line-names = "FLASH0_D0",
 116                           "FLASH0_D1",
 117                           "FLASH0_D2",
 118                           "FLASH0_D3",
 119                           "FLASH0_D4",
 120                           "FLASH0_D5",
 121                           "FLASH0_D6",
 122                           "FLASH0_D7",
 123
 124                           "",
 125                           "",
 126                           "",
 127                           "",
 128                           "",
 129                           "",
 130                           "",
 131                           "",
 132
 133                           "FLASH0_CS2/EMMC_CMD",
 134                           "",
 135                           "FLASH0_DQS/EMMC_CLKO";
 136 };
 137
 138 &gpio4 {
 139         gpio-line-names = "",
 140                           "",
 141                           "",
 142                           "",
 143                           "",
 144                           "",
 145                           "",
 146                           "",
 147
 148                           "",
 149                           "",
 150                           "",
 151                           "",
 152                           "",
 153                           "",
 154                           "",
 155                           "",
 156
 157                           "UART0_RXD",
 158                           "UART0_TXD",
 159                           "UART0_CTS",
 160                           "UART0_RTS",
 161                           "SDIO0_D0",
 162                           "SDIO0_D1",
 163                           "SDIO0_D2",
 164                           "SDIO0_D3",
 165
 166                           "SDIO0_CMD",
 167                           "SDIO0_CLK",
 168                           "BT_DEV_WAKE",        /* Maybe missing from mighty? */
 169                           "",
 170                           "WIFI_ENABLE_H",
 171                           "BT_ENABLE_L",
 172                           "WIFI_HOST_WAKE",
 173                           "BT_HOST_WAKE";
 174 };
 175
 176 &gpio5 {
 177         gpio-line-names = "",
 178                           "",
 179                           "",
 180                           "",
 181                           "",
 182                           "",
 183                           "",
 184                           "",
 185
 186                           "",
 187                           "",
 188                           "",
 189                           "",
 190                           "SPI0_CLK",
 191                           "SPI0_CS0",
 192                           "SPI0_TXD",
 193                           "SPI0_RXD",
 194
 195                           "",
 196                           "",
 197                           "",
 198                           "VCC50_HDMI_EN";
 199 };
 200
 201 &gpio6 {
 202         gpio-line-names = "I2S0_SCLK",
 203                           "I2S0_LRCK_RX",
 204                           "I2S0_LRCK_TX",
 205                           "I2S0_SDI",
 206                           "I2S0_SDO0",
 207                           "HP_DET_H",
 208                           "ALS_INT",
 209                           "INT_CODEC",
 210
 211                           "I2S0_CLK",
 212                           "I2C2_SDA",
 213                           "I2C2_SCL",
 214                           "MICDET",
 215                           "",
 216                           "",
 217                           "",
 218                           "",
 219
 220                           "SDMMC_D0",
 221                           "SDMMC_D1",
 222                           "SDMMC_D2",
 223                           "SDMMC_D3",
 224                           "SDMMC_CLK",
 225                           "SDMMC_CMD";
 226 };
 227
 228 &gpio7 {
 229         gpio-line-names = "LCDC_BL",
 230                           "PWM_LOG",
 231                           "BL_EN",
 232                           "TRACKPAD_INT",
 233                           "TPM_INT_H",
 234                           "SDMMC_DET_L",
 235                           /*
 236                            * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
 237                            * it FW_WP_AP.
 238                            */
 239                           "AP_FLASH_WP_L",
 240                           "EC_INT",
 241
 242                           "CPU_NMI",
 243                           "DVSOK",
 244                           "SDMMC_WP",           /* mighty only */
 245                           "EDP_HPD",
 246                           "DVS1",
 247                           "nFALUT1",            /* nFAULT1 on jaq */
 248                           "LCD_EN",
 249                           "DVS2",
 250
 251                           "VCC5V_GOOD_H",
 252                           "I2C4_SDA_TP",
 253                           "I2C4_SCL_TP",
 254                           "I2C5_SDA_HDMI",
 255                           "I2C5_SCL_HDMI",
 256                           "5V_DRV",
 257                           "UART2_RXD",
 258                           "UART2_TXD";
 259 };
 260
 261 &gpio8 {
 262         gpio-line-names = "RAM_ID0",
 263                           "RAM_ID1",
 264                           "RAM_ID2",
 265                           "RAM_ID3",
 266                           "I2C1_SDA_TPM",
 267                           "I2C1_SCL_TPM",
 268                           "SPI2_CLK",
 269                           "SPI2_CS0",
 270
 271                           "SPI2_RXD",
 272                           "SPI2_TXD";
 273 };
 274
 275 &pinctrl {
 276         pinctrl-names = "default", "sleep";
 277         pinctrl-0 = <
 278                 /* Common for sleep and wake, but no owners */
 279                 &ddr0_retention
 280                 &ddrio_pwroff
 281                 &global_pwroff
 282
 283                 /* Wake only */
 284                 &suspend_l_wake
 285                 &bt_dev_wake_awake
 286         >;
 287         pinctrl-1 = <
 288                 /* Common for sleep and wake, but no owners */
 289                 &ddr0_retention
 290                 &ddrio_pwroff
 291                 &global_pwroff
 292
 293                 /* Sleep only */
 294                 &suspend_l_sleep
 295                 &bt_dev_wake_sleep
 296         >;
 297
 298         buck-5v {
 299                 drv_5v: drv-5v {
 300                         rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 301                 };
 302         };
 303
 304         hdmi {
 305                 vcc50_hdmi_en: vcc50-hdmi-en {
 306                         rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
 307                 };
 308         };
 309
 310         pmic {
 311                 dvs_1: dvs-1 {
 312                         rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
 313                 };
 314
 315                 dvs_2: dvs-2 {
 316                         rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
 317                 };
 318         };
 319 };