Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
[linux-2.6-microblaze.git] / arch / arm / boot / dts / rk322x.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9
10 / {
11         #address-cells = <1>;
12         #size-cells = <1>;
13
14         interrupt-parent = <&gic>;
15
16         aliases {
17                 serial0 = &uart0;
18                 serial1 = &uart1;
19                 serial2 = &uart2;
20                 spi0 = &spi0;
21         };
22
23         cpus {
24                 #address-cells = <1>;
25                 #size-cells = <0>;
26
27                 cpu0: cpu@f00 {
28                         device_type = "cpu";
29                         compatible = "arm,cortex-a7";
30                         reg = <0xf00>;
31                         resets = <&cru SRST_CORE0>;
32                         operating-points-v2 = <&cpu0_opp_table>;
33                         #cooling-cells = <2>; /* min followed by max */
34                         clock-latency = <40000>;
35                         clocks = <&cru ARMCLK>;
36                         enable-method = "psci";
37                 };
38
39                 cpu1: cpu@f01 {
40                         device_type = "cpu";
41                         compatible = "arm,cortex-a7";
42                         reg = <0xf01>;
43                         resets = <&cru SRST_CORE1>;
44                         operating-points-v2 = <&cpu0_opp_table>;
45                         #cooling-cells = <2>; /* min followed by max */
46                         enable-method = "psci";
47                 };
48
49                 cpu2: cpu@f02 {
50                         device_type = "cpu";
51                         compatible = "arm,cortex-a7";
52                         reg = <0xf02>;
53                         resets = <&cru SRST_CORE2>;
54                         operating-points-v2 = <&cpu0_opp_table>;
55                         #cooling-cells = <2>; /* min followed by max */
56                         enable-method = "psci";
57                 };
58
59                 cpu3: cpu@f03 {
60                         device_type = "cpu";
61                         compatible = "arm,cortex-a7";
62                         reg = <0xf03>;
63                         resets = <&cru SRST_CORE3>;
64                         operating-points-v2 = <&cpu0_opp_table>;
65                         #cooling-cells = <2>; /* min followed by max */
66                         enable-method = "psci";
67                 };
68         };
69
70         cpu0_opp_table: opp_table0 {
71                 compatible = "operating-points-v2";
72                 opp-shared;
73
74                 opp-408000000 {
75                         opp-hz = /bits/ 64 <408000000>;
76                         opp-microvolt = <950000>;
77                         clock-latency-ns = <40000>;
78                         opp-suspend;
79                 };
80                 opp-600000000 {
81                         opp-hz = /bits/ 64 <600000000>;
82                         opp-microvolt = <975000>;
83                 };
84                 opp-816000000 {
85                         opp-hz = /bits/ 64 <816000000>;
86                         opp-microvolt = <1000000>;
87                 };
88                 opp-1008000000 {
89                         opp-hz = /bits/ 64 <1008000000>;
90                         opp-microvolt = <1175000>;
91                 };
92                 opp-1200000000 {
93                         opp-hz = /bits/ 64 <1200000000>;
94                         opp-microvolt = <1275000>;
95                 };
96         };
97
98         amba: bus {
99                 compatible = "simple-bus";
100                 #address-cells = <1>;
101                 #size-cells = <1>;
102                 ranges;
103
104                 pdma: pdma@110f0000 {
105                         compatible = "arm,pl330", "arm,primecell";
106                         reg = <0x110f0000 0x4000>;
107                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109                         #dma-cells = <1>;
110                         arm,pl330-periph-burst;
111                         clocks = <&cru ACLK_DMAC>;
112                         clock-names = "apb_pclk";
113                 };
114         };
115
116         arm-pmu {
117                 compatible = "arm,cortex-a7-pmu";
118                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
119                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
120                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
121                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
122                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
123         };
124
125         psci {
126                 compatible = "arm,psci-1.0", "arm,psci-0.2";
127                 method = "smc";
128         };
129
130         timer {
131                 compatible = "arm,armv7-timer";
132                 arm,cpu-registers-not-fw-configured;
133                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
136                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
137                 clock-frequency = <24000000>;
138         };
139
140         xin24m: oscillator {
141                 compatible = "fixed-clock";
142                 clock-frequency = <24000000>;
143                 clock-output-names = "xin24m";
144                 #clock-cells = <0>;
145         };
146
147         display_subsystem: display-subsystem {
148                 compatible = "rockchip,display-subsystem";
149                 ports = <&vop_out>;
150         };
151
152         i2s1: i2s1@100b0000 {
153                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
154                 reg = <0x100b0000 0x4000>;
155                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
156                 clock-names = "i2s_clk", "i2s_hclk";
157                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
158                 dmas = <&pdma 14>, <&pdma 15>;
159                 dma-names = "tx", "rx";
160                 pinctrl-names = "default";
161                 pinctrl-0 = <&i2s1_bus>;
162                 status = "disabled";
163         };
164
165         i2s0: i2s0@100c0000 {
166                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
167                 reg = <0x100c0000 0x4000>;
168                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
169                 clock-names = "i2s_clk", "i2s_hclk";
170                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
171                 dmas = <&pdma 11>, <&pdma 12>;
172                 dma-names = "tx", "rx";
173                 status = "disabled";
174         };
175
176         spdif: spdif@100d0000 {
177                 compatible = "rockchip,rk3228-spdif";
178                 reg = <0x100d0000 0x1000>;
179                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
180                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
181                 clock-names = "mclk", "hclk";
182                 dmas = <&pdma 10>;
183                 dma-names = "tx";
184                 pinctrl-names = "default";
185                 pinctrl-0 = <&spdif_tx>;
186                 status = "disabled";
187         };
188
189         i2s2: i2s2@100e0000 {
190                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
191                 reg = <0x100e0000 0x4000>;
192                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
193                 clock-names = "i2s_clk", "i2s_hclk";
194                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195                 dmas = <&pdma 0>, <&pdma 1>;
196                 dma-names = "tx", "rx";
197                 status = "disabled";
198         };
199
200         grf: syscon@11000000 {
201                 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
202                 reg = <0x11000000 0x1000>;
203                 #address-cells = <1>;
204                 #size-cells = <1>;
205
206                 io_domains: io-domains {
207                         compatible = "rockchip,rk3228-io-voltage-domain";
208                         status = "disabled";
209                 };
210
211                 u2phy0: usb2-phy@760 {
212                         compatible = "rockchip,rk3228-usb2phy";
213                         reg = <0x0760 0x0c>;
214                         clocks = <&cru SCLK_OTGPHY0>;
215                         clock-names = "phyclk";
216                         clock-output-names = "usb480m_phy0";
217                         #clock-cells = <0>;
218                         status = "disabled";
219
220                         u2phy0_otg: otg-port {
221                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
222                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
223                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
224                                 interrupt-names = "otg-bvalid", "otg-id",
225                                                   "linestate";
226                                 #phy-cells = <0>;
227                                 status = "disabled";
228                         };
229
230                         u2phy0_host: host-port {
231                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
232                                 interrupt-names = "linestate";
233                                 #phy-cells = <0>;
234                                 status = "disabled";
235                         };
236                 };
237
238                 u2phy1: usb2-phy@800 {
239                         compatible = "rockchip,rk3228-usb2phy";
240                         reg = <0x0800 0x0c>;
241                         clocks = <&cru SCLK_OTGPHY1>;
242                         clock-names = "phyclk";
243                         clock-output-names = "usb480m_phy1";
244                         #clock-cells = <0>;
245                         status = "disabled";
246
247                         u2phy1_otg: otg-port {
248                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
249                                 interrupt-names = "linestate";
250                                 #phy-cells = <0>;
251                                 status = "disabled";
252                         };
253
254                         u2phy1_host: host-port {
255                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
256                                 interrupt-names = "linestate";
257                                 #phy-cells = <0>;
258                                 status = "disabled";
259                         };
260                 };
261         };
262
263         uart0: serial@11010000 {
264                 compatible = "snps,dw-apb-uart";
265                 reg = <0x11010000 0x100>;
266                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
267                 clock-frequency = <24000000>;
268                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
269                 clock-names = "baudclk", "apb_pclk";
270                 pinctrl-names = "default";
271                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
272                 reg-shift = <2>;
273                 reg-io-width = <4>;
274                 status = "disabled";
275         };
276
277         uart1: serial@11020000 {
278                 compatible = "snps,dw-apb-uart";
279                 reg = <0x11020000 0x100>;
280                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
281                 clock-frequency = <24000000>;
282                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
283                 clock-names = "baudclk", "apb_pclk";
284                 pinctrl-names = "default";
285                 pinctrl-0 = <&uart1_xfer>;
286                 reg-shift = <2>;
287                 reg-io-width = <4>;
288                 status = "disabled";
289         };
290
291         uart2: serial@11030000 {
292                 compatible = "snps,dw-apb-uart";
293                 reg = <0x11030000 0x100>;
294                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
295                 clock-frequency = <24000000>;
296                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
297                 clock-names = "baudclk", "apb_pclk";
298                 pinctrl-names = "default";
299                 pinctrl-0 = <&uart2_xfer>;
300                 reg-shift = <2>;
301                 reg-io-width = <4>;
302                 status = "disabled";
303         };
304
305         efuse: efuse@11040000 {
306                 compatible = "rockchip,rk3228-efuse";
307                 reg = <0x11040000 0x20>;
308                 clocks = <&cru PCLK_EFUSE_256>;
309                 clock-names = "pclk_efuse";
310                 #address-cells = <1>;
311                 #size-cells = <1>;
312
313                 /* Data cells */
314                 efuse_id: id@7 {
315                         reg = <0x7 0x10>;
316                 };
317                 cpu_leakage: cpu_leakage@17 {
318                         reg = <0x17 0x1>;
319                 };
320         };
321
322         i2c0: i2c@11050000 {
323                 compatible = "rockchip,rk3228-i2c";
324                 reg = <0x11050000 0x1000>;
325                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
326                 #address-cells = <1>;
327                 #size-cells = <0>;
328                 clock-names = "i2c";
329                 clocks = <&cru PCLK_I2C0>;
330                 pinctrl-names = "default";
331                 pinctrl-0 = <&i2c0_xfer>;
332                 status = "disabled";
333         };
334
335         i2c1: i2c@11060000 {
336                 compatible = "rockchip,rk3228-i2c";
337                 reg = <0x11060000 0x1000>;
338                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
339                 #address-cells = <1>;
340                 #size-cells = <0>;
341                 clock-names = "i2c";
342                 clocks = <&cru PCLK_I2C1>;
343                 pinctrl-names = "default";
344                 pinctrl-0 = <&i2c1_xfer>;
345                 status = "disabled";
346         };
347
348         i2c2: i2c@11070000 {
349                 compatible = "rockchip,rk3228-i2c";
350                 reg = <0x11070000 0x1000>;
351                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
352                 #address-cells = <1>;
353                 #size-cells = <0>;
354                 clock-names = "i2c";
355                 clocks = <&cru PCLK_I2C2>;
356                 pinctrl-names = "default";
357                 pinctrl-0 = <&i2c2_xfer>;
358                 status = "disabled";
359         };
360
361         i2c3: i2c@11080000 {
362                 compatible = "rockchip,rk3228-i2c";
363                 reg = <0x11080000 0x1000>;
364                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
365                 #address-cells = <1>;
366                 #size-cells = <0>;
367                 clock-names = "i2c";
368                 clocks = <&cru PCLK_I2C3>;
369                 pinctrl-names = "default";
370                 pinctrl-0 = <&i2c3_xfer>;
371                 status = "disabled";
372         };
373
374         spi0: spi@11090000 {
375                 compatible = "rockchip,rk3228-spi";
376                 reg = <0x11090000 0x1000>;
377                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
378                 #address-cells = <1>;
379                 #size-cells = <0>;
380                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
381                 clock-names = "spiclk", "apb_pclk";
382                 pinctrl-names = "default";
383                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
384                 status = "disabled";
385         };
386
387         wdt: watchdog@110a0000 {
388                 compatible = "snps,dw-wdt";
389                 reg = <0x110a0000 0x100>;
390                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
391                 clocks = <&cru PCLK_CPU>;
392                 status = "disabled";
393         };
394
395         pwm0: pwm@110b0000 {
396                 compatible = "rockchip,rk3288-pwm";
397                 reg = <0x110b0000 0x10>;
398                 #pwm-cells = <3>;
399                 clocks = <&cru PCLK_PWM>;
400                 clock-names = "pwm";
401                 pinctrl-names = "default";
402                 pinctrl-0 = <&pwm0_pin>;
403                 status = "disabled";
404         };
405
406         pwm1: pwm@110b0010 {
407                 compatible = "rockchip,rk3288-pwm";
408                 reg = <0x110b0010 0x10>;
409                 #pwm-cells = <3>;
410                 clocks = <&cru PCLK_PWM>;
411                 clock-names = "pwm";
412                 pinctrl-names = "default";
413                 pinctrl-0 = <&pwm1_pin>;
414                 status = "disabled";
415         };
416
417         pwm2: pwm@110b0020 {
418                 compatible = "rockchip,rk3288-pwm";
419                 reg = <0x110b0020 0x10>;
420                 #pwm-cells = <3>;
421                 clocks = <&cru PCLK_PWM>;
422                 clock-names = "pwm";
423                 pinctrl-names = "default";
424                 pinctrl-0 = <&pwm2_pin>;
425                 status = "disabled";
426         };
427
428         pwm3: pwm@110b0030 {
429                 compatible = "rockchip,rk3288-pwm";
430                 reg = <0x110b0030 0x10>;
431                 #pwm-cells = <2>;
432                 clocks = <&cru PCLK_PWM>;
433                 clock-names = "pwm";
434                 pinctrl-names = "default";
435                 pinctrl-0 = <&pwm3_pin>;
436                 status = "disabled";
437         };
438
439         timer: timer@110c0000 {
440                 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
441                 reg = <0x110c0000 0x20>;
442                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
443                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
444                 clock-names = "timer", "pclk";
445         };
446
447         cru: clock-controller@110e0000 {
448                 compatible = "rockchip,rk3228-cru";
449                 reg = <0x110e0000 0x1000>;
450                 rockchip,grf = <&grf>;
451                 #clock-cells = <1>;
452                 #reset-cells = <1>;
453                 assigned-clocks =
454                         <&cru PLL_GPLL>, <&cru ARMCLK>,
455                         <&cru PLL_CPLL>, <&cru ACLK_PERI>,
456                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
457                         <&cru ACLK_CPU>, <&cru HCLK_CPU>,
458                         <&cru PCLK_CPU>;
459                 assigned-clock-rates =
460                         <594000000>, <816000000>,
461                         <500000000>, <150000000>,
462                         <150000000>, <75000000>,
463                         <150000000>, <150000000>,
464                         <75000000>;
465         };
466
467         thermal-zones {
468                 cpu_thermal: cpu-thermal {
469                         polling-delay-passive = <100>; /* milliseconds */
470                         polling-delay = <5000>; /* milliseconds */
471
472                         thermal-sensors = <&tsadc 0>;
473
474                         trips {
475                                 cpu_alert0: cpu_alert0 {
476                                         temperature = <70000>; /* millicelsius */
477                                         hysteresis = <2000>; /* millicelsius */
478                                         type = "passive";
479                                 };
480                                 cpu_alert1: cpu_alert1 {
481                                         temperature = <75000>; /* millicelsius */
482                                         hysteresis = <2000>; /* millicelsius */
483                                         type = "passive";
484                                 };
485                                 cpu_crit: cpu_crit {
486                                         temperature = <90000>; /* millicelsius */
487                                         hysteresis = <2000>; /* millicelsius */
488                                         type = "critical";
489                                 };
490                         };
491
492                         cooling-maps {
493                                 map0 {
494                                         trip = <&cpu_alert0>;
495                                         cooling-device =
496                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
497                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
498                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
499                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
500                                 };
501                                 map1 {
502                                         trip = <&cpu_alert1>;
503                                         cooling-device =
504                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
505                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
506                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
507                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
508                                 };
509                         };
510                 };
511         };
512
513         tsadc: tsadc@11150000 {
514                 compatible = "rockchip,rk3228-tsadc";
515                 reg = <0x11150000 0x100>;
516                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
517                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
518                 clock-names = "tsadc", "apb_pclk";
519                 assigned-clocks = <&cru SCLK_TSADC>;
520                 assigned-clock-rates = <32768>;
521                 resets = <&cru SRST_TSADC>;
522                 reset-names = "tsadc-apb";
523                 pinctrl-names = "init", "default", "sleep";
524                 pinctrl-0 = <&otp_pin>;
525                 pinctrl-1 = <&otp_out>;
526                 pinctrl-2 = <&otp_pin>;
527                 #thermal-sensor-cells = <0>;
528                 rockchip,hw-tshut-temp = <95000>;
529                 status = "disabled";
530         };
531
532         hdmi_phy: hdmi-phy@12030000 {
533                 compatible = "rockchip,rk3228-hdmi-phy";
534                 reg = <0x12030000 0x10000>;
535                 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
536                 clock-names = "sysclk", "refoclk", "refpclk";
537                 #clock-cells = <0>;
538                 clock-output-names = "hdmiphy_phy";
539                 #phy-cells = <0>;
540                 status = "disabled";
541         };
542
543         gpu: gpu@20000000 {
544                 compatible = "rockchip,rk3228-mali", "arm,mali-400";
545                 reg = <0x20000000 0x10000>;
546                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
547                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
548                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
549                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
550                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
551                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
552                 interrupt-names = "gp",
553                                   "gpmmu",
554                                   "pp0",
555                                   "ppmmu0",
556                                   "pp1",
557                                   "ppmmu1";
558                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
559                 clock-names = "bus", "core";
560                 resets = <&cru SRST_GPU_A>;
561                 status = "disabled";
562         };
563
564         vpu_mmu: iommu@20020800 {
565                 compatible = "rockchip,iommu";
566                 reg = <0x20020800 0x100>;
567                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
568                 interrupt-names = "vpu_mmu";
569                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
570                 clock-names = "aclk", "iface";
571                 iommu-cells = <0>;
572                 status = "disabled";
573         };
574
575         vdec_mmu: iommu@20030480 {
576                 compatible = "rockchip,iommu";
577                 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
578                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
579                 interrupt-names = "vdec_mmu";
580                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
581                 clock-names = "aclk", "iface";
582                 iommu-cells = <0>;
583                 status = "disabled";
584         };
585
586         vop: vop@20050000 {
587                 compatible = "rockchip,rk3228-vop";
588                 reg = <0x20050000 0x1ffc>;
589                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
590                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
591                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
592                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
593                 reset-names = "axi", "ahb", "dclk";
594                 iommus = <&vop_mmu>;
595                 status = "disabled";
596
597                 vop_out: port {
598                         #address-cells = <1>;
599                         #size-cells = <0>;
600
601                         vop_out_hdmi: endpoint@0 {
602                                 reg = <0>;
603                                 remote-endpoint = <&hdmi_in_vop>;
604                         };
605                 };
606         };
607
608         vop_mmu: iommu@20053f00 {
609                 compatible = "rockchip,iommu";
610                 reg = <0x20053f00 0x100>;
611                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
612                 interrupt-names = "vop_mmu";
613                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
614                 clock-names = "aclk", "iface";
615                 #iommu-cells = <0>;
616                 status = "disabled";
617         };
618
619         rga: rga@20060000 {
620                 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
621                 reg = <0x20060000 0x1000>;
622                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
623                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
624                 clock-names = "aclk", "hclk", "sclk";
625                 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
626                 reset-names = "core", "axi", "ahb";
627         };
628
629         iep_mmu: iommu@20070800 {
630                 compatible = "rockchip,iommu";
631                 reg = <0x20070800 0x100>;
632                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
633                 interrupt-names = "iep_mmu";
634                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
635                 clock-names = "aclk", "iface";
636                 iommu-cells = <0>;
637                 status = "disabled";
638         };
639
640         hdmi: hdmi@200a0000 {
641                 compatible = "rockchip,rk3228-dw-hdmi";
642                 reg = <0x200a0000 0x20000>;
643                 reg-io-width = <4>;
644                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
645                 assigned-clocks = <&cru SCLK_HDMI_PHY>;
646                 assigned-clock-parents = <&hdmi_phy>;
647                 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
648                 clock-names = "isfr", "iahb", "cec";
649                 pinctrl-names = "default";
650                 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
651                 resets = <&cru SRST_HDMI_P>;
652                 reset-names = "hdmi";
653                 phys = <&hdmi_phy>;
654                 phy-names = "hdmi";
655                 rockchip,grf = <&grf>;
656                 status = "disabled";
657
658                 ports {
659                         hdmi_in: port {
660                                 #address-cells = <1>;
661                                 #size-cells = <0>;
662                                 hdmi_in_vop: endpoint@0 {
663                                         reg = <0>;
664                                         remote-endpoint = <&vop_out_hdmi>;
665                                 };
666                         };
667                 };
668         };
669
670         sdmmc: mmc@30000000 {
671                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
672                 reg = <0x30000000 0x4000>;
673                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
674                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
675                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
676                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
677                 fifo-depth = <0x100>;
678                 pinctrl-names = "default";
679                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
680                 status = "disabled";
681         };
682
683         sdio: mmc@30010000 {
684                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
685                 reg = <0x30010000 0x4000>;
686                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
687                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
688                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
689                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
690                 fifo-depth = <0x100>;
691                 pinctrl-names = "default";
692                 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
693                 status = "disabled";
694         };
695
696         emmc: mmc@30020000 {
697                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
698                 reg = <0x30020000 0x4000>;
699                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
700                 clock-frequency = <37500000>;
701                 max-frequency = <37500000>;
702                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
703                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
704                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
705                 bus-width = <8>;
706                 rockchip,default-sample-phase = <158>;
707                 fifo-depth = <0x100>;
708                 pinctrl-names = "default";
709                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
710                 resets = <&cru SRST_EMMC>;
711                 reset-names = "reset";
712                 status = "disabled";
713         };
714
715         usb_otg: usb@30040000 {
716                 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
717                              "snps,dwc2";
718                 reg = <0x30040000 0x40000>;
719                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
720                 clocks = <&cru HCLK_OTG>;
721                 clock-names = "otg";
722                 dr_mode = "otg";
723                 g-np-tx-fifo-size = <16>;
724                 g-rx-fifo-size = <280>;
725                 g-tx-fifo-size = <256 128 128 64 32 16>;
726                 phys = <&u2phy0_otg>;
727                 phy-names = "usb2-phy";
728                 status = "disabled";
729         };
730
731         usb_host0_ehci: usb@30080000 {
732                 compatible = "generic-ehci";
733                 reg = <0x30080000 0x20000>;
734                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
735                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
736                 phys = <&u2phy0_host>;
737                 phy-names = "usb";
738                 status = "disabled";
739         };
740
741         usb_host0_ohci: usb@300a0000 {
742                 compatible = "generic-ohci";
743                 reg = <0x300a0000 0x20000>;
744                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
745                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
746                 phys = <&u2phy0_host>;
747                 phy-names = "usb";
748                 status = "disabled";
749         };
750
751         usb_host1_ehci: usb@300c0000 {
752                 compatible = "generic-ehci";
753                 reg = <0x300c0000 0x20000>;
754                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
755                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
756                 phys = <&u2phy1_otg>;
757                 phy-names = "usb";
758                 status = "disabled";
759         };
760
761         usb_host1_ohci: usb@300e0000 {
762                 compatible = "generic-ohci";
763                 reg = <0x300e0000 0x20000>;
764                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
765                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
766                 phys = <&u2phy1_otg>;
767                 phy-names = "usb";
768                 status = "disabled";
769         };
770
771         usb_host2_ehci: usb@30100000 {
772                 compatible = "generic-ehci";
773                 reg = <0x30100000 0x20000>;
774                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
775                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
776                 phys = <&u2phy1_host>;
777                 phy-names = "usb";
778                 status = "disabled";
779         };
780
781         usb_host2_ohci: usb@30120000 {
782                 compatible = "generic-ohci";
783                 reg = <0x30120000 0x20000>;
784                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
785                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
786                 phys = <&u2phy1_host>;
787                 phy-names = "usb";
788                 status = "disabled";
789         };
790
791         gmac: ethernet@30200000 {
792                 compatible = "rockchip,rk3228-gmac";
793                 reg = <0x30200000 0x10000>;
794                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
795                 interrupt-names = "macirq";
796                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
797                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
798                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
799                         <&cru PCLK_GMAC>;
800                 clock-names = "stmmaceth", "mac_clk_rx",
801                         "mac_clk_tx", "clk_mac_ref",
802                         "clk_mac_refout", "aclk_mac",
803                         "pclk_mac";
804                 resets = <&cru SRST_GMAC>;
805                 reset-names = "stmmaceth";
806                 rockchip,grf = <&grf>;
807                 status = "disabled";
808         };
809
810         gic: interrupt-controller@32010000 {
811                 compatible = "arm,gic-400";
812                 interrupt-controller;
813                 #interrupt-cells = <3>;
814                 #address-cells = <0>;
815
816                 reg = <0x32011000 0x1000>,
817                       <0x32012000 0x2000>,
818                       <0x32014000 0x2000>,
819                       <0x32016000 0x2000>;
820                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
821         };
822
823         pinctrl: pinctrl {
824                 compatible = "rockchip,rk3228-pinctrl";
825                 rockchip,grf = <&grf>;
826                 #address-cells = <1>;
827                 #size-cells = <1>;
828                 ranges;
829
830                 gpio0: gpio0@11110000 {
831                         compatible = "rockchip,gpio-bank";
832                         reg = <0x11110000 0x100>;
833                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
834                         clocks = <&cru PCLK_GPIO0>;
835
836                         gpio-controller;
837                         #gpio-cells = <2>;
838
839                         interrupt-controller;
840                         #interrupt-cells = <2>;
841                 };
842
843                 gpio1: gpio1@11120000 {
844                         compatible = "rockchip,gpio-bank";
845                         reg = <0x11120000 0x100>;
846                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
847                         clocks = <&cru PCLK_GPIO1>;
848
849                         gpio-controller;
850                         #gpio-cells = <2>;
851
852                         interrupt-controller;
853                         #interrupt-cells = <2>;
854                 };
855
856                 gpio2: gpio2@11130000 {
857                         compatible = "rockchip,gpio-bank";
858                         reg = <0x11130000 0x100>;
859                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
860                         clocks = <&cru PCLK_GPIO2>;
861
862                         gpio-controller;
863                         #gpio-cells = <2>;
864
865                         interrupt-controller;
866                         #interrupt-cells = <2>;
867                 };
868
869                 gpio3: gpio3@11140000 {
870                         compatible = "rockchip,gpio-bank";
871                         reg = <0x11140000 0x100>;
872                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
873                         clocks = <&cru PCLK_GPIO3>;
874
875                         gpio-controller;
876                         #gpio-cells = <2>;
877
878                         interrupt-controller;
879                         #interrupt-cells = <2>;
880                 };
881
882                 pcfg_pull_up: pcfg-pull-up {
883                         bias-pull-up;
884                 };
885
886                 pcfg_pull_down: pcfg-pull-down {
887                         bias-pull-down;
888                 };
889
890                 pcfg_pull_none: pcfg-pull-none {
891                         bias-disable;
892                 };
893
894                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
895                         drive-strength = <12>;
896                 };
897
898                 sdmmc {
899                         sdmmc_clk: sdmmc-clk {
900                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
901                         };
902
903                         sdmmc_cmd: sdmmc-cmd {
904                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
905                         };
906
907                         sdmmc_bus4: sdmmc-bus4 {
908                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
909                                                 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
910                                                 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
911                                                 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
912                         };
913                 };
914
915                 sdio {
916                         sdio_clk: sdio-clk {
917                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
918                         };
919
920                         sdio_cmd: sdio-cmd {
921                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
922                         };
923
924                         sdio_bus4: sdio-bus4 {
925                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
926                                                 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
927                                                 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
928                                                 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
929                         };
930                 };
931
932                 emmc {
933                         emmc_clk: emmc-clk {
934                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
935                         };
936
937                         emmc_cmd: emmc-cmd {
938                                 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
939                         };
940
941                         emmc_bus8: emmc-bus8 {
942                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
943                                                 <1 RK_PD1 2 &pcfg_pull_none>,
944                                                 <1 RK_PD2 2 &pcfg_pull_none>,
945                                                 <1 RK_PD3 2 &pcfg_pull_none>,
946                                                 <1 RK_PD4 2 &pcfg_pull_none>,
947                                                 <1 RK_PD5 2 &pcfg_pull_none>,
948                                                 <1 RK_PD6 2 &pcfg_pull_none>,
949                                                 <1 RK_PD7 2 &pcfg_pull_none>;
950                         };
951                 };
952
953                 gmac {
954                         rgmii_pins: rgmii-pins {
955                                 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
956                                                 <2 RK_PB4 1 &pcfg_pull_none>,
957                                                 <2 RK_PD1 1 &pcfg_pull_none>,
958                                                 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
959                                                 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
960                                                 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
961                                                 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
962                                                 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
963                                                 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
964                                                 <2 RK_PC1 1 &pcfg_pull_none>,
965                                                 <2 RK_PC0 1 &pcfg_pull_none>,
966                                                 <2 RK_PC5 2 &pcfg_pull_none>,
967                                                 <2 RK_PC4 2 &pcfg_pull_none>,
968                                                 <2 RK_PB3 1 &pcfg_pull_none>,
969                                                 <2 RK_PB0 1 &pcfg_pull_none>;
970                         };
971
972                         rmii_pins: rmii-pins {
973                                 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
974                                                 <2 RK_PB4 1 &pcfg_pull_none>,
975                                                 <2 RK_PD1 1 &pcfg_pull_none>,
976                                                 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
977                                                 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
978                                                 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
979                                                 <2 RK_PC1 1 &pcfg_pull_none>,
980                                                 <2 RK_PC0 1 &pcfg_pull_none>,
981                                                 <2 RK_PB0 1 &pcfg_pull_none>,
982                                                 <2 RK_PB7 1 &pcfg_pull_none>;
983                         };
984
985                         phy_pins: phy-pins {
986                                 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
987                                                 <2 RK_PB0 2 &pcfg_pull_none>;
988                         };
989                 };
990
991                 hdmi {
992                         hdmi_hpd: hdmi-hpd {
993                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
994                         };
995
996                         hdmii2c_xfer: hdmii2c-xfer {
997                                 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
998                                                 <0 RK_PA7 2 &pcfg_pull_none>;
999                         };
1000
1001                         hdmi_cec: hdmi-cec {
1002                                 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1003                         };
1004                 };
1005
1006                 i2c0 {
1007                         i2c0_xfer: i2c0-xfer {
1008                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1009                                                 <0 RK_PA1 1 &pcfg_pull_none>;
1010                         };
1011                 };
1012
1013                 i2c1 {
1014                         i2c1_xfer: i2c1-xfer {
1015                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1016                                                 <0 RK_PA3 1 &pcfg_pull_none>;
1017                         };
1018                 };
1019
1020                 i2c2 {
1021                         i2c2_xfer: i2c2-xfer {
1022                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1023                                                 <2 RK_PC5 1 &pcfg_pull_none>;
1024                         };
1025                 };
1026
1027                 i2c3 {
1028                         i2c3_xfer: i2c3-xfer {
1029                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1030                                                 <0 RK_PA7 1 &pcfg_pull_none>;
1031                         };
1032                 };
1033
1034                 spi0 {
1035                         spi0_clk: spi0-clk {
1036                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1037                         };
1038                         spi0_cs0: spi0-cs0 {
1039                                 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1040                         };
1041                         spi0_tx: spi0-tx {
1042                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1043                         };
1044                         spi0_rx: spi0-rx {
1045                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1046                         };
1047                         spi0_cs1: spi0-cs1 {
1048                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1049                         };
1050                 };
1051
1052                 spi1 {
1053                         spi1_clk: spi1-clk {
1054                                 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1055                         };
1056                         spi1_cs0: spi1-cs0 {
1057                                 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1058                         };
1059                         spi1_rx: spi1-rx {
1060                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1061                         };
1062                         spi1_tx: spi1-tx {
1063                                 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1064                         };
1065                         spi1_cs1: spi1-cs1 {
1066                                 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1067                         };
1068                 };
1069
1070                 i2s1 {
1071                         i2s1_bus: i2s1-bus {
1072                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1073                                                 <0 RK_PB1 1 &pcfg_pull_none>,
1074                                                 <0 RK_PB3 1 &pcfg_pull_none>,
1075                                                 <0 RK_PB4 1 &pcfg_pull_none>,
1076                                                 <0 RK_PB5 1 &pcfg_pull_none>,
1077                                                 <0 RK_PB6 1 &pcfg_pull_none>,
1078                                                 <1 RK_PA2 2 &pcfg_pull_none>,
1079                                                 <1 RK_PA4 2 &pcfg_pull_none>,
1080                                                 <1 RK_PA5 2 &pcfg_pull_none>;
1081                         };
1082                 };
1083
1084                 pwm0 {
1085                         pwm0_pin: pwm0-pin {
1086                                 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1087                         };
1088                 };
1089
1090                 pwm1 {
1091                         pwm1_pin: pwm1-pin {
1092                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 pwm2 {
1097                         pwm2_pin: pwm2-pin {
1098                                 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1099                         };
1100                 };
1101
1102                 pwm3 {
1103                         pwm3_pin: pwm3-pin {
1104                                 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1105                         };
1106                 };
1107
1108                 spdif {
1109                         spdif_tx: spdif-tx {
1110                                 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1111                         };
1112                 };
1113
1114                 tsadc {
1115                         otp_pin: otp-pin {
1116                                 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1117                         };
1118
1119                         otp_out: otp-out {
1120                                 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 uart0 {
1125                         uart0_xfer: uart0-xfer {
1126                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1127                                                 <2 RK_PD3 1 &pcfg_pull_none>;
1128                         };
1129
1130                         uart0_cts: uart0-cts {
1131                                 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1132                         };
1133
1134                         uart0_rts: uart0-rts {
1135                                 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 uart1 {
1140                         uart1_xfer: uart1-xfer {
1141                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1142                                                 <1 RK_PB2 1 &pcfg_pull_none>;
1143                         };
1144
1145                         uart1_cts: uart1-cts {
1146                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1147                         };
1148
1149                         uart1_rts: uart1-rts {
1150                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1151                         };
1152                 };
1153
1154                 uart2 {
1155                         uart2_xfer: uart2-xfer {
1156                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1157                                                 <1 RK_PC3 2 &pcfg_pull_none>;
1158                         };
1159
1160                         uart21_xfer: uart21-xfer {
1161                                 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1162                                                 <1 RK_PB1 2 &pcfg_pull_none>;
1163                         };
1164
1165                         uart2_cts: uart2-cts {
1166                                 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1167                         };
1168
1169                         uart2_rts: uart2-rts {
1170                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1171                         };
1172                 };
1173         };
1174 };