1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
15 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a7";
32 resets = <&cru SRST_CORE0>;
33 operating-points-v2 = <&cpu0_opp_table>;
34 #cooling-cells = <2>; /* min followed by max */
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 enable-method = "psci";
42 compatible = "arm,cortex-a7";
44 resets = <&cru SRST_CORE1>;
45 operating-points-v2 = <&cpu0_opp_table>;
46 #cooling-cells = <2>; /* min followed by max */
47 enable-method = "psci";
52 compatible = "arm,cortex-a7";
54 resets = <&cru SRST_CORE2>;
55 operating-points-v2 = <&cpu0_opp_table>;
56 #cooling-cells = <2>; /* min followed by max */
57 enable-method = "psci";
62 compatible = "arm,cortex-a7";
64 resets = <&cru SRST_CORE3>;
65 operating-points-v2 = <&cpu0_opp_table>;
66 #cooling-cells = <2>; /* min followed by max */
67 enable-method = "psci";
71 cpu0_opp_table: opp-table-0 {
72 compatible = "operating-points-v2";
76 opp-hz = /bits/ 64 <408000000>;
77 opp-microvolt = <950000>;
78 clock-latency-ns = <40000>;
82 opp-hz = /bits/ 64 <600000000>;
83 opp-microvolt = <975000>;
86 opp-hz = /bits/ 64 <816000000>;
87 opp-microvolt = <1000000>;
90 opp-hz = /bits/ 64 <1008000000>;
91 opp-microvolt = <1175000>;
94 opp-hz = /bits/ 64 <1200000000>;
95 opp-microvolt = <1275000>;
100 compatible = "arm,cortex-a7-pmu";
101 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
114 compatible = "arm,armv7-timer";
115 arm,cpu-registers-not-fw-configured;
116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
120 clock-frequency = <24000000>;
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "xin24m";
130 display_subsystem: display-subsystem {
131 compatible = "rockchip,display-subsystem";
135 i2s1: i2s1@100b0000 {
136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
137 reg = <0x100b0000 0x4000>;
138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
139 clock-names = "i2s_clk", "i2s_hclk";
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
141 dmas = <&pdma 14>, <&pdma 15>;
142 dma-names = "tx", "rx";
143 pinctrl-names = "default";
144 pinctrl-0 = <&i2s1_bus>;
148 i2s0: i2s0@100c0000 {
149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
150 reg = <0x100c0000 0x4000>;
151 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
152 clock-names = "i2s_clk", "i2s_hclk";
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
154 dmas = <&pdma 11>, <&pdma 12>;
155 dma-names = "tx", "rx";
159 spdif: spdif@100d0000 {
160 compatible = "rockchip,rk3228-spdif";
161 reg = <0x100d0000 0x1000>;
162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
164 clock-names = "mclk", "hclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&spdif_tx>;
172 i2s2: i2s2@100e0000 {
173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
174 reg = <0x100e0000 0x4000>;
175 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
176 clock-names = "i2s_clk", "i2s_hclk";
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
178 dmas = <&pdma 0>, <&pdma 1>;
179 dma-names = "tx", "rx";
183 grf: syscon@11000000 {
184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
185 reg = <0x11000000 0x1000>;
186 #address-cells = <1>;
189 io_domains: io-domains {
190 compatible = "rockchip,rk3228-io-voltage-domain";
194 power: power-controller {
195 compatible = "rockchip,rk3228-power-controller";
196 #power-domain-cells = <1>;
197 #address-cells = <1>;
200 power-domain@RK3228_PD_VIO {
201 reg = <RK3228_PD_VIO>;
202 clocks = <&cru ACLK_HDCP>,
209 pm_qos = <&qos_hdcp>,
213 #power-domain-cells = <0>;
216 power-domain@RK3228_PD_VOP {
217 reg = <RK3228_PD_VOP>;
218 clocks =<&cru ACLK_VOP>,
222 #power-domain-cells = <0>;
225 power-domain@RK3228_PD_VPU {
226 reg = <RK3228_PD_VPU>;
227 clocks = <&cru ACLK_VPU>,
230 #power-domain-cells = <0>;
233 power-domain@RK3228_PD_RKVDEC {
234 reg = <RK3228_PD_RKVDEC>;
235 clocks = <&cru ACLK_RKVDEC>,
237 <&cru SCLK_VDEC_CABAC>,
238 <&cru SCLK_VDEC_CORE>;
239 pm_qos = <&qos_rkvdec_r>,
241 #power-domain-cells = <0>;
244 power-domain@RK3228_PD_GPU {
245 reg = <RK3228_PD_GPU>;
246 clocks = <&cru ACLK_GPU>;
248 #power-domain-cells = <0>;
252 u2phy0: usb2phy@760 {
253 compatible = "rockchip,rk3228-usb2phy";
255 clocks = <&cru SCLK_OTGPHY0>;
256 clock-names = "phyclk";
257 clock-output-names = "usb480m_phy0";
261 u2phy0_otg: otg-port {
262 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-names = "otg-bvalid", "otg-id",
271 u2phy0_host: host-port {
272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "linestate";
279 u2phy1: usb2phy@800 {
280 compatible = "rockchip,rk3228-usb2phy";
282 clocks = <&cru SCLK_OTGPHY1>;
283 clock-names = "phyclk";
284 clock-output-names = "usb480m_phy1";
288 u2phy1_otg: otg-port {
289 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "linestate";
295 u2phy1_host: host-port {
296 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "linestate";
304 uart0: serial@11010000 {
305 compatible = "snps,dw-apb-uart";
306 reg = <0x11010000 0x100>;
307 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
308 clock-frequency = <24000000>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
318 uart1: serial@11020000 {
319 compatible = "snps,dw-apb-uart";
320 reg = <0x11020000 0x100>;
321 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
322 clock-frequency = <24000000>;
323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
324 clock-names = "baudclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_xfer>;
332 uart2: serial@11030000 {
333 compatible = "snps,dw-apb-uart";
334 reg = <0x11030000 0x100>;
335 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
336 clock-frequency = <24000000>;
337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
338 clock-names = "baudclk", "apb_pclk";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_xfer>;
346 efuse: efuse@11040000 {
347 compatible = "rockchip,rk3228-efuse";
348 reg = <0x11040000 0x20>;
349 clocks = <&cru PCLK_EFUSE_256>;
350 clock-names = "pclk_efuse";
351 #address-cells = <1>;
358 cpu_leakage: cpu_leakage@17 {
364 compatible = "rockchip,rk3228-i2c";
365 reg = <0x11050000 0x1000>;
366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
370 clocks = <&cru PCLK_I2C0>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c0_xfer>;
377 compatible = "rockchip,rk3228-i2c";
378 reg = <0x11060000 0x1000>;
379 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
383 clocks = <&cru PCLK_I2C1>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c1_xfer>;
390 compatible = "rockchip,rk3228-i2c";
391 reg = <0x11070000 0x1000>;
392 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
396 clocks = <&cru PCLK_I2C2>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2c2_xfer>;
403 compatible = "rockchip,rk3228-i2c";
404 reg = <0x11080000 0x1000>;
405 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
409 clocks = <&cru PCLK_I2C3>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c3_xfer>;
416 compatible = "rockchip,rk3228-spi";
417 reg = <0x11090000 0x1000>;
418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
422 clock-names = "spiclk", "apb_pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
428 wdt: watchdog@110a0000 {
429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
430 reg = <0x110a0000 0x100>;
431 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru PCLK_CPU>;
437 compatible = "rockchip,rk3288-pwm";
438 reg = <0x110b0000 0x10>;
440 clocks = <&cru PCLK_PWM>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pwm0_pin>;
447 compatible = "rockchip,rk3288-pwm";
448 reg = <0x110b0010 0x10>;
450 clocks = <&cru PCLK_PWM>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pwm1_pin>;
457 compatible = "rockchip,rk3288-pwm";
458 reg = <0x110b0020 0x10>;
460 clocks = <&cru PCLK_PWM>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pwm2_pin>;
467 compatible = "rockchip,rk3288-pwm";
468 reg = <0x110b0030 0x10>;
470 clocks = <&cru PCLK_PWM>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm3_pin>;
476 timer: timer@110c0000 {
477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
478 reg = <0x110c0000 0x20>;
479 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&cru PCLK_TIMER>, <&xin24m>;
481 clock-names = "pclk", "timer";
484 cru: clock-controller@110e0000 {
485 compatible = "rockchip,rk3228-cru";
486 reg = <0x110e0000 0x1000>;
488 clock-names = "xin24m";
489 rockchip,grf = <&grf>;
493 <&cru PLL_GPLL>, <&cru ARMCLK>,
494 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
495 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
496 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
498 assigned-clock-rates =
499 <594000000>, <816000000>,
500 <500000000>, <150000000>,
501 <150000000>, <75000000>,
502 <150000000>, <150000000>,
506 pdma: dma-controller@110f0000 {
507 compatible = "arm,pl330", "arm,primecell";
508 reg = <0x110f0000 0x4000>;
509 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
512 arm,pl330-periph-burst;
513 clocks = <&cru ACLK_DMAC>;
514 clock-names = "apb_pclk";
518 cpu_thermal: cpu-thermal {
519 polling-delay-passive = <100>; /* milliseconds */
520 polling-delay = <5000>; /* milliseconds */
522 thermal-sensors = <&tsadc 0>;
525 cpu_alert0: cpu_alert0 {
526 temperature = <70000>; /* millicelsius */
527 hysteresis = <2000>; /* millicelsius */
530 cpu_alert1: cpu_alert1 {
531 temperature = <75000>; /* millicelsius */
532 hysteresis = <2000>; /* millicelsius */
536 temperature = <90000>; /* millicelsius */
537 hysteresis = <2000>; /* millicelsius */
544 trip = <&cpu_alert0>;
546 <&cpu0 THERMAL_NO_LIMIT 6>,
547 <&cpu1 THERMAL_NO_LIMIT 6>,
548 <&cpu2 THERMAL_NO_LIMIT 6>,
549 <&cpu3 THERMAL_NO_LIMIT 6>;
552 trip = <&cpu_alert1>;
554 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
555 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
556 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
557 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
563 tsadc: tsadc@11150000 {
564 compatible = "rockchip,rk3228-tsadc";
565 reg = <0x11150000 0x100>;
566 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
568 clock-names = "tsadc", "apb_pclk";
569 assigned-clocks = <&cru SCLK_TSADC>;
570 assigned-clock-rates = <32768>;
571 resets = <&cru SRST_TSADC>;
572 reset-names = "tsadc-apb";
573 pinctrl-names = "init", "default", "sleep";
574 pinctrl-0 = <&otp_pin>;
575 pinctrl-1 = <&otp_out>;
576 pinctrl-2 = <&otp_pin>;
577 #thermal-sensor-cells = <1>;
578 rockchip,hw-tshut-temp = <95000>;
582 hdmi_phy: hdmi-phy@12030000 {
583 compatible = "rockchip,rk3228-hdmi-phy";
584 reg = <0x12030000 0x10000>;
585 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
586 clock-names = "sysclk", "refoclk", "refpclk";
588 clock-output-names = "hdmiphy_phy";
594 compatible = "rockchip,rk3228-mali", "arm,mali-400";
595 reg = <0x20000000 0x10000>;
596 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
602 interrupt-names = "gp",
608 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
609 clock-names = "bus", "core";
610 power-domains = <&power RK3228_PD_GPU>;
611 resets = <&cru SRST_GPU_A>;
615 vpu: video-codec@20020000 {
616 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
617 reg = <0x20020000 0x800>;
618 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-names = "vepu", "vdpu";
621 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
622 clock-names = "aclk", "hclk";
624 power-domains = <&power RK3228_PD_VPU>;
627 vpu_mmu: iommu@20020800 {
628 compatible = "rockchip,iommu";
629 reg = <0x20020800 0x100>;
630 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
632 clock-names = "aclk", "iface";
633 power-domains = <&power RK3228_PD_VPU>;
637 vdec: video-codec@20030000 {
638 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
639 reg = <0x20030000 0x480>;
640 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
642 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
643 clock-names = "axi", "ahb", "cabac", "core";
644 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
645 assigned-clock-rates = <300000000>, <300000000>;
646 iommus = <&vdec_mmu>;
647 power-domains = <&power RK3228_PD_RKVDEC>;
650 vdec_mmu: iommu@20030480 {
651 compatible = "rockchip,iommu";
652 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
653 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
655 clock-names = "aclk", "iface";
656 power-domains = <&power RK3228_PD_RKVDEC>;
661 compatible = "rockchip,rk3228-vop";
662 reg = <0x20050000 0x1ffc>;
663 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
665 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
666 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
667 reset-names = "axi", "ahb", "dclk";
669 power-domains = <&power RK3228_PD_VOP>;
673 #address-cells = <1>;
676 vop_out_hdmi: endpoint@0 {
678 remote-endpoint = <&hdmi_in_vop>;
683 vop_mmu: iommu@20053f00 {
684 compatible = "rockchip,iommu";
685 reg = <0x20053f00 0x100>;
686 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
688 clock-names = "aclk", "iface";
689 power-domains = <&power RK3228_PD_VOP>;
695 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
696 reg = <0x20060000 0x1000>;
697 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
699 clock-names = "aclk", "hclk", "sclk";
700 power-domains = <&power RK3228_PD_VIO>;
701 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
702 reset-names = "core", "axi", "ahb";
705 iep_mmu: iommu@20070800 {
706 compatible = "rockchip,iommu";
707 reg = <0x20070800 0x100>;
708 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
710 clock-names = "aclk", "iface";
711 power-domains = <&power RK3228_PD_VIO>;
716 hdmi: hdmi@200a0000 {
717 compatible = "rockchip,rk3228-dw-hdmi";
718 reg = <0x200a0000 0x20000>;
720 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
721 assigned-clocks = <&cru SCLK_HDMI_PHY>;
722 assigned-clock-parents = <&hdmi_phy>;
723 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
724 clock-names = "iahb", "isfr", "cec";
725 pinctrl-names = "default";
726 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
727 resets = <&cru SRST_HDMI_P>;
728 reset-names = "hdmi";
731 rockchip,grf = <&grf>;
736 #address-cells = <1>;
738 hdmi_in_vop: endpoint@0 {
740 remote-endpoint = <&vop_out_hdmi>;
746 sdmmc: mmc@30000000 {
747 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
748 reg = <0x30000000 0x4000>;
749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
751 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
752 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
753 fifo-depth = <0x100>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
760 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
761 reg = <0x30010000 0x4000>;
762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
764 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
765 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
766 fifo-depth = <0x100>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
773 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
774 reg = <0x30020000 0x4000>;
775 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
776 clock-frequency = <37500000>;
777 max-frequency = <37500000>;
778 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
779 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
780 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
782 rockchip,default-sample-phase = <158>;
783 fifo-depth = <0x100>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
786 resets = <&cru SRST_EMMC>;
787 reset-names = "reset";
791 usb_otg: usb@30040000 {
792 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
794 reg = <0x30040000 0x40000>;
795 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&cru HCLK_OTG>;
799 g-np-tx-fifo-size = <16>;
800 g-rx-fifo-size = <280>;
801 g-tx-fifo-size = <256 128 128 64 32 16>;
802 phys = <&u2phy0_otg>;
803 phy-names = "usb2-phy";
807 usb_host0_ehci: usb@30080000 {
808 compatible = "generic-ehci";
809 reg = <0x30080000 0x20000>;
810 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
812 phys = <&u2phy0_host>;
817 usb_host0_ohci: usb@300a0000 {
818 compatible = "generic-ohci";
819 reg = <0x300a0000 0x20000>;
820 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
822 phys = <&u2phy0_host>;
827 usb_host1_ehci: usb@300c0000 {
828 compatible = "generic-ehci";
829 reg = <0x300c0000 0x20000>;
830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
832 phys = <&u2phy1_otg>;
837 usb_host1_ohci: usb@300e0000 {
838 compatible = "generic-ohci";
839 reg = <0x300e0000 0x20000>;
840 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
842 phys = <&u2phy1_otg>;
847 usb_host2_ehci: usb@30100000 {
848 compatible = "generic-ehci";
849 reg = <0x30100000 0x20000>;
850 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
852 phys = <&u2phy1_host>;
857 usb_host2_ohci: usb@30120000 {
858 compatible = "generic-ohci";
859 reg = <0x30120000 0x20000>;
860 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
862 phys = <&u2phy1_host>;
867 gmac: ethernet@30200000 {
868 compatible = "rockchip,rk3228-gmac";
869 reg = <0x30200000 0x10000>;
870 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
871 interrupt-names = "macirq";
872 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
873 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
874 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
876 clock-names = "stmmaceth", "mac_clk_rx",
877 "mac_clk_tx", "clk_mac_ref",
878 "clk_mac_refout", "aclk_mac",
880 resets = <&cru SRST_GMAC>;
881 reset-names = "stmmaceth";
882 rockchip,grf = <&grf>;
886 qos_iep: qos@31030080 {
887 compatible = "rockchip,rk3228-qos", "syscon";
888 reg = <0x31030080 0x20>;
891 qos_rga_w: qos@31030100 {
892 compatible = "rockchip,rk3228-qos", "syscon";
893 reg = <0x31030100 0x20>;
896 qos_hdcp: qos@31030180 {
897 compatible = "rockchip,rk3228-qos", "syscon";
898 reg = <0x31030180 0x20>;
901 qos_rga_r: qos@31030200 {
902 compatible = "rockchip,rk3228-qos", "syscon";
903 reg = <0x31030200 0x20>;
906 qos_vpu: qos@31040000 {
907 compatible = "rockchip,rk3228-qos", "syscon";
908 reg = <0x31040000 0x20>;
911 qos_gpu: qos@31050000 {
912 compatible = "rockchip,rk3228-qos", "syscon";
913 reg = <0x31050000 0x20>;
916 qos_vop: qos@31060000 {
917 compatible = "rockchip,rk3228-qos", "syscon";
918 reg = <0x31060000 0x20>;
921 qos_rkvdec_r: qos@31070000 {
922 compatible = "rockchip,rk3228-qos", "syscon";
923 reg = <0x31070000 0x20>;
926 qos_rkvdec_w: qos@31070080 {
927 compatible = "rockchip,rk3228-qos", "syscon";
928 reg = <0x31070080 0x20>;
931 gic: interrupt-controller@32010000 {
932 compatible = "arm,gic-400";
933 interrupt-controller;
934 #interrupt-cells = <3>;
935 #address-cells = <0>;
937 reg = <0x32011000 0x1000>,
941 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
945 compatible = "rockchip,rk3228-pinctrl";
946 rockchip,grf = <&grf>;
947 #address-cells = <1>;
951 gpio0: gpio@11110000 {
952 compatible = "rockchip,gpio-bank";
953 reg = <0x11110000 0x100>;
954 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&cru PCLK_GPIO0>;
960 interrupt-controller;
961 #interrupt-cells = <2>;
964 gpio1: gpio@11120000 {
965 compatible = "rockchip,gpio-bank";
966 reg = <0x11120000 0x100>;
967 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&cru PCLK_GPIO1>;
973 interrupt-controller;
974 #interrupt-cells = <2>;
977 gpio2: gpio@11130000 {
978 compatible = "rockchip,gpio-bank";
979 reg = <0x11130000 0x100>;
980 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru PCLK_GPIO2>;
986 interrupt-controller;
987 #interrupt-cells = <2>;
990 gpio3: gpio@11140000 {
991 compatible = "rockchip,gpio-bank";
992 reg = <0x11140000 0x100>;
993 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru PCLK_GPIO3>;
999 interrupt-controller;
1000 #interrupt-cells = <2>;
1003 pcfg_pull_up: pcfg-pull-up {
1007 pcfg_pull_down: pcfg-pull-down {
1011 pcfg_pull_none: pcfg-pull-none {
1015 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1016 drive-strength = <12>;
1020 sdmmc_clk: sdmmc-clk {
1021 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
1024 sdmmc_cmd: sdmmc-cmd {
1025 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
1028 sdmmc_bus4: sdmmc-bus4 {
1029 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1030 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1031 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
1032 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
1037 sdio_clk: sdio-clk {
1038 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
1041 sdio_cmd: sdio-cmd {
1042 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
1045 sdio_bus4: sdio-bus4 {
1046 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
1047 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
1048 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
1049 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
1054 emmc_clk: emmc-clk {
1055 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
1058 emmc_cmd: emmc-cmd {
1059 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
1062 emmc_bus8: emmc-bus8 {
1063 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
1064 <1 RK_PD1 2 &pcfg_pull_none>,
1065 <1 RK_PD2 2 &pcfg_pull_none>,
1066 <1 RK_PD3 2 &pcfg_pull_none>,
1067 <1 RK_PD4 2 &pcfg_pull_none>,
1068 <1 RK_PD5 2 &pcfg_pull_none>,
1069 <1 RK_PD6 2 &pcfg_pull_none>,
1070 <1 RK_PD7 2 &pcfg_pull_none>;
1075 rgmii_pins: rgmii-pins {
1076 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1077 <2 RK_PB4 1 &pcfg_pull_none>,
1078 <2 RK_PD1 1 &pcfg_pull_none>,
1079 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1080 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1081 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
1082 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
1083 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
1084 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1085 <2 RK_PC1 1 &pcfg_pull_none>,
1086 <2 RK_PC0 1 &pcfg_pull_none>,
1087 <2 RK_PC5 2 &pcfg_pull_none>,
1088 <2 RK_PC4 2 &pcfg_pull_none>,
1089 <2 RK_PB3 1 &pcfg_pull_none>,
1090 <2 RK_PB0 1 &pcfg_pull_none>;
1093 rmii_pins: rmii-pins {
1094 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1095 <2 RK_PB4 1 &pcfg_pull_none>,
1096 <2 RK_PD1 1 &pcfg_pull_none>,
1097 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1098 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1099 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1100 <2 RK_PC1 1 &pcfg_pull_none>,
1101 <2 RK_PC0 1 &pcfg_pull_none>,
1102 <2 RK_PB0 1 &pcfg_pull_none>,
1103 <2 RK_PB7 1 &pcfg_pull_none>;
1106 phy_pins: phy-pins {
1107 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
1108 <2 RK_PB0 2 &pcfg_pull_none>;
1113 hdmi_hpd: hdmi-hpd {
1114 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1117 hdmii2c_xfer: hdmii2c-xfer {
1118 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1119 <0 RK_PA7 2 &pcfg_pull_none>;
1122 hdmi_cec: hdmi-cec {
1123 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1128 i2c0_xfer: i2c0-xfer {
1129 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1130 <0 RK_PA1 1 &pcfg_pull_none>;
1135 i2c1_xfer: i2c1-xfer {
1136 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1137 <0 RK_PA3 1 &pcfg_pull_none>;
1142 i2c2_xfer: i2c2-xfer {
1143 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1144 <2 RK_PC5 1 &pcfg_pull_none>;
1149 i2c3_xfer: i2c3-xfer {
1150 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1151 <0 RK_PA7 1 &pcfg_pull_none>;
1156 spi0_clk: spi0-clk {
1157 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1159 spi0_cs0: spi0-cs0 {
1160 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1163 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1166 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1168 spi0_cs1: spi0-cs1 {
1169 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1174 spi1_clk: spi1-clk {
1175 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1177 spi1_cs0: spi1-cs0 {
1178 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1181 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1184 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1186 spi1_cs1: spi1-cs1 {
1187 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1192 i2s1_bus: i2s1-bus {
1193 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1194 <0 RK_PB1 1 &pcfg_pull_none>,
1195 <0 RK_PB3 1 &pcfg_pull_none>,
1196 <0 RK_PB4 1 &pcfg_pull_none>,
1197 <0 RK_PB5 1 &pcfg_pull_none>,
1198 <0 RK_PB6 1 &pcfg_pull_none>,
1199 <1 RK_PA2 2 &pcfg_pull_none>,
1200 <1 RK_PA4 2 &pcfg_pull_none>,
1201 <1 RK_PA5 2 &pcfg_pull_none>;
1206 pwm0_pin: pwm0-pin {
1207 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1212 pwm1_pin: pwm1-pin {
1213 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1218 pwm2_pin: pwm2-pin {
1219 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1224 pwm3_pin: pwm3-pin {
1225 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1230 spdif_tx: spdif-tx {
1231 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1237 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1241 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1246 uart0_xfer: uart0-xfer {
1247 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1248 <2 RK_PD3 1 &pcfg_pull_none>;
1251 uart0_cts: uart0-cts {
1252 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1255 uart0_rts: uart0-rts {
1256 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1261 uart1_xfer: uart1-xfer {
1262 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1263 <1 RK_PB2 1 &pcfg_pull_none>;
1266 uart1_cts: uart1-cts {
1267 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1270 uart1_rts: uart1-rts {
1271 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1276 uart2_xfer: uart2-xfer {
1277 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1278 <1 RK_PC3 2 &pcfg_pull_none>;
1281 uart21_xfer: uart21-xfer {
1282 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1283 <1 RK_PB1 2 &pcfg_pull_none>;
1286 uart2_cts: uart2-cts {
1287 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1290 uart2_rts: uart2-rts {
1291 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;