1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
32 compatible = "arm,cortex-a7";
34 resets = <&cru SRST_CORE0>;
35 operating-points-v2 = <&cpu0_opp_table>;
36 #cooling-cells = <2>; /* min followed by max */
37 clock-latency = <40000>;
38 clocks = <&cru ARMCLK>;
39 enable-method = "psci";
44 compatible = "arm,cortex-a7";
46 resets = <&cru SRST_CORE1>;
47 operating-points-v2 = <&cpu0_opp_table>;
48 #cooling-cells = <2>; /* min followed by max */
49 enable-method = "psci";
54 compatible = "arm,cortex-a7";
56 resets = <&cru SRST_CORE2>;
57 operating-points-v2 = <&cpu0_opp_table>;
58 #cooling-cells = <2>; /* min followed by max */
59 enable-method = "psci";
64 compatible = "arm,cortex-a7";
66 resets = <&cru SRST_CORE3>;
67 operating-points-v2 = <&cpu0_opp_table>;
68 #cooling-cells = <2>; /* min followed by max */
69 enable-method = "psci";
73 cpu0_opp_table: opp_table0 {
74 compatible = "operating-points-v2";
78 opp-hz = /bits/ 64 <408000000>;
79 opp-microvolt = <950000>;
80 clock-latency-ns = <40000>;
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <975000>;
88 opp-hz = /bits/ 64 <816000000>;
89 opp-microvolt = <1000000>;
92 opp-hz = /bits/ 64 <1008000000>;
93 opp-microvolt = <1175000>;
96 opp-hz = /bits/ 64 <1200000000>;
97 opp-microvolt = <1275000>;
102 compatible = "arm,cortex-a7-pmu";
103 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
111 compatible = "arm,psci-1.0", "arm,psci-0.2";
116 compatible = "arm,armv7-timer";
117 arm,cpu-registers-not-fw-configured;
118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
122 clock-frequency = <24000000>;
126 compatible = "fixed-clock";
127 clock-frequency = <24000000>;
128 clock-output-names = "xin24m";
132 display_subsystem: display-subsystem {
133 compatible = "rockchip,display-subsystem";
137 i2s1: i2s1@100b0000 {
138 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
139 reg = <0x100b0000 0x4000>;
140 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
141 clock-names = "i2s_clk", "i2s_hclk";
142 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
143 dmas = <&pdma 14>, <&pdma 15>;
144 dma-names = "tx", "rx";
145 pinctrl-names = "default";
146 pinctrl-0 = <&i2s1_bus>;
150 i2s0: i2s0@100c0000 {
151 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
152 reg = <0x100c0000 0x4000>;
153 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
154 clock-names = "i2s_clk", "i2s_hclk";
155 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
156 dmas = <&pdma 11>, <&pdma 12>;
157 dma-names = "tx", "rx";
161 spdif: spdif@100d0000 {
162 compatible = "rockchip,rk3228-spdif";
163 reg = <0x100d0000 0x1000>;
164 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
166 clock-names = "mclk", "hclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&spdif_tx>;
174 i2s2: i2s2@100e0000 {
175 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
176 reg = <0x100e0000 0x4000>;
177 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
178 clock-names = "i2s_clk", "i2s_hclk";
179 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
180 dmas = <&pdma 0>, <&pdma 1>;
181 dma-names = "tx", "rx";
185 grf: syscon@11000000 {
186 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
187 reg = <0x11000000 0x1000>;
188 #address-cells = <1>;
191 io_domains: io-domains {
192 compatible = "rockchip,rk3228-io-voltage-domain";
196 u2phy0: usb2-phy@760 {
197 compatible = "rockchip,rk3228-usb2phy";
199 clocks = <&cru SCLK_OTGPHY0>;
200 clock-names = "phyclk";
201 clock-output-names = "usb480m_phy0";
205 u2phy0_otg: otg-port {
206 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
209 interrupt-names = "otg-bvalid", "otg-id",
215 u2phy0_host: host-port {
216 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-names = "linestate";
223 u2phy1: usb2-phy@800 {
224 compatible = "rockchip,rk3228-usb2phy";
226 clocks = <&cru SCLK_OTGPHY1>;
227 clock-names = "phyclk";
228 clock-output-names = "usb480m_phy1";
232 u2phy1_otg: otg-port {
233 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-names = "linestate";
239 u2phy1_host: host-port {
240 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "linestate";
248 uart0: serial@11010000 {
249 compatible = "snps,dw-apb-uart";
250 reg = <0x11010000 0x100>;
251 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
252 clock-frequency = <24000000>;
253 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
254 clock-names = "baudclk", "apb_pclk";
255 pinctrl-names = "default";
256 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
262 uart1: serial@11020000 {
263 compatible = "snps,dw-apb-uart";
264 reg = <0x11020000 0x100>;
265 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
266 clock-frequency = <24000000>;
267 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
268 clock-names = "baudclk", "apb_pclk";
269 pinctrl-names = "default";
270 pinctrl-0 = <&uart1_xfer>;
276 uart2: serial@11030000 {
277 compatible = "snps,dw-apb-uart";
278 reg = <0x11030000 0x100>;
279 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
280 clock-frequency = <24000000>;
281 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
282 clock-names = "baudclk", "apb_pclk";
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart2_xfer>;
290 efuse: efuse@11040000 {
291 compatible = "rockchip,rk3228-efuse";
292 reg = <0x11040000 0x20>;
293 clocks = <&cru PCLK_EFUSE_256>;
294 clock-names = "pclk_efuse";
295 #address-cells = <1>;
302 cpu_leakage: cpu_leakage@17 {
308 compatible = "rockchip,rk3228-i2c";
309 reg = <0x11050000 0x1000>;
310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
314 clocks = <&cru PCLK_I2C0>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c0_xfer>;
321 compatible = "rockchip,rk3228-i2c";
322 reg = <0x11060000 0x1000>;
323 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
324 #address-cells = <1>;
327 clocks = <&cru PCLK_I2C1>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c1_xfer>;
334 compatible = "rockchip,rk3228-i2c";
335 reg = <0x11070000 0x1000>;
336 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
337 #address-cells = <1>;
340 clocks = <&cru PCLK_I2C2>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c2_xfer>;
347 compatible = "rockchip,rk3228-i2c";
348 reg = <0x11080000 0x1000>;
349 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
353 clocks = <&cru PCLK_I2C3>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_xfer>;
360 compatible = "rockchip,rk3228-spi";
361 reg = <0x11090000 0x1000>;
362 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
365 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
366 clock-names = "spiclk", "apb_pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
372 wdt: watchdog@110a0000 {
373 compatible = "snps,dw-wdt";
374 reg = <0x110a0000 0x100>;
375 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru PCLK_CPU>;
381 compatible = "rockchip,rk3288-pwm";
382 reg = <0x110b0000 0x10>;
384 clocks = <&cru PCLK_PWM>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pwm0_pin>;
392 compatible = "rockchip,rk3288-pwm";
393 reg = <0x110b0010 0x10>;
395 clocks = <&cru PCLK_PWM>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pwm1_pin>;
403 compatible = "rockchip,rk3288-pwm";
404 reg = <0x110b0020 0x10>;
406 clocks = <&cru PCLK_PWM>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pwm2_pin>;
414 compatible = "rockchip,rk3288-pwm";
415 reg = <0x110b0030 0x10>;
417 clocks = <&cru PCLK_PWM>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pwm3_pin>;
424 timer: timer@110c0000 {
425 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
426 reg = <0x110c0000 0x20>;
427 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&xin24m>, <&cru PCLK_TIMER>;
429 clock-names = "timer", "pclk";
432 cru: clock-controller@110e0000 {
433 compatible = "rockchip,rk3228-cru";
434 reg = <0x110e0000 0x1000>;
435 rockchip,grf = <&grf>;
439 <&cru PLL_GPLL>, <&cru ARMCLK>,
440 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
441 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
442 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
444 assigned-clock-rates =
445 <594000000>, <816000000>,
446 <500000000>, <150000000>,
447 <150000000>, <75000000>,
448 <150000000>, <150000000>,
452 pdma: pdma@110f0000 {
453 compatible = "arm,pl330", "arm,primecell";
454 reg = <0x110f0000 0x4000>;
455 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
458 arm,pl330-periph-burst;
459 clocks = <&cru ACLK_DMAC>;
460 clock-names = "apb_pclk";
464 cpu_thermal: cpu-thermal {
465 polling-delay-passive = <100>; /* milliseconds */
466 polling-delay = <5000>; /* milliseconds */
468 thermal-sensors = <&tsadc 0>;
471 cpu_alert0: cpu_alert0 {
472 temperature = <70000>; /* millicelsius */
473 hysteresis = <2000>; /* millicelsius */
476 cpu_alert1: cpu_alert1 {
477 temperature = <75000>; /* millicelsius */
478 hysteresis = <2000>; /* millicelsius */
482 temperature = <90000>; /* millicelsius */
483 hysteresis = <2000>; /* millicelsius */
490 trip = <&cpu_alert0>;
492 <&cpu0 THERMAL_NO_LIMIT 6>,
493 <&cpu1 THERMAL_NO_LIMIT 6>,
494 <&cpu2 THERMAL_NO_LIMIT 6>,
495 <&cpu3 THERMAL_NO_LIMIT 6>;
498 trip = <&cpu_alert1>;
500 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
501 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
502 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
503 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
509 tsadc: tsadc@11150000 {
510 compatible = "rockchip,rk3228-tsadc";
511 reg = <0x11150000 0x100>;
512 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
514 clock-names = "tsadc", "apb_pclk";
515 assigned-clocks = <&cru SCLK_TSADC>;
516 assigned-clock-rates = <32768>;
517 resets = <&cru SRST_TSADC>;
518 reset-names = "tsadc-apb";
519 pinctrl-names = "init", "default", "sleep";
520 pinctrl-0 = <&otp_pin>;
521 pinctrl-1 = <&otp_out>;
522 pinctrl-2 = <&otp_pin>;
523 #thermal-sensor-cells = <0>;
524 rockchip,hw-tshut-temp = <95000>;
528 hdmi_phy: hdmi-phy@12030000 {
529 compatible = "rockchip,rk3228-hdmi-phy";
530 reg = <0x12030000 0x10000>;
531 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
532 clock-names = "sysclk", "refoclk", "refpclk";
534 clock-output-names = "hdmiphy_phy";
540 compatible = "rockchip,rk3228-mali", "arm,mali-400";
541 reg = <0x20000000 0x10000>;
542 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "gp",
554 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
555 clock-names = "bus", "core";
556 resets = <&cru SRST_GPU_A>;
560 vpu_mmu: iommu@20020800 {
561 compatible = "rockchip,iommu";
562 reg = <0x20020800 0x100>;
563 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-names = "vpu_mmu";
565 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
566 clock-names = "aclk", "iface";
571 vdec_mmu: iommu@20030480 {
572 compatible = "rockchip,iommu";
573 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
574 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "vdec_mmu";
576 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
577 clock-names = "aclk", "iface";
583 compatible = "rockchip,rk3228-vop";
584 reg = <0x20050000 0x1ffc>;
585 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
587 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
588 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
589 reset-names = "axi", "ahb", "dclk";
594 #address-cells = <1>;
597 vop_out_hdmi: endpoint@0 {
599 remote-endpoint = <&hdmi_in_vop>;
604 vop_mmu: iommu@20053f00 {
605 compatible = "rockchip,iommu";
606 reg = <0x20053f00 0x100>;
607 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
608 interrupt-names = "vop_mmu";
609 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
610 clock-names = "aclk", "iface";
616 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
617 reg = <0x20060000 0x1000>;
618 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
620 clock-names = "aclk", "hclk", "sclk";
621 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
622 reset-names = "core", "axi", "ahb";
625 iep_mmu: iommu@20070800 {
626 compatible = "rockchip,iommu";
627 reg = <0x20070800 0x100>;
628 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-names = "iep_mmu";
630 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
631 clock-names = "aclk", "iface";
636 hdmi: hdmi@200a0000 {
637 compatible = "rockchip,rk3228-dw-hdmi";
638 reg = <0x200a0000 0x20000>;
640 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
641 assigned-clocks = <&cru SCLK_HDMI_PHY>;
642 assigned-clock-parents = <&hdmi_phy>;
643 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
644 clock-names = "isfr", "iahb", "cec";
645 pinctrl-names = "default";
646 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
647 resets = <&cru SRST_HDMI_P>;
648 reset-names = "hdmi";
651 rockchip,grf = <&grf>;
656 #address-cells = <1>;
658 hdmi_in_vop: endpoint@0 {
660 remote-endpoint = <&vop_out_hdmi>;
666 sdmmc: mmc@30000000 {
667 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
668 reg = <0x30000000 0x4000>;
669 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
671 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
672 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
673 fifo-depth = <0x100>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
680 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
681 reg = <0x30010000 0x4000>;
682 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
684 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
685 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
686 fifo-depth = <0x100>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
693 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
694 reg = <0x30020000 0x4000>;
695 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
696 clock-frequency = <37500000>;
697 max-frequency = <37500000>;
698 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
699 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
700 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
702 rockchip,default-sample-phase = <158>;
703 fifo-depth = <0x100>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
706 resets = <&cru SRST_EMMC>;
707 reset-names = "reset";
711 usb_otg: usb@30040000 {
712 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
714 reg = <0x30040000 0x40000>;
715 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&cru HCLK_OTG>;
719 g-np-tx-fifo-size = <16>;
720 g-rx-fifo-size = <280>;
721 g-tx-fifo-size = <256 128 128 64 32 16>;
722 phys = <&u2phy0_otg>;
723 phy-names = "usb2-phy";
727 usb_host0_ehci: usb@30080000 {
728 compatible = "generic-ehci";
729 reg = <0x30080000 0x20000>;
730 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
732 phys = <&u2phy0_host>;
737 usb_host0_ohci: usb@300a0000 {
738 compatible = "generic-ohci";
739 reg = <0x300a0000 0x20000>;
740 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
742 phys = <&u2phy0_host>;
747 usb_host1_ehci: usb@300c0000 {
748 compatible = "generic-ehci";
749 reg = <0x300c0000 0x20000>;
750 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
752 phys = <&u2phy1_otg>;
757 usb_host1_ohci: usb@300e0000 {
758 compatible = "generic-ohci";
759 reg = <0x300e0000 0x20000>;
760 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
762 phys = <&u2phy1_otg>;
767 usb_host2_ehci: usb@30100000 {
768 compatible = "generic-ehci";
769 reg = <0x30100000 0x20000>;
770 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
772 phys = <&u2phy1_host>;
777 usb_host2_ohci: usb@30120000 {
778 compatible = "generic-ohci";
779 reg = <0x30120000 0x20000>;
780 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
782 phys = <&u2phy1_host>;
787 gmac: ethernet@30200000 {
788 compatible = "rockchip,rk3228-gmac";
789 reg = <0x30200000 0x10000>;
790 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
791 interrupt-names = "macirq";
792 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
793 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
794 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
796 clock-names = "stmmaceth", "mac_clk_rx",
797 "mac_clk_tx", "clk_mac_ref",
798 "clk_mac_refout", "aclk_mac",
800 resets = <&cru SRST_GMAC>;
801 reset-names = "stmmaceth";
802 rockchip,grf = <&grf>;
806 gic: interrupt-controller@32010000 {
807 compatible = "arm,gic-400";
808 interrupt-controller;
809 #interrupt-cells = <3>;
810 #address-cells = <0>;
812 reg = <0x32011000 0x1000>,
816 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
820 compatible = "rockchip,rk3228-pinctrl";
821 rockchip,grf = <&grf>;
822 #address-cells = <1>;
826 gpio0: gpio0@11110000 {
827 compatible = "rockchip,gpio-bank";
828 reg = <0x11110000 0x100>;
829 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&cru PCLK_GPIO0>;
835 interrupt-controller;
836 #interrupt-cells = <2>;
839 gpio1: gpio1@11120000 {
840 compatible = "rockchip,gpio-bank";
841 reg = <0x11120000 0x100>;
842 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&cru PCLK_GPIO1>;
848 interrupt-controller;
849 #interrupt-cells = <2>;
852 gpio2: gpio2@11130000 {
853 compatible = "rockchip,gpio-bank";
854 reg = <0x11130000 0x100>;
855 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&cru PCLK_GPIO2>;
861 interrupt-controller;
862 #interrupt-cells = <2>;
865 gpio3: gpio3@11140000 {
866 compatible = "rockchip,gpio-bank";
867 reg = <0x11140000 0x100>;
868 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&cru PCLK_GPIO3>;
874 interrupt-controller;
875 #interrupt-cells = <2>;
878 pcfg_pull_up: pcfg-pull-up {
882 pcfg_pull_down: pcfg-pull-down {
886 pcfg_pull_none: pcfg-pull-none {
890 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
891 drive-strength = <12>;
895 sdmmc_clk: sdmmc-clk {
896 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
899 sdmmc_cmd: sdmmc-cmd {
900 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
903 sdmmc_bus4: sdmmc-bus4 {
904 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
905 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
906 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
907 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
913 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
917 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
920 sdio_bus4: sdio-bus4 {
921 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
922 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
923 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
924 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
930 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
934 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
937 emmc_bus8: emmc-bus8 {
938 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
939 <1 RK_PD1 2 &pcfg_pull_none>,
940 <1 RK_PD2 2 &pcfg_pull_none>,
941 <1 RK_PD3 2 &pcfg_pull_none>,
942 <1 RK_PD4 2 &pcfg_pull_none>,
943 <1 RK_PD5 2 &pcfg_pull_none>,
944 <1 RK_PD6 2 &pcfg_pull_none>,
945 <1 RK_PD7 2 &pcfg_pull_none>;
950 rgmii_pins: rgmii-pins {
951 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
952 <2 RK_PB4 1 &pcfg_pull_none>,
953 <2 RK_PD1 1 &pcfg_pull_none>,
954 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
955 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
956 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
957 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
958 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
959 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
960 <2 RK_PC1 1 &pcfg_pull_none>,
961 <2 RK_PC0 1 &pcfg_pull_none>,
962 <2 RK_PC5 2 &pcfg_pull_none>,
963 <2 RK_PC4 2 &pcfg_pull_none>,
964 <2 RK_PB3 1 &pcfg_pull_none>,
965 <2 RK_PB0 1 &pcfg_pull_none>;
968 rmii_pins: rmii-pins {
969 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
970 <2 RK_PB4 1 &pcfg_pull_none>,
971 <2 RK_PD1 1 &pcfg_pull_none>,
972 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
973 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
974 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
975 <2 RK_PC1 1 &pcfg_pull_none>,
976 <2 RK_PC0 1 &pcfg_pull_none>,
977 <2 RK_PB0 1 &pcfg_pull_none>,
978 <2 RK_PB7 1 &pcfg_pull_none>;
982 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
983 <2 RK_PB0 2 &pcfg_pull_none>;
989 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
992 hdmii2c_xfer: hdmii2c-xfer {
993 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
994 <0 RK_PA7 2 &pcfg_pull_none>;
998 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1003 i2c0_xfer: i2c0-xfer {
1004 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1005 <0 RK_PA1 1 &pcfg_pull_none>;
1010 i2c1_xfer: i2c1-xfer {
1011 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1012 <0 RK_PA3 1 &pcfg_pull_none>;
1017 i2c2_xfer: i2c2-xfer {
1018 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1019 <2 RK_PC5 1 &pcfg_pull_none>;
1024 i2c3_xfer: i2c3-xfer {
1025 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1026 <0 RK_PA7 1 &pcfg_pull_none>;
1031 spi0_clk: spi0-clk {
1032 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1034 spi0_cs0: spi0-cs0 {
1035 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1038 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1041 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1043 spi0_cs1: spi0-cs1 {
1044 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1049 spi1_clk: spi1-clk {
1050 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1052 spi1_cs0: spi1-cs0 {
1053 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1056 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1059 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1061 spi1_cs1: spi1-cs1 {
1062 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1067 i2s1_bus: i2s1-bus {
1068 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1069 <0 RK_PB1 1 &pcfg_pull_none>,
1070 <0 RK_PB3 1 &pcfg_pull_none>,
1071 <0 RK_PB4 1 &pcfg_pull_none>,
1072 <0 RK_PB5 1 &pcfg_pull_none>,
1073 <0 RK_PB6 1 &pcfg_pull_none>,
1074 <1 RK_PA2 2 &pcfg_pull_none>,
1075 <1 RK_PA4 2 &pcfg_pull_none>,
1076 <1 RK_PA5 2 &pcfg_pull_none>;
1081 pwm0_pin: pwm0-pin {
1082 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1087 pwm1_pin: pwm1-pin {
1088 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1093 pwm2_pin: pwm2-pin {
1094 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1099 pwm3_pin: pwm3-pin {
1100 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1105 spdif_tx: spdif-tx {
1106 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1112 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1116 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1121 uart0_xfer: uart0-xfer {
1122 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1123 <2 RK_PD3 1 &pcfg_pull_none>;
1126 uart0_cts: uart0-cts {
1127 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1130 uart0_rts: uart0-rts {
1131 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1136 uart1_xfer: uart1-xfer {
1137 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1138 <1 RK_PB2 1 &pcfg_pull_none>;
1141 uart1_cts: uart1-cts {
1142 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1145 uart1_rts: uart1-rts {
1146 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1151 uart2_xfer: uart2-xfer {
1152 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1153 <1 RK_PC3 2 &pcfg_pull_none>;
1156 uart21_xfer: uart21-xfer {
1157 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1158 <1 RK_PB1 2 &pcfg_pull_none>;
1161 uart2_cts: uart2-cts {
1162 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1165 uart2_rts: uart2-rts {
1166 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;