arch/arm/boot/dts/rk3188.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3188-cru.h>
  10 #include <dt-bindings/power/rk3188-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3188";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1608000 1350000
  29                                 1416000 1250000
  30                                 1200000 1150000
  31                                 1008000 1075000
  32                                  816000  975000
  33                                  600000  950000
  34                                  504000  925000
  35                                  312000  875000
  36                         >;
  37                         clock-latency = <40000>;
  38                         clocks = <&cru ARMCLK>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         next-level-cache = <&L2>;
  44                         reg = <0x1>;
  45                 };
  46                 cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         next-level-cache = <&L2>;
  50                         reg = <0x2>;
  51                 };
  52                 cpu@3 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         next-level-cache = <&L2>;
  56                         reg = <0x3>;
  57                 };
  58         };
  59
  60         display-subsystem {
  61                 compatible = "rockchip,display-subsystem";
  62                 ports = <&vop0_out>, <&vop1_out>;
  63         };
  64
  65         sram: sram@10080000 {
  66                 compatible = "mmio-sram";
  67                 reg = <0x10080000 0x8000>;
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges = <0 0x10080000 0x8000>;
  71
  72                 smp-sram@0 {
  73                         compatible = "rockchip,rk3066-smp-sram";
  74                         reg = <0x0 0x50>;
  75                 };
  76         };
  77
  78         vop0: vop@1010c000 {
  79                 compatible = "rockchip,rk3188-vop";
  80                 reg = <0x1010c000 0x1000>;
  81                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  82                 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
  83                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  84                 power-domains = <&power RK3188_PD_VIO>;
  85                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
  86                 reset-names = "axi", "ahb", "dclk";
  87                 status = "disabled";
  88
  89                 vop0_out: port {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                 };
  93         };
  94
  95         vop1: vop@1010e000 {
  96                 compatible = "rockchip,rk3188-vop";
  97                 reg = <0x1010e000 0x1000>;
  98                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  99                 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
 100                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 101                 power-domains = <&power RK3188_PD_VIO>;
 102                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 103                 reset-names = "axi", "ahb", "dclk";
 104                 status = "disabled";
 105
 106                 vop1_out: port {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                 };
 110         };
 111
 112         timer3: timer@2000e000 {
 113                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 114                 reg = <0x2000e000 0x20>;
 115                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 116                 clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
 117                 clock-names = "timer", "pclk";
 118         };
 119
 120         timer6: timer@200380a0 {
 121                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 122                 reg = <0x200380a0 0x20>;
 123                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 124                 clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
 125                 clock-names = "timer", "pclk";
 126         };
 127
 128         i2s0: i2s@1011a000 {
 129                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 130                 reg = <0x1011a000 0x2000>;
 131                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134                 pinctrl-names = "default";
 135                 pinctrl-0 = <&i2s0_bus>;
 136                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 137                 dma-names = "tx", "rx";
 138                 clock-names = "i2s_hclk", "i2s_clk";
 139                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 140                 rockchip,playback-channels = <2>;
 141                 rockchip,capture-channels = <2>;
 142                 #sound-dai-cells = <0>;
 143                 status = "disabled";
 144         };
 145
 146         spdif: sound@1011e000 {
 147                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 148                 reg = <0x1011e000 0x2000>;
 149                 #sound-dai-cells = <0>;
 150                 clock-names = "hclk", "mclk";
 151                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
 152                 dmas = <&dmac1_s 8>;
 153                 dma-names = "tx";
 154                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&spdif_tx>;
 157                 status = "disabled";
 158         };
 159
 160         cru: clock-controller@20000000 {
 161                 compatible = "rockchip,rk3188-cru";
 162                 reg = <0x20000000 0x1000>;
 163                 rockchip,grf = <&grf>;
 164
 165                 #clock-cells = <1>;
 166                 #reset-cells = <1>;
 167         };
 168
 169         efuse: efuse@20010000 {
 170                 compatible = "rockchip,rk3188-efuse";
 171                 reg = <0x20010000 0x4000>;
 172                 #address-cells = <1>;
 173                 #size-cells = <1>;
 174                 clocks = <&cru PCLK_EFUSE>;
 175                 clock-names = "pclk_efuse";
 176
 177                 cpu_leakage: cpu_leakage@17 {
 178                         reg = <0x17 0x1>;
 179                 };
 180         };
 181
 182         usbphy: phy {
 183                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 184                 rockchip,grf = <&grf>;
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 status = "disabled";
 188
 189                 usbphy0: usb-phy@10c {
 190                         #phy-cells = <0>;
 191                         reg = <0x10c>;
 192                         clocks = <&cru SCLK_OTGPHY0>;
 193                         clock-names = "phyclk";
 194                         #clock-cells = <0>;
 195                 };
 196
 197                 usbphy1: usb-phy@11c {
 198                         #phy-cells = <0>;
 199                         reg = <0x11c>;
 200                         clocks = <&cru SCLK_OTGPHY1>;
 201                         clock-names = "phyclk";
 202                         #clock-cells = <0>;
 203                 };
 204         };
 205
 206         pinctrl: pinctrl {
 207                 compatible = "rockchip,rk3188-pinctrl";
 208                 rockchip,grf = <&grf>;
 209                 rockchip,pmu = <&pmu>;
 210
 211                 #address-cells = <1>;
 212                 #size-cells = <1>;
 213                 ranges;
 214
 215                 gpio0: gpio0@2000a000 {
 216                         compatible = "rockchip,rk3188-gpio-bank0";
 217                         reg = <0x2000a000 0x100>;
 218                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&cru PCLK_GPIO0>;
 220
 221                         gpio-controller;
 222                         #gpio-cells = <2>;
 223
 224                         interrupt-controller;
 225                         #interrupt-cells = <2>;
 226                 };
 227
 228                 gpio1: gpio1@2003c000 {
 229                         compatible = "rockchip,gpio-bank";
 230                         reg = <0x2003c000 0x100>;
 231                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&cru PCLK_GPIO1>;
 233
 234                         gpio-controller;
 235                         #gpio-cells = <2>;
 236
 237                         interrupt-controller;
 238                         #interrupt-cells = <2>;
 239                 };
 240
 241                 gpio2: gpio2@2003e000 {
 242                         compatible = "rockchip,gpio-bank";
 243                         reg = <0x2003e000 0x100>;
 244                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&cru PCLK_GPIO2>;
 246
 247                         gpio-controller;
 248                         #gpio-cells = <2>;
 249
 250                         interrupt-controller;
 251                         #interrupt-cells = <2>;
 252                 };
 253
 254                 gpio3: gpio3@20080000 {
 255                         compatible = "rockchip,gpio-bank";
 256                         reg = <0x20080000 0x100>;
 257                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 258                         clocks = <&cru PCLK_GPIO3>;
 259
 260                         gpio-controller;
 261                         #gpio-cells = <2>;
 262
 263                         interrupt-controller;
 264                         #interrupt-cells = <2>;
 265                 };
 266
 267                 pcfg_pull_up: pcfg_pull_up {
 268                         bias-pull-up;
 269                 };
 270
 271                 pcfg_pull_down: pcfg_pull_down {
 272                         bias-pull-down;
 273                 };
 274
 275                 pcfg_pull_none: pcfg_pull_none {
 276                         bias-disable;
 277                 };
 278
 279                 emmc {
 280                         emmc_clk: emmc-clk {
 281                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 282                         };
 283
 284                         emmc_cmd: emmc-cmd {
 285                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 286                         };
 287
 288                         emmc_rst: emmc-rst {
 289                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 290                         };
 291
 292                         /*
 293                          * The data pins are shared between nandc and emmc and
 294                          * not accessible through pinctrl. Also they should've
 295                          * been already set correctly by firmware, as
 296                          * flash/emmc is the boot-device.
 297                          */
 298                 };
 299
 300                 emac {
 301                         emac_xfer: emac-xfer {
 302                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 303                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 304                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 305                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 306                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 307                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 308                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 309                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 310                         };
 311
 312                         emac_mdio: emac-mdio {
 313                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 314                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 315                         };
 316                 };
 317
 318                 i2c0 {
 319                         i2c0_xfer: i2c0-xfer {
 320                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 321                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 322                         };
 323                 };
 324
 325                 i2c1 {
 326                         i2c1_xfer: i2c1-xfer {
 327                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 328                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 329                         };
 330                 };
 331
 332                 i2c2 {
 333                         i2c2_xfer: i2c2-xfer {
 334                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 335                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 336                         };
 337                 };
 338
 339                 i2c3 {
 340                         i2c3_xfer: i2c3-xfer {
 341                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 342                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 343                         };
 344                 };
 345
 346                 i2c4 {
 347                         i2c4_xfer: i2c4-xfer {
 348                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 349                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 350                         };
 351                 };
 352
 353                 lcdc1 {
 354                         lcdc1_dclk: lcdc1-dclk {
 355                                 rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 356                         };
 357
 358                         lcdc1_den: lcdc1-den {
 359                                 rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 360                         };
 361
 362                         lcdc1_hsync: lcdc1-hsync {
 363                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
 364                         };
 365
 366                         lcdc1_vsync: lcdc1-vsync {
 367                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
 368                         };
 369
 370                         lcdc1_rgb24: ldcd1-rgb24 {
 371                                 rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
 372                                                 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
 373                                                 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
 374                                                 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
 375                                                 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
 376                                                 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
 377                                                 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
 378                                                 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
 379                                                 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
 380                                                 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
 381                                                 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
 382                                                 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
 383                                                 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
 384                                                 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
 385                                                 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
 386                                                 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
 387                                                 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
 388                                                 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
 389                                                 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
 390                                                 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
 391                                                 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
 392                                                 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
 393                                                 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
 394                                                 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
 395                         };
 396                 };
 397
 398                 pwm0 {
 399                         pwm0_out: pwm0-out {
 400                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 401                         };
 402                 };
 403
 404                 pwm1 {
 405                         pwm1_out: pwm1-out {
 406                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 407                         };
 408                 };
 409
 410                 pwm2 {
 411                         pwm2_out: pwm2-out {
 412                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 413                         };
 414                 };
 415
 416                 pwm3 {
 417                         pwm3_out: pwm3-out {
 418                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 419                         };
 420                 };
 421
 422                 spi0 {
 423                         spi0_clk: spi0-clk {
 424                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 425                         };
 426                         spi0_cs0: spi0-cs0 {
 427                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 428                         };
 429                         spi0_tx: spi0-tx {
 430                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 431                         };
 432                         spi0_rx: spi0-rx {
 433                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 434                         };
 435                         spi0_cs1: spi0-cs1 {
 436                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 437                         };
 438                 };
 439
 440                 spi1 {
 441                         spi1_clk: spi1-clk {
 442                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 443                         };
 444                         spi1_cs0: spi1-cs0 {
 445                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 446                         };
 447                         spi1_rx: spi1-rx {
 448                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 449                         };
 450                         spi1_tx: spi1-tx {
 451                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 452                         };
 453                         spi1_cs1: spi1-cs1 {
 454                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 455                         };
 456                 };
 457
 458                 uart0 {
 459                         uart0_xfer: uart0-xfer {
 460                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 461                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 462                         };
 463
 464                         uart0_cts: uart0-cts {
 465                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 466                         };
 467
 468                         uart0_rts: uart0-rts {
 469                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 470                         };
 471                 };
 472
 473                 uart1 {
 474                         uart1_xfer: uart1-xfer {
 475                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 476                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 477                         };
 478
 479                         uart1_cts: uart1-cts {
 480                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 481                         };
 482
 483                         uart1_rts: uart1-rts {
 484                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 485                         };
 486                 };
 487
 488                 uart2 {
 489                         uart2_xfer: uart2-xfer {
 490                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 491                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 492                         };
 493                         /* no rts / cts for uart2 */
 494                 };
 495
 496                 uart3 {
 497                         uart3_xfer: uart3-xfer {
 498                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 499                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 500                         };
 501
 502                         uart3_cts: uart3-cts {
 503                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 504                         };
 505
 506                         uart3_rts: uart3-rts {
 507                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 508                         };
 509                 };
 510
 511                 sd0 {
 512                         sd0_clk: sd0-clk {
 513                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 514                         };
 515
 516                         sd0_cmd: sd0-cmd {
 517                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 518                         };
 519
 520                         sd0_cd: sd0-cd {
 521                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 522                         };
 523
 524                         sd0_wp: sd0-wp {
 525                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 526                         };
 527
 528                         sd0_pwr: sd0-pwr {
 529                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 530                         };
 531
 532                         sd0_bus1: sd0-bus-width1 {
 533                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 534                         };
 535
 536                         sd0_bus4: sd0-bus-width4 {
 537                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 538                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 539                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 540                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 541                         };
 542                 };
 543
 544                 sd1 {
 545                         sd1_clk: sd1-clk {
 546                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 547                         };
 548
 549                         sd1_cmd: sd1-cmd {
 550                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 551                         };
 552
 553                         sd1_cd: sd1-cd {
 554                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 555                         };
 556
 557                         sd1_wp: sd1-wp {
 558                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 559                         };
 560
 561                         sd1_bus1: sd1-bus-width1 {
 562                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 563                         };
 564
 565                         sd1_bus4: sd1-bus-width4 {
 566                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 567                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 568                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 569                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 570                         };
 571                 };
 572
 573                 i2s0 {
 574                         i2s0_bus: i2s0-bus {
 575                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 576                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 577                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 578                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 579                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 580                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 581                         };
 582                 };
 583
 584                 spdif {
 585                         spdif_tx: spdif-tx {
 586                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 587                         };
 588                 };
 589         };
 590 };
 591
 592 &emac {
 593         compatible = "rockchip,rk3188-emac";
 594 };
 595
 596 &global_timer {
 597         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 598         status = "disabled";
 599 };
 600
 601 &local_timer {
 602         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 603 };
 604
 605 &gpu {
 606         compatible = "rockchip,rk3188-mali", "arm,mali-400";
 607         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 608                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 609                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 610                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 611                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 612                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 613                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 614                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 615                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 616                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 617         interrupt-names = "gp",
 618                           "gpmmu",
 619                           "pp0",
 620                           "ppmmu0",
 621                           "pp1",
 622                           "ppmmu1",
 623                           "pp2",
 624                           "ppmmu2",
 625                           "pp3",
 626                           "ppmmu3";
 627         power-domains = <&power RK3188_PD_GPU>;
 628 };
 629
 630 &i2c0 {
 631         compatible = "rockchip,rk3188-i2c";
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&i2c0_xfer>;
 634 };
 635
 636 &i2c1 {
 637         compatible = "rockchip,rk3188-i2c";
 638         pinctrl-names = "default";
 639         pinctrl-0 = <&i2c1_xfer>;
 640 };
 641
 642 &i2c2 {
 643         compatible = "rockchip,rk3188-i2c";
 644         pinctrl-names = "default";
 645         pinctrl-0 = <&i2c2_xfer>;
 646 };
 647
 648 &i2c3 {
 649         compatible = "rockchip,rk3188-i2c";
 650         pinctrl-names = "default";
 651         pinctrl-0 = <&i2c3_xfer>;
 652 };
 653
 654 &i2c4 {
 655         compatible = "rockchip,rk3188-i2c";
 656         pinctrl-names = "default";
 657         pinctrl-0 = <&i2c4_xfer>;
 658 };
 659
 660 &pmu {
 661         power: power-controller {
 662                 compatible = "rockchip,rk3188-power-controller";
 663                 #power-domain-cells = <1>;
 664                 #address-cells = <1>;
 665                 #size-cells = <0>;
 666
 667                 pd_vio@RK3188_PD_VIO {
 668                         reg = <RK3188_PD_VIO>;
 669                         clocks = <&cru ACLK_LCDC0>,
 670                                  <&cru ACLK_LCDC1>,
 671                                  <&cru DCLK_LCDC0>,
 672                                  <&cru DCLK_LCDC1>,
 673                                  <&cru HCLK_LCDC0>,
 674                                  <&cru HCLK_LCDC1>,
 675                                  <&cru SCLK_CIF0>,
 676                                  <&cru ACLK_CIF0>,
 677                                  <&cru HCLK_CIF0>,
 678                                  <&cru ACLK_IPP>,
 679                                  <&cru HCLK_IPP>,
 680                                  <&cru ACLK_RGA>,
 681                                  <&cru HCLK_RGA>;
 682                         pm_qos = <&qos_lcdc0>,
 683                                  <&qos_lcdc1>,
 684                                  <&qos_cif0>,
 685                                  <&qos_cif1>,
 686                                  <&qos_ipp>,
 687                                  <&qos_rga>;
 688                 };
 689
 690                 pd_video@RK3188_PD_VIDEO {
 691                         reg = <RK3188_PD_VIDEO>;
 692                         clocks = <&cru ACLK_VDPU>,
 693                                  <&cru ACLK_VEPU>,
 694                                  <&cru HCLK_VDPU>,
 695                                  <&cru HCLK_VEPU>;
 696                         pm_qos = <&qos_vpu>;
 697                 };
 698
 699                 pd_gpu@RK3188_PD_GPU {
 700                         reg = <RK3188_PD_GPU>;
 701                         clocks = <&cru ACLK_GPU>;
 702                         pm_qos = <&qos_gpu>;
 703                 };
 704         };
 705 };
 706
 707 &pwm0 {
 708         pinctrl-names = "default";
 709         pinctrl-0 = <&pwm0_out>;
 710 };
 711
 712 &pwm1 {
 713         pinctrl-names = "default";
 714         pinctrl-0 = <&pwm1_out>;
 715 };
 716
 717 &pwm2 {
 718         pinctrl-names = "default";
 719         pinctrl-0 = <&pwm2_out>;
 720 };
 721
 722 &pwm3 {
 723         pinctrl-names = "default";
 724         pinctrl-0 = <&pwm3_out>;
 725 };
 726
 727 &spi0 {
 728         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 729         pinctrl-names = "default";
 730         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 731 };
 732
 733 &spi1 {
 734         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 735         pinctrl-names = "default";
 736         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 737 };
 738
 739 &uart0 {
 740         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 741         pinctrl-names = "default";
 742         pinctrl-0 = <&uart0_xfer>;
 743 };
 744
 745 &uart1 {
 746         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 747         pinctrl-names = "default";
 748         pinctrl-0 = <&uart1_xfer>;
 749 };
 750
 751 &uart2 {
 752         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 753         pinctrl-names = "default";
 754         pinctrl-0 = <&uart2_xfer>;
 755 };
 756
 757 &uart3 {
 758         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 759         pinctrl-names = "default";
 760         pinctrl-0 = <&uart3_xfer>;
 761 };
 762
 763 &wdt {
 764         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 765 };