1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
11 #include "rk3xxx.dtsi"
14 compatible = "rockchip,rk3188";
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 clock-latency = <40000>;
27 clocks = <&cru ARMCLK>;
28 operating-points-v2 = <&cpu0_opp_table>;
29 resets = <&cru SRST_CORE0>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
36 operating-points-v2 = <&cpu0_opp_table>;
37 resets = <&cru SRST_CORE1>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 resets = <&cru SRST_CORE2>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
52 operating-points-v2 = <&cpu0_opp_table>;
53 resets = <&cru SRST_CORE3>;
57 cpu0_opp_table: opp_table0 {
58 compatible = "operating-points-v2";
62 opp-hz = /bits/ 64 <312000000>;
63 opp-microvolt = <875000>;
64 clock-latency-ns = <40000>;
67 opp-hz = /bits/ 64 <504000000>;
68 opp-microvolt = <925000>;
71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <950000>;
76 opp-hz = /bits/ 64 <816000000>;
77 opp-microvolt = <975000>;
80 opp-hz = /bits/ 64 <1008000000>;
81 opp-microvolt = <1075000>;
84 opp-hz = /bits/ 64 <1200000000>;
85 opp-microvolt = <1150000>;
88 opp-hz = /bits/ 64 <1416000000>;
89 opp-microvolt = <1250000>;
92 opp-hz = /bits/ 64 <1608000000>;
93 opp-microvolt = <1350000>;
98 compatible = "rockchip,display-subsystem";
99 ports = <&vop0_out>, <&vop1_out>;
102 sram: sram@10080000 {
103 compatible = "mmio-sram";
104 reg = <0x10080000 0x8000>;
105 #address-cells = <1>;
107 ranges = <0 0x10080000 0x8000>;
110 compatible = "rockchip,rk3066-smp-sram";
116 compatible = "rockchip,rk3188-vop";
117 reg = <0x1010c000 0x1000>;
118 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
120 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
121 power-domains = <&power RK3188_PD_VIO>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
123 reset-names = "axi", "ahb", "dclk";
127 #address-cells = <1>;
133 compatible = "rockchip,rk3188-vop";
134 reg = <0x1010e000 0x1000>;
135 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
137 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
138 power-domains = <&power RK3188_PD_VIO>;
139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
140 reset-names = "axi", "ahb", "dclk";
144 #address-cells = <1>;
149 timer3: timer@2000e000 {
150 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
151 reg = <0x2000e000 0x20>;
152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
154 clock-names = "pclk", "timer";
157 timer6: timer@200380a0 {
158 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
159 reg = <0x200380a0 0x20>;
160 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
162 clock-names = "pclk", "timer";
166 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
167 reg = <0x1011a000 0x2000>;
168 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2s0_bus>;
171 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
172 clock-names = "i2s_clk", "i2s_hclk";
173 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
174 dma-names = "tx", "rx";
175 rockchip,playback-channels = <2>;
176 rockchip,capture-channels = <2>;
177 #sound-dai-cells = <0>;
181 spdif: sound@1011e000 {
182 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
183 reg = <0x1011e000 0x2000>;
184 #sound-dai-cells = <0>;
185 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
186 clock-names = "mclk", "hclk";
189 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&spdif_tx>;
195 cru: clock-controller@20000000 {
196 compatible = "rockchip,rk3188-cru";
197 reg = <0x20000000 0x1000>;
198 rockchip,grf = <&grf>;
204 efuse: efuse@20010000 {
205 compatible = "rockchip,rk3188-efuse";
206 reg = <0x20010000 0x4000>;
207 #address-cells = <1>;
209 clocks = <&cru PCLK_EFUSE>;
210 clock-names = "pclk_efuse";
212 cpu_leakage: cpu_leakage@17 {
218 compatible = "rockchip,rk3188-pinctrl";
219 rockchip,grf = <&grf>;
220 rockchip,pmu = <&pmu>;
222 #address-cells = <1>;
226 gpio0: gpio0@2000a000 {
227 compatible = "rockchip,rk3188-gpio-bank0";
228 reg = <0x2000a000 0x100>;
229 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cru PCLK_GPIO0>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
239 gpio1: gpio1@2003c000 {
240 compatible = "rockchip,gpio-bank";
241 reg = <0x2003c000 0x100>;
242 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cru PCLK_GPIO1>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
252 gpio2: gpio2@2003e000 {
253 compatible = "rockchip,gpio-bank";
254 reg = <0x2003e000 0x100>;
255 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cru PCLK_GPIO2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
265 gpio3: gpio3@20080000 {
266 compatible = "rockchip,gpio-bank";
267 reg = <0x20080000 0x100>;
268 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cru PCLK_GPIO3>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
278 pcfg_pull_up: pcfg-pull-up {
282 pcfg_pull_down: pcfg-pull-down {
286 pcfg_pull_none: pcfg-pull-none {
292 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
296 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
300 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
304 * The data pins are shared between nandc and emmc and
305 * not accessible through pinctrl. Also they should've
306 * been already set correctly by firmware, as
307 * flash/emmc is the boot-device.
312 emac_xfer: emac-xfer {
313 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
314 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
315 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
316 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
317 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
318 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
319 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
320 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
323 emac_mdio: emac-mdio {
324 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
325 <3 RK_PD1 2 &pcfg_pull_none>;
330 i2c0_xfer: i2c0-xfer {
331 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
332 <1 RK_PD1 1 &pcfg_pull_none>;
337 i2c1_xfer: i2c1-xfer {
338 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
339 <1 RK_PD3 1 &pcfg_pull_none>;
344 i2c2_xfer: i2c2-xfer {
345 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
346 <1 RK_PD5 1 &pcfg_pull_none>;
351 i2c3_xfer: i2c3-xfer {
352 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
353 <3 RK_PB7 2 &pcfg_pull_none>;
358 i2c4_xfer: i2c4-xfer {
359 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
360 <1 RK_PD7 1 &pcfg_pull_none>;
365 lcdc1_dclk: lcdc1-dclk {
366 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
369 lcdc1_den: lcdc1-den {
370 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
373 lcdc1_hsync: lcdc1-hsync {
374 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
377 lcdc1_vsync: lcdc1-vsync {
378 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
381 lcdc1_rgb24: ldcd1-rgb24 {
382 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
383 <2 RK_PA1 1 &pcfg_pull_none>,
384 <2 RK_PA2 1 &pcfg_pull_none>,
385 <2 RK_PA3 1 &pcfg_pull_none>,
386 <2 RK_PA4 1 &pcfg_pull_none>,
387 <2 RK_PA5 1 &pcfg_pull_none>,
388 <2 RK_PA6 1 &pcfg_pull_none>,
389 <2 RK_PA7 1 &pcfg_pull_none>,
390 <2 RK_PB0 1 &pcfg_pull_none>,
391 <2 RK_PB1 1 &pcfg_pull_none>,
392 <2 RK_PB2 1 &pcfg_pull_none>,
393 <2 RK_PB3 1 &pcfg_pull_none>,
394 <2 RK_PB4 1 &pcfg_pull_none>,
395 <2 RK_PB5 1 &pcfg_pull_none>,
396 <2 RK_PB6 1 &pcfg_pull_none>,
397 <2 RK_PB7 1 &pcfg_pull_none>,
398 <2 RK_PC0 1 &pcfg_pull_none>,
399 <2 RK_PC1 1 &pcfg_pull_none>,
400 <2 RK_PC2 1 &pcfg_pull_none>,
401 <2 RK_PC3 1 &pcfg_pull_none>,
402 <2 RK_PC4 1 &pcfg_pull_none>,
403 <2 RK_PC5 1 &pcfg_pull_none>,
404 <2 RK_PC6 1 &pcfg_pull_none>,
405 <2 RK_PC7 1 &pcfg_pull_none>;
411 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
417 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
423 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
429 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
435 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
438 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
441 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
444 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
447 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
453 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
456 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
459 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
462 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
465 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
470 uart0_xfer: uart0-xfer {
471 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
472 <1 RK_PA1 1 &pcfg_pull_none>;
475 uart0_cts: uart0-cts {
476 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
479 uart0_rts: uart0-rts {
480 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
485 uart1_xfer: uart1-xfer {
486 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
487 <1 RK_PA5 1 &pcfg_pull_none>;
490 uart1_cts: uart1-cts {
491 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
494 uart1_rts: uart1-rts {
495 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
500 uart2_xfer: uart2-xfer {
501 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
502 <1 RK_PB1 1 &pcfg_pull_none>;
504 /* no rts / cts for uart2 */
508 uart3_xfer: uart3-xfer {
509 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
510 <1 RK_PB3 1 &pcfg_pull_none>;
513 uart3_cts: uart3-cts {
514 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
517 uart3_rts: uart3-rts {
518 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
524 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
528 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
532 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
536 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
540 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
543 sd0_bus1: sd0-bus-width1 {
544 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
547 sd0_bus4: sd0-bus-width4 {
548 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
549 <3 RK_PA5 1 &pcfg_pull_none>,
550 <3 RK_PA6 1 &pcfg_pull_none>,
551 <3 RK_PA7 1 &pcfg_pull_none>;
557 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
561 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
565 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
569 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
572 sd1_bus1: sd1-bus-width1 {
573 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
576 sd1_bus4: sd1-bus-width4 {
577 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
578 <3 RK_PC2 1 &pcfg_pull_none>,
579 <3 RK_PC3 1 &pcfg_pull_none>,
580 <3 RK_PC4 1 &pcfg_pull_none>;
586 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
587 <1 RK_PC1 1 &pcfg_pull_none>,
588 <1 RK_PC2 1 &pcfg_pull_none>,
589 <1 RK_PC3 1 &pcfg_pull_none>,
590 <1 RK_PC4 1 &pcfg_pull_none>,
591 <1 RK_PC5 1 &pcfg_pull_none>;
597 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
604 compatible = "rockchip,rk3188-emac";
608 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
613 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
617 compatible = "rockchip,rk3188-mali", "arm,mali-400";
618 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-names = "gp",
638 power-domains = <&power RK3188_PD_GPU>;
642 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
644 io_domains: io-domains {
645 compatible = "rockchip,rk3188-io-voltage-domain";
650 compatible = "rockchip,rk3188-usb-phy",
651 "rockchip,rk3288-usb-phy";
652 #address-cells = <1>;
656 usbphy0: usb-phy@10c {
658 clocks = <&cru SCLK_OTGPHY0>;
659 clock-names = "phyclk";
664 usbphy1: usb-phy@11c {
666 clocks = <&cru SCLK_OTGPHY1>;
667 clock-names = "phyclk";
675 compatible = "rockchip,rk3188-i2c";
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c0_xfer>;
681 compatible = "rockchip,rk3188-i2c";
682 pinctrl-names = "default";
683 pinctrl-0 = <&i2c1_xfer>;
687 compatible = "rockchip,rk3188-i2c";
688 pinctrl-names = "default";
689 pinctrl-0 = <&i2c2_xfer>;
693 compatible = "rockchip,rk3188-i2c";
694 pinctrl-names = "default";
695 pinctrl-0 = <&i2c3_xfer>;
699 compatible = "rockchip,rk3188-i2c";
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2c4_xfer>;
705 power: power-controller {
706 compatible = "rockchip,rk3188-power-controller";
707 #power-domain-cells = <1>;
708 #address-cells = <1>;
711 power-domain@RK3188_PD_VIO {
712 reg = <RK3188_PD_VIO>;
713 clocks = <&cru ACLK_LCDC0>,
726 pm_qos = <&qos_lcdc0>,
731 #power-domain-cells = <0>;
734 power-domain@RK3188_PD_VIDEO {
735 reg = <RK3188_PD_VIDEO>;
736 clocks = <&cru ACLK_VDPU>,
741 #power-domain-cells = <0>;
744 power-domain@RK3188_PD_GPU {
745 reg = <RK3188_PD_GPU>;
746 clocks = <&cru ACLK_GPU>;
748 #power-domain-cells = <0>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&pwm0_out>;
759 pinctrl-names = "default";
760 pinctrl-0 = <&pwm1_out>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pwm2_out>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&pwm3_out>;
774 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
775 pinctrl-names = "default";
776 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
780 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
781 pinctrl-names = "default";
782 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
786 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
787 pinctrl-names = "default";
788 pinctrl-0 = <&uart0_xfer>;
792 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
793 pinctrl-names = "default";
794 pinctrl-0 = <&uart1_xfer>;
798 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
799 pinctrl-names = "default";
800 pinctrl-0 = <&uart2_xfer>;
804 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
805 pinctrl-names = "default";
806 pinctrl-0 = <&uart3_xfer>;
810 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
811 power-domains = <&power RK3188_PD_VIDEO>;
815 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";