1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
11 #include "rk3xxx.dtsi"
14 compatible = "rockchip,rk3066a";
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
40 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
47 compatible = "rockchip,display-subsystem";
48 ports = <&vop0_out>, <&vop1_out>;
52 compatible = "mmio-sram";
53 reg = <0x10080000 0x10000>;
56 ranges = <0 0x10080000 0x10000>;
59 compatible = "rockchip,rk3066-smp-sram";
65 compatible = "rockchip,rk3066-vop";
66 reg = <0x1010c000 0x19c>;
67 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&cru ACLK_LCDC0>,
71 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
72 power-domains = <&power RK3066_PD_VIO>;
73 resets = <&cru SRST_LCDC0_AXI>,
74 <&cru SRST_LCDC0_AHB>,
75 <&cru SRST_LCDC0_DCLK>;
76 reset-names = "axi", "ahb", "dclk";
83 vop0_out_hdmi: endpoint@0 {
85 remote-endpoint = <&hdmi_in_vop0>;
91 compatible = "rockchip,rk3066-vop";
92 reg = <0x1010e000 0x19c>;
93 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&cru ACLK_LCDC1>,
97 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
98 power-domains = <&power RK3066_PD_VIO>;
99 resets = <&cru SRST_LCDC1_AXI>,
100 <&cru SRST_LCDC1_AHB>,
101 <&cru SRST_LCDC1_DCLK>;
102 reset-names = "axi", "ahb", "dclk";
106 #address-cells = <1>;
109 vop1_out_hdmi: endpoint@0 {
111 remote-endpoint = <&hdmi_in_vop1>;
116 hdmi: hdmi@10116000 {
117 compatible = "rockchip,rk3066-hdmi";
118 reg = <0x10116000 0x2000>;
119 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&cru HCLK_HDMI>;
121 clock-names = "hclk";
122 pinctrl-names = "default";
123 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
124 power-domains = <&power RK3066_PD_VIO>;
125 rockchip,grf = <&grf>;
129 #address-cells = <1>;
134 #address-cells = <1>;
137 hdmi_in_vop0: endpoint@0 {
139 remote-endpoint = <&vop0_out_hdmi>;
142 hdmi_in_vop1: endpoint@1 {
144 remote-endpoint = <&vop1_out_hdmi>;
155 compatible = "rockchip,rk3066-i2s";
156 reg = <0x10118000 0x2000>;
157 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&i2s0_bus>;
160 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
161 clock-names = "i2s_clk", "i2s_hclk";
162 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
163 dma-names = "tx", "rx";
164 rockchip,playback-channels = <8>;
165 rockchip,capture-channels = <2>;
166 #sound-dai-cells = <0>;
171 compatible = "rockchip,rk3066-i2s";
172 reg = <0x1011a000 0x2000>;
173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&i2s1_bus>;
176 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
177 clock-names = "i2s_clk", "i2s_hclk";
178 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
179 dma-names = "tx", "rx";
180 rockchip,playback-channels = <2>;
181 rockchip,capture-channels = <2>;
182 #sound-dai-cells = <0>;
187 compatible = "rockchip,rk3066-i2s";
188 reg = <0x1011c000 0x2000>;
189 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&i2s2_bus>;
192 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
193 clock-names = "i2s_clk", "i2s_hclk";
194 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
195 dma-names = "tx", "rx";
196 rockchip,playback-channels = <2>;
197 rockchip,capture-channels = <2>;
198 #sound-dai-cells = <0>;
202 cru: clock-controller@20000000 {
203 compatible = "rockchip,rk3066a-cru";
204 reg = <0x20000000 0x1000>;
206 clock-names = "xin24m";
207 rockchip,grf = <&grf>;
210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
211 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
212 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
213 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
214 assigned-clock-rates = <400000000>, <594000000>,
215 <300000000>, <150000000>,
216 <75000000>, <300000000>,
217 <150000000>, <75000000>;
220 timer2: timer@2000e000 {
221 compatible = "snps,dw-apb-timer";
222 reg = <0x2000e000 0x100>;
223 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
225 clock-names = "timer", "pclk";
228 efuse: efuse@20010000 {
229 compatible = "rockchip,rk3066a-efuse";
230 reg = <0x20010000 0x4000>;
231 #address-cells = <1>;
233 clocks = <&cru PCLK_EFUSE>;
234 clock-names = "pclk_efuse";
236 cpu_leakage: cpu_leakage@17 {
241 timer0: timer@20038000 {
242 compatible = "snps,dw-apb-timer";
243 reg = <0x20038000 0x100>;
244 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
246 clock-names = "timer", "pclk";
249 timer1: timer@2003a000 {
250 compatible = "snps,dw-apb-timer";
251 reg = <0x2003a000 0x100>;
252 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
254 clock-names = "timer", "pclk";
257 tsadc: tsadc@20060000 {
258 compatible = "rockchip,rk3066-tsadc";
259 reg = <0x20060000 0x100>;
260 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
261 clock-names = "saradc", "apb_pclk";
262 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
263 #io-channel-cells = <1>;
264 resets = <&cru SRST_TSADC>;
265 reset-names = "saradc-apb";
270 compatible = "rockchip,rk3066a-pinctrl";
271 rockchip,grf = <&grf>;
272 #address-cells = <1>;
276 gpio0: gpio@20034000 {
277 compatible = "rockchip,gpio-bank";
278 reg = <0x20034000 0x100>;
279 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&cru PCLK_GPIO0>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
289 gpio1: gpio@2003c000 {
290 compatible = "rockchip,gpio-bank";
291 reg = <0x2003c000 0x100>;
292 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&cru PCLK_GPIO1>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
302 gpio2: gpio@2003e000 {
303 compatible = "rockchip,gpio-bank";
304 reg = <0x2003e000 0x100>;
305 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cru PCLK_GPIO2>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
315 gpio3: gpio@20080000 {
316 compatible = "rockchip,gpio-bank";
317 reg = <0x20080000 0x100>;
318 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&cru PCLK_GPIO3>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
328 gpio4: gpio@20084000 {
329 compatible = "rockchip,gpio-bank";
330 reg = <0x20084000 0x100>;
331 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cru PCLK_GPIO4>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
341 gpio6: gpio@2000a000 {
342 compatible = "rockchip,gpio-bank";
343 reg = <0x2000a000 0x100>;
344 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&cru PCLK_GPIO6>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
354 pcfg_pull_default: pcfg-pull-default {
355 bias-pull-pin-default;
358 pcfg_pull_none: pcfg-pull-none {
363 emac_xfer: emac-xfer {
364 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
365 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
366 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
367 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
368 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
369 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
370 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
371 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
374 emac_mdio: emac-mdio {
375 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
376 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
382 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
386 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
390 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
394 * The data pins are shared between nandc and emmc and
395 * not accessible through pinctrl. Also they should've
396 * been already set correctly by firmware, as
397 * flash/emmc is the boot-device.
403 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
406 hdmii2c_xfer: hdmii2c-xfer {
407 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
408 <0 RK_PA2 1 &pcfg_pull_none>;
413 i2c0_xfer: i2c0-xfer {
414 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
415 <2 RK_PD5 1 &pcfg_pull_none>;
420 i2c1_xfer: i2c1-xfer {
421 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
422 <2 RK_PD7 1 &pcfg_pull_none>;
427 i2c2_xfer: i2c2-xfer {
428 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
429 <3 RK_PA1 1 &pcfg_pull_none>;
434 i2c3_xfer: i2c3-xfer {
435 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
436 <3 RK_PA3 2 &pcfg_pull_none>;
441 i2c4_xfer: i2c4-xfer {
442 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
443 <3 RK_PA5 1 &pcfg_pull_none>;
449 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
455 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
461 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
467 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
473 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
476 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
479 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
482 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
485 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
491 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
494 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
497 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
500 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
503 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
508 uart0_xfer: uart0-xfer {
509 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
510 <1 RK_PA1 1 &pcfg_pull_default>;
513 uart0_cts: uart0-cts {
514 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
517 uart0_rts: uart0-rts {
518 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
523 uart1_xfer: uart1-xfer {
524 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
525 <1 RK_PA5 1 &pcfg_pull_default>;
528 uart1_cts: uart1-cts {
529 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
532 uart1_rts: uart1-rts {
533 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
538 uart2_xfer: uart2-xfer {
539 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
540 <1 RK_PB1 1 &pcfg_pull_default>;
542 /* no rts / cts for uart2 */
546 uart3_xfer: uart3-xfer {
547 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
548 <3 RK_PD4 1 &pcfg_pull_default>;
551 uart3_cts: uart3-cts {
552 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
555 uart3_rts: uart3-rts {
556 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
562 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
566 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
570 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
574 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
577 sd0_bus1: sd0-bus-width1 {
578 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
581 sd0_bus4: sd0-bus-width4 {
582 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
583 <3 RK_PB3 1 &pcfg_pull_default>,
584 <3 RK_PB4 1 &pcfg_pull_default>,
585 <3 RK_PB5 1 &pcfg_pull_default>;
591 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
595 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
599 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
603 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
606 sd1_bus1: sd1-bus-width1 {
607 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
610 sd1_bus4: sd1-bus-width4 {
611 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
612 <3 RK_PC2 1 &pcfg_pull_default>,
613 <3 RK_PC3 1 &pcfg_pull_default>,
614 <3 RK_PC4 1 &pcfg_pull_default>;
620 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
621 <0 RK_PB0 1 &pcfg_pull_default>,
622 <0 RK_PB1 1 &pcfg_pull_default>,
623 <0 RK_PB2 1 &pcfg_pull_default>,
624 <0 RK_PB3 1 &pcfg_pull_default>,
625 <0 RK_PB4 1 &pcfg_pull_default>,
626 <0 RK_PB5 1 &pcfg_pull_default>,
627 <0 RK_PB6 1 &pcfg_pull_default>,
628 <0 RK_PB7 1 &pcfg_pull_default>;
634 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
635 <0 RK_PC1 1 &pcfg_pull_default>,
636 <0 RK_PC2 1 &pcfg_pull_default>,
637 <0 RK_PC3 1 &pcfg_pull_default>,
638 <0 RK_PC4 1 &pcfg_pull_default>,
639 <0 RK_PC5 1 &pcfg_pull_default>;
645 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
646 <0 RK_PD1 1 &pcfg_pull_default>,
647 <0 RK_PD2 1 &pcfg_pull_default>,
648 <0 RK_PD3 1 &pcfg_pull_default>,
649 <0 RK_PD4 1 &pcfg_pull_default>,
650 <0 RK_PD5 1 &pcfg_pull_default>;
657 compatible = "rockchip,rk3066-mali", "arm,mali-400";
658 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
668 interrupt-names = "gp",
678 power-domains = <&power RK3066_PD_GPU>;
682 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
685 compatible = "rockchip,rk3066a-usb-phy";
686 #address-cells = <1>;
690 usbphy0: usb-phy@17c {
692 clocks = <&cru SCLK_OTGPHY0>;
693 clock-names = "phyclk";
698 usbphy1: usb-phy@188 {
700 clocks = <&cru SCLK_OTGPHY1>;
701 clock-names = "phyclk";
709 pinctrl-names = "default";
710 pinctrl-0 = <&i2c0_xfer>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c1_xfer>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c2_xfer>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c3_xfer>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&i2c4_xfer>;
734 clock-frequency = <50000000>;
737 max-frequency = <50000000>;
738 pinctrl-names = "default";
739 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
755 power: power-controller {
756 compatible = "rockchip,rk3066-power-controller";
757 #power-domain-cells = <1>;
758 #address-cells = <1>;
761 power-domain@RK3066_PD_VIO {
762 reg = <RK3066_PD_VIO>;
763 clocks = <&cru ACLK_LCDC0>,
780 pm_qos = <&qos_lcdc0>,
786 #power-domain-cells = <0>;
789 power-domain@RK3066_PD_VIDEO {
790 reg = <RK3066_PD_VIDEO>;
791 clocks = <&cru ACLK_VDPU>,
796 #power-domain-cells = <0>;
799 power-domain@RK3066_PD_GPU {
800 reg = <RK3066_PD_GPU>;
801 clocks = <&cru ACLK_GPU>;
803 #power-domain-cells = <0>;
809 pinctrl-names = "default";
810 pinctrl-0 = <&pwm0_out>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&pwm1_out>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&pwm2_out>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&pwm3_out>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
839 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
840 dmas = <&dmac1_s 0>, <&dmac1_s 1>;
841 dma-names = "tx", "rx";
842 pinctrl-names = "default";
843 pinctrl-0 = <&uart0_xfer>;
847 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
848 dmas = <&dmac1_s 2>, <&dmac1_s 3>;
849 dma-names = "tx", "rx";
850 pinctrl-names = "default";
851 pinctrl-0 = <&uart1_xfer>;
855 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
856 dmas = <&dmac2 6>, <&dmac2 7>;
857 dma-names = "tx", "rx";
858 pinctrl-names = "default";
859 pinctrl-0 = <&uart2_xfer>;
863 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
864 dmas = <&dmac2 8>, <&dmac2 9>;
865 dma-names = "tx", "rx";
866 pinctrl-names = "default";
867 pinctrl-0 = <&uart3_xfer>;
871 power-domains = <&power RK3066_PD_VIDEO>;
875 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
879 compatible = "rockchip,rk3066-emac";