1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
15 compatible = "rockchip,rk3036";
17 interrupt-parent = <&gic>;
35 enable-method = "rockchip,rk3036-smp";
39 compatible = "arm,cortex-a7";
41 resets = <&cru SRST_CORE0>;
46 clock-latency = <40000>;
47 clocks = <&cru ARMCLK>;
52 compatible = "arm,cortex-a7";
54 resets = <&cru SRST_CORE1>;
59 compatible = "arm,cortex-a7-pmu";
60 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
62 interrupt-affinity = <&cpu0>, <&cpu1>;
66 compatible = "rockchip,display-subsystem";
71 compatible = "arm,armv7-timer";
72 arm,cpu-registers-not-fw-configured;
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
77 clock-frequency = <24000000>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
83 clock-output-names = "xin24m";
87 bus_intmem: sram@10080000 {
88 compatible = "mmio-sram";
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
95 compatible = "rockchip,rk3066-smp-sram";
101 compatible = "rockchip,rk3036-mali", "arm,mali-400";
102 reg = <0x10090000 0x10000>;
103 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "gp",
111 assigned-clocks = <&cru SCLK_GPU>;
112 assigned-clock-rates = <100000000>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
114 clock-names = "bus", "core";
115 power-domains = <&power RK3036_PD_GPU>;
116 resets = <&cru SRST_GPU>;
120 vpu: video-codec@10108000 {
121 compatible = "rockchip,rk3036-vpu";
122 reg = <0x10108000 0x800>;
123 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-names = "vdpu";
125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
126 clock-names = "aclk", "hclk";
128 power-domains = <&power RK3036_PD_VPU>;
131 vpu_mmu: iommu@10108800 {
132 compatible = "rockchip,iommu";
133 reg = <0x10108800 0x100>;
134 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
136 clock-names = "aclk", "iface";
137 power-domains = <&power RK3036_PD_VPU>;
142 compatible = "rockchip,rk3036-vop";
143 reg = <0x10118000 0x19c>;
144 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
146 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
147 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
148 reset-names = "axi", "ahb", "dclk";
150 power-domains = <&power RK3036_PD_VIO>;
154 #address-cells = <1>;
156 vop_out_hdmi: endpoint@0 {
158 remote-endpoint = <&hdmi_in_vop>;
163 vop_mmu: iommu@10118300 {
164 compatible = "rockchip,iommu";
165 reg = <0x10118300 0x100>;
166 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
168 clock-names = "aclk", "iface";
169 power-domains = <&power RK3036_PD_VIO>;
174 qos_gpu: qos@1012d000 {
175 compatible = "rockchip,rk3036-qos", "syscon";
176 reg = <0x1012d000 0x20>;
179 qos_vpu: qos@1012e000 {
180 compatible = "rockchip,rk3036-qos", "syscon";
181 reg = <0x1012e000 0x20>;
184 qos_vio: qos@1012f000 {
185 compatible = "rockchip,rk3036-qos", "syscon";
186 reg = <0x1012f000 0x20>;
189 gic: interrupt-controller@10139000 {
190 compatible = "arm,gic-400";
191 interrupt-controller;
192 #interrupt-cells = <3>;
193 #address-cells = <0>;
195 reg = <0x10139000 0x1000>,
199 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
202 usb_otg: usb@10180000 {
203 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
205 reg = <0x10180000 0x40000>;
206 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru HCLK_OTG0>;
210 g-np-tx-fifo-size = <16>;
211 g-rx-fifo-size = <275>;
212 g-tx-fifo-size = <256 128 128 64 64 32>;
216 usb_host: usb@101c0000 {
217 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
219 reg = <0x101c0000 0x40000>;
220 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru HCLK_OTG1>;
227 emac: ethernet@10200000 {
228 compatible = "rockchip,rk3036-emac";
229 reg = <0x10200000 0x4000>;
230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
231 rockchip,grf = <&grf>;
232 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
233 clock-names = "hclk", "macref", "macclk";
235 * Fix the emac parent clock is DPLL instead of APLL.
236 * since that will cause some unstable things if the cpufreq
237 * is working. (e.g: the accurate 50MHz what mac_ref need)
239 assigned-clocks = <&cru SCLK_MACPLL>;
240 assigned-clock-parents = <&cru PLL_DPLL>;
246 sdmmc: mmc@10214000 {
247 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
248 reg = <0x10214000 0x4000>;
249 clock-frequency = <37500000>;
250 max-frequency = <37500000>;
251 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
252 clock-names = "biu", "ciu";
253 fifo-depth = <0x100>;
254 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
255 resets = <&cru SRST_MMC0>;
256 reset-names = "reset";
261 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
262 reg = <0x10218000 0x4000>;
263 max-frequency = <37500000>;
264 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
265 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
267 fifo-depth = <0x100>;
268 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
269 resets = <&cru SRST_SDIO>;
270 reset-names = "reset";
275 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
276 reg = <0x1021c000 0x4000>;
277 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
280 clock-frequency = <37500000>;
281 max-frequency = <37500000>;
282 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
283 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
284 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
285 rockchip,default-sample-phase = <158>;
289 fifo-depth = <0x100>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
294 resets = <&cru SRST_EMMC>;
295 reset-names = "reset";
300 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
301 reg = <0x10220000 0x4000>;
302 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
303 clock-names = "i2s_clk", "i2s_hclk";
304 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
305 dmas = <&pdma 0>, <&pdma 1>;
306 dma-names = "tx", "rx";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2s_bus>;
309 #sound-dai-cells = <0>;
313 nfc: nand-controller@10500000 {
314 compatible = "rockchip,rk3036-nfc",
315 "rockchip,rk2928-nfc";
316 reg = <0x10500000 0x4000>;
317 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
319 clock-names = "ahb", "nfc";
320 assigned-clocks = <&cru SCLK_NANDC>;
321 assigned-clock-rates = <150000000>;
322 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
323 &flash_rdn &flash_rdy &flash_wrn>;
324 pinctrl-names = "default";
328 cru: clock-controller@20000000 {
329 compatible = "rockchip,rk3036-cru";
330 reg = <0x20000000 0x1000>;
332 clock-names = "xin24m";
333 rockchip,grf = <&grf>;
336 assigned-clocks = <&cru PLL_GPLL>;
337 assigned-clock-rates = <594000000>;
340 grf: syscon@20008000 {
341 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
342 reg = <0x20008000 0x1000>;
344 power: power-controller {
345 compatible = "rockchip,rk3036-power-controller";
346 #power-domain-cells = <1>;
347 #address-cells = <1>;
350 power-domain@RK3036_PD_VIO {
351 reg = <RK3036_PD_VIO>;
352 clocks = <&cru ACLK_LCDC>,
356 #power-domain-cells = <0>;
359 power-domain@RK3036_PD_VPU {
360 reg = <RK3036_PD_VPU>;
361 clocks = <&cru ACLK_VCODEC>,
364 #power-domain-cells = <0>;
367 power-domain@RK3036_PD_GPU {
368 reg = <RK3036_PD_GPU>;
369 clocks = <&cru SCLK_GPU>;
371 #power-domain-cells = <0>;
376 compatible = "syscon-reboot-mode";
378 mode-normal = <BOOT_NORMAL>;
379 mode-recovery = <BOOT_RECOVERY>;
380 mode-bootloader = <BOOT_FASTBOOT>;
381 mode-loader = <BOOT_BL_DOWNLOAD>;
385 acodec: acodec-ana@20030000 {
386 compatible = "rk3036-codec";
387 reg = <0x20030000 0x4000>;
388 rockchip,grf = <&grf>;
389 clock-names = "acodec_pclk";
390 clocks = <&cru PCLK_ACODEC>;
394 hdmi: hdmi@20034000 {
395 compatible = "rockchip,rk3036-inno-hdmi";
396 reg = <0x20034000 0x4000>;
397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&cru PCLK_HDMI>;
399 clock-names = "pclk";
400 rockchip,grf = <&grf>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&hdmi_ctl>;
406 #address-cells = <1>;
408 hdmi_in_vop: endpoint@0 {
410 remote-endpoint = <&vop_out_hdmi>;
415 timer: timer@20044000 {
416 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
417 reg = <0x20044000 0x20>;
418 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&cru PCLK_TIMER>, <&xin24m>;
420 clock-names = "pclk", "timer";
424 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
425 reg = <0x20050000 0x10>;
427 clocks = <&cru PCLK_PWM>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm0_pin>;
434 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
435 reg = <0x20050010 0x10>;
437 clocks = <&cru PCLK_PWM>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm1_pin>;
444 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
445 reg = <0x20050020 0x10>;
447 clocks = <&cru PCLK_PWM>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm2_pin>;
454 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
455 reg = <0x20050030 0x10>;
457 clocks = <&cru PCLK_PWM>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pwm3_pin>;
464 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
465 reg = <0x20056000 0x1000>;
466 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
470 clocks = <&cru PCLK_I2C1>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2c1_xfer>;
477 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
478 reg = <0x2005a000 0x1000>;
479 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
480 #address-cells = <1>;
483 clocks = <&cru PCLK_I2C2>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&i2c2_xfer>;
489 uart0: serial@20060000 {
490 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
491 reg = <0x20060000 0x100>;
492 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
495 clock-frequency = <24000000>;
496 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
497 clock-names = "baudclk", "apb_pclk";
498 pinctrl-names = "default";
499 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
503 uart1: serial@20064000 {
504 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
505 reg = <0x20064000 0x100>;
506 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
509 clock-frequency = <24000000>;
510 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
511 clock-names = "baudclk", "apb_pclk";
512 pinctrl-names = "default";
513 pinctrl-0 = <&uart1_xfer>;
517 uart2: serial@20068000 {
518 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
519 reg = <0x20068000 0x100>;
520 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
523 clock-frequency = <24000000>;
524 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
525 clock-names = "baudclk", "apb_pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&uart2_xfer>;
532 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
533 reg = <0x20072000 0x1000>;
534 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
535 #address-cells = <1>;
538 clocks = <&cru PCLK_I2C0>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c0_xfer>;
545 compatible = "rockchip,rockchip-spi";
546 reg = <0x20074000 0x1000>;
547 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
549 clock-names = "apb-pclk","spi_pclk";
550 dmas = <&pdma 8>, <&pdma 9>;
551 dma-names = "tx", "rx";
552 pinctrl-names = "default";
553 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
554 #address-cells = <1>;
559 pdma: dma-controller@20078000 {
560 compatible = "arm,pl330", "arm,primecell";
561 reg = <0x20078000 0x4000>;
562 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
565 arm,pl330-broken-no-flushp;
566 arm,pl330-periph-burst;
567 clocks = <&cru ACLK_DMAC2>;
568 clock-names = "apb_pclk";
572 compatible = "rockchip,rk3036-pinctrl";
573 rockchip,grf = <&grf>;
574 #address-cells = <1>;
578 gpio0: gpio@2007c000 {
579 compatible = "rockchip,gpio-bank";
580 reg = <0x2007c000 0x100>;
581 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cru PCLK_GPIO0>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
591 gpio1: gpio@20080000 {
592 compatible = "rockchip,gpio-bank";
593 reg = <0x20080000 0x100>;
594 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cru PCLK_GPIO1>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
604 gpio2: gpio@20084000 {
605 compatible = "rockchip,gpio-bank";
606 reg = <0x20084000 0x100>;
607 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&cru PCLK_GPIO2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
617 pcfg_pull_default: pcfg-pull-default {
618 bias-pull-pin-default;
621 pcfg_pull_none: pcfg-pull-none {
627 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
633 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
639 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
645 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
650 sdmmc_clk: sdmmc-clk {
651 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
654 sdmmc_cmd: sdmmc-cmd {
655 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
659 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
662 sdmmc_bus1: sdmmc-bus1 {
663 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
666 sdmmc_bus4: sdmmc-bus4 {
667 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
668 <1 RK_PC3 1 &pcfg_pull_default>,
669 <1 RK_PC4 1 &pcfg_pull_default>,
670 <1 RK_PC5 1 &pcfg_pull_default>;
675 sdio_bus1: sdio-bus1 {
676 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
679 sdio_bus4: sdio-bus4 {
680 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
681 <0 RK_PB4 1 &pcfg_pull_default>,
682 <0 RK_PB5 1 &pcfg_pull_default>,
683 <0 RK_PB6 1 &pcfg_pull_default>;
687 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
691 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
697 * We run eMMC at max speed; bump up drive strength.
698 * We also have external pulls, so disable the internal ones.
701 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
705 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
708 emmc_bus8: emmc-bus8 {
709 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
710 <1 RK_PD1 2 &pcfg_pull_default>,
711 <1 RK_PD2 2 &pcfg_pull_default>,
712 <1 RK_PD3 2 &pcfg_pull_default>,
713 <1 RK_PD4 2 &pcfg_pull_default>,
714 <1 RK_PD5 2 &pcfg_pull_default>,
715 <1 RK_PD6 2 &pcfg_pull_default>,
716 <1 RK_PD7 2 &pcfg_pull_default>;
721 flash_ale: flash-ale {
722 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
725 flash_bus8: flash-bus8 {
726 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
727 <1 RK_PD1 1 &pcfg_pull_default>,
728 <1 RK_PD2 1 &pcfg_pull_default>,
729 <1 RK_PD3 1 &pcfg_pull_default>,
730 <1 RK_PD4 1 &pcfg_pull_default>,
731 <1 RK_PD5 1 &pcfg_pull_default>,
732 <1 RK_PD6 1 &pcfg_pull_default>,
733 <1 RK_PD7 1 &pcfg_pull_default>;
736 flash_cle: flash-cle {
737 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
740 flash_csn0: flash-csn0 {
741 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
744 flash_rdn: flash-rdn {
745 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
748 flash_rdy: flash-rdy {
749 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
752 flash_wrn: flash-wrn {
753 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
758 emac_xfer: emac-xfer {
759 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
760 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
761 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
762 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
763 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
764 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
765 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
766 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
769 emac_mdio: emac-mdio {
770 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
771 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
776 i2c0_xfer: i2c0-xfer {
777 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
778 <0 RK_PA1 1 &pcfg_pull_none>;
783 i2c1_xfer: i2c1-xfer {
784 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
785 <0 RK_PA3 1 &pcfg_pull_none>;
790 i2c2_xfer: i2c2-xfer {
791 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
792 <2 RK_PC5 1 &pcfg_pull_none>;
798 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
799 <1 RK_PA1 1 &pcfg_pull_default>,
800 <1 RK_PA2 1 &pcfg_pull_default>,
801 <1 RK_PA3 1 &pcfg_pull_default>,
802 <1 RK_PA4 1 &pcfg_pull_default>,
803 <1 RK_PA5 1 &pcfg_pull_default>;
809 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
810 <1 RK_PB1 1 &pcfg_pull_none>,
811 <1 RK_PB2 1 &pcfg_pull_none>,
812 <1 RK_PB3 1 &pcfg_pull_none>;
817 uart0_xfer: uart0-xfer {
818 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
819 <0 RK_PC1 1 &pcfg_pull_none>;
822 uart0_cts: uart0-cts {
823 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
826 uart0_rts: uart0-rts {
827 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
832 uart1_xfer: uart1-xfer {
833 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
834 <2 RK_PC7 1 &pcfg_pull_none>;
836 /* no rts / cts for uart1 */
840 uart2_xfer: uart2-xfer {
841 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
842 <1 RK_PC3 2 &pcfg_pull_none>;
844 /* no rts / cts for uart2 */
849 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
853 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
857 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
861 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
866 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;