arch/arm/boot/dts/r9a06g032.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Europe Limited
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
  11
  12 / {
  13         compatible = "renesas,r9a06g032";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a7";
  24                         reg = <0>;
  25                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
  26                 };
  27
  28                 cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <1>;
  32                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
  33                         enable-method = "renesas,r9a06g032-smp";
  34                         cpu-release-addr = <0 0x4000c204>;
  35                 };
  36         };
  37
  38         ext_jtag_clk: extjtagclk {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41                 clock-frequency = <0>;
  42         };
  43
  44         ext_mclk: extmclk {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47                 clock-frequency = <40000000>;
  48         };
  49
  50         ext_rgmii_ref: extrgmiiref {
  51                 #clock-cells = <0>;
  52                 compatible = "fixed-clock";
  53                 clock-frequency = <0>;
  54         };
  55
  56         ext_rtc_clk: extrtcclk {
  57                 #clock-cells = <0>;
  58                 compatible = "fixed-clock";
  59                 clock-frequency = <0>;
  60         };
  61
  62         soc {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 interrupt-parent = <&gic>;
  67                 ranges;
  68
  69                 rtc0: rtc@40006000 {
  70                         compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
  71                         reg = <0x40006000 0x1000>;
  72                         interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
  73                                      <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
  74                                      <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
  75                         interrupt-names = "alarm", "timer", "pps";
  76                         clocks = <&sysctrl R9A06G032_HCLK_RTC>;
  77                         clock-names = "hclk";
  78                         power-domains = <&sysctrl>;
  79                         status = "disabled";
  80                 };
  81
  82                 wdt0: watchdog@40008000 {
  83                         compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
  84                         reg = <0x40008000 0x1000>;
  85                         interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
  86                         clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
  87                         status = "disabled";
  88                 };
  89
  90                 wdt1: watchdog@40009000 {
  91                         compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
  92                         reg = <0x40009000 0x1000>;
  93                         interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
  94                         clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
  95                         status = "disabled";
  96                 };
  97
  98                 sysctrl: system-controller@4000c000 {
  99                         compatible = "renesas,r9a06g032-sysctrl";
 100                         reg = <0x4000c000 0x1000>;
 101                         status = "okay";
 102                         #clock-cells = <1>;
 103                         #power-domain-cells = <0>;
 104
 105                         clocks = <&ext_mclk>, <&ext_rtc_clk>,
 106                                         <&ext_jtag_clk>, <&ext_rgmii_ref>;
 107                         clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
 108                         #address-cells = <1>;
 109                         #size-cells = <1>;
 110
 111                         dmamux: dma-router@a0 {
 112                                 compatible = "renesas,rzn1-dmamux";
 113                                 reg = <0xa0 4>;
 114                                 #dma-cells = <6>;
 115                                 dma-requests = <32>;
 116                                 dma-masters = <&dma0 &dma1>;
 117                         };
 118                 };
 119
 120                 pci_usb: pci@40030000 {
 121                         compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
 122                         device_type = "pci";
 123                         clocks = <&sysctrl R9A06G032_HCLK_USBH>,
 124                                  <&sysctrl R9A06G032_HCLK_USBPM>,
 125                                  <&sysctrl R9A06G032_CLK_PCI_USB>;
 126                         clock-names = "hclkh", "hclkpm", "pciclk";
 127                         power-domains = <&sysctrl>;
 128                         reg = <0x40030000 0xc00>,
 129                               <0x40020000 0x1100>;
 130                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 131                         status = "disabled";
 132
 133                         bus-range = <0 0>;
 134                         #address-cells = <3>;
 135                         #size-cells = <2>;
 136                         #interrupt-cells = <1>;
 137                         ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
 138                         /* Should map all possible DDR as inbound ranges, but
 139                          * the IP only supports a 256MB, 512MB, or 1GB window.
 140                          * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
 141                          */
 142                         dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
 143                         interrupt-map-mask = <0xf800 0 0 0x7>;
 144                         interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
 145                                          0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
 146                                          0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 147
 148                         usb@1,0 {
 149                                 reg = <0x800 0 0 0 0>;
 150                                 phys = <&usbphy>;
 151                                 phy-names = "usb";
 152                         };
 153
 154                         usb@2,0 {
 155                                 reg = <0x1000 0 0 0 0>;
 156                                 phys = <&usbphy>;
 157                                 phy-names = "usb";
 158                         };
 159                 };
 160
 161                 uart0: serial@40060000 {
 162                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 163                         reg = <0x40060000 0x400>;
 164                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 165                         reg-shift = <2>;
 166                         reg-io-width = <4>;
 167                         clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
 168                         clock-names = "baudclk", "apb_pclk";
 169                         status = "disabled";
 170                 };
 171
 172                 uart1: serial@40061000 {
 173                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 174                         reg = <0x40061000 0x400>;
 175                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 176                         reg-shift = <2>;
 177                         reg-io-width = <4>;
 178                         clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
 179                         clock-names = "baudclk", "apb_pclk";
 180                         status = "disabled";
 181                 };
 182
 183                 uart2: serial@40062000 {
 184                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 185                         reg = <0x40062000 0x400>;
 186                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 187                         reg-shift = <2>;
 188                         reg-io-width = <4>;
 189                         clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
 190                         clock-names = "baudclk", "apb_pclk";
 191                         status = "disabled";
 192                 };
 193
 194                 uart3: serial@50000000 {
 195                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 196                         reg = <0x50000000 0x400>;
 197                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 198                         reg-shift = <2>;
 199                         reg-io-width = <4>;
 200                         clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
 201                         clock-names = "baudclk", "apb_pclk";
 202                         dmas =  <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
 203                         dma-names = "rx", "tx";
 204                         status = "disabled";
 205                 };
 206
 207                 uart4: serial@50001000 {
 208                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 209                         reg = <0x50001000 0x400>;
 210                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 211                         reg-shift = <2>;
 212                         reg-io-width = <4>;
 213                         clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
 214                         clock-names = "baudclk", "apb_pclk";
 215                         dmas =  <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
 216                         dma-names = "rx", "tx";
 217                         status = "disabled";
 218                 };
 219
 220                 uart5: serial@50002000 {
 221                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 222                         reg = <0x50002000 0x400>;
 223                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 224                         reg-shift = <2>;
 225                         reg-io-width = <4>;
 226                         clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
 227                         clock-names = "baudclk", "apb_pclk";
 228                         dmas =  <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
 229                         dma-names = "rx", "tx";
 230                         status = "disabled";
 231                 };
 232
 233                 uart6: serial@50003000 {
 234                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 235                         reg = <0x50003000 0x400>;
 236                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 237                         reg-shift = <2>;
 238                         reg-io-width = <4>;
 239                         clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
 240                         clock-names = "baudclk", "apb_pclk";
 241                         dmas =  <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
 242                         dma-names = "rx", "tx";
 243                         status = "disabled";
 244                 };
 245
 246                 uart7: serial@50004000 {
 247                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 248                         reg = <0x50004000 0x400>;
 249                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 250                         reg-shift = <2>;
 251                         reg-io-width = <4>;
 252                         clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
 253                         clock-names = "baudclk", "apb_pclk";
 254                         dmas =  <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
 255                         dma-names = "rx", "tx";
 256                         status = "disabled";
 257                 };
 258
 259                 pinctrl: pinctrl@40067000 {
 260                         compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
 261                         reg = <0x40067000 0x1000>, <0x51000000 0x480>;
 262                         clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
 263                         clock-names = "bus";
 264                         status = "okay";
 265                 };
 266
 267                 nand_controller: nand-controller@40102000 {
 268                         compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
 269                         reg = <0x40102000 0x2000>;
 270                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
 272                         clock-names = "hclk", "eclk";
 273                         power-domains = <&sysctrl>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         status = "disabled";
 277                 };
 278
 279                 dma0: dma-controller@40104000 {
 280                         compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
 281                         reg = <0x40104000 0x1000>;
 282                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 283                         clock-names = "hclk";
 284                         clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
 285                         dma-channels = <8>;
 286                         dma-requests = <16>;
 287                         dma-masters = <1>;
 288                         #dma-cells = <3>;
 289                         block_size = <0xfff>;
 290                         data-width = <8>;
 291                 };
 292
 293                 dma1: dma-controller@40105000 {
 294                         compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
 295                         reg = <0x40105000 0x1000>;
 296                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 297                         clock-names = "hclk";
 298                         clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
 299                         dma-channels = <8>;
 300                         dma-requests = <16>;
 301                         dma-masters = <1>;
 302                         #dma-cells = <3>;
 303                         block_size = <0xfff>;
 304                         data-width = <8>;
 305                 };
 306
 307                 gic: interrupt-controller@44101000 {
 308                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 309                         interrupt-controller;
 310                         #interrupt-cells = <3>;
 311                         reg = <0x44101000 0x1000>, /* Distributer */
 312                               <0x44102000 0x2000>, /* CPU interface */
 313                               <0x44104000 0x2000>, /* Virt interface control */
 314                               <0x44106000 0x2000>; /* Virt CPU interface */
 315                         interrupts =
 316                                 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 317                 };
 318         };
 319
 320         timer {
 321                 compatible = "arm,armv7-timer";
 322                 interrupt-parent = <&gic>;
 323                 arm,cpu-registers-not-fw-configured;
 324                 always-on;
 325                 interrupts =
 326                         <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 327                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 328                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 329                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 330         };
 331
 332         usbphy: usb-phy {
 333                 #phy-cells = <0>;
 334                 compatible = "usb-nop-xceiv";
 335                 status = "disabled";
 336         };
 337 };