2 * Device Tree Source for the r8a7792 SoC
4 * Copyright (C) 2016 Cogent Embedded Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/r8a7792-sysc.h>
17 compatible = "renesas,r8a7792";
42 enable-method = "renesas,apmu";
46 compatible = "arm,cortex-a15";
48 clock-frequency = <1000000000>;
49 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
50 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
51 next-level-cache = <&L2_CA15>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1000000000>;
59 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
60 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
61 next-level-cache = <&L2_CA15>;
64 L2_CA15: cache-controller-0 {
68 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
73 compatible = "simple-bus";
74 interrupt-parent = <&gic>;
81 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
82 reg = <0 0xe6152000 0 0x188>;
86 gic: interrupt-controller@f1001000 {
87 compatible = "arm,gic-400";
88 #interrupt-cells = <3>;
90 reg = <0 0xf1001000 0 0x1000>,
91 <0 0xf1002000 0 0x2000>,
92 <0 0xf1004000 0 0x2000>,
93 <0 0xf1006000 0 0x2000>;
94 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
95 IRQ_TYPE_LEVEL_HIGH)>;
96 clocks = <&cpg CPG_MOD 408>;
98 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
102 irqc: interrupt-controller@e61c0000 {
103 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 reg = <0 0xe61c0000 0 0x200>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&cpg CPG_MOD 407>;
112 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
117 compatible = "arm,armv7-timer";
118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
119 IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
121 IRQ_TYPE_LEVEL_LOW)>,
122 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
123 IRQ_TYPE_LEVEL_LOW)>,
124 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
125 IRQ_TYPE_LEVEL_LOW)>;
128 rst: reset-controller@e6160000 {
129 compatible = "renesas,r8a7792-rst";
130 reg = <0 0xe6160000 0 0x0100>;
133 prr: chipid@ff000044 {
134 compatible = "renesas,prr";
135 reg = <0 0xff000044 0 4>;
138 sysc: system-controller@e6180000 {
139 compatible = "renesas,r8a7792-sysc";
140 reg = <0 0xe6180000 0 0x0200>;
141 #power-domain-cells = <1>;
144 pfc: pin-controller@e6060000 {
145 compatible = "renesas,pfc-r8a7792";
146 reg = <0 0xe6060000 0 0x144>;
149 gpio0: gpio@e6050000 {
150 compatible = "renesas,gpio-r8a7792",
151 "renesas,rcar-gen2-gpio";
152 reg = <0 0xe6050000 0 0x50>;
153 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
156 gpio-ranges = <&pfc 0 0 29>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&cpg CPG_MOD 912>;
160 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
164 gpio1: gpio@e6051000 {
165 compatible = "renesas,gpio-r8a7792",
166 "renesas,rcar-gen2-gpio";
167 reg = <0 0xe6051000 0 0x50>;
168 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
171 gpio-ranges = <&pfc 0 32 23>;
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 clocks = <&cpg CPG_MOD 911>;
175 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
179 gpio2: gpio@e6052000 {
180 compatible = "renesas,gpio-r8a7792",
181 "renesas,rcar-gen2-gpio";
182 reg = <0 0xe6052000 0 0x50>;
183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
186 gpio-ranges = <&pfc 0 64 32>;
187 #interrupt-cells = <2>;
188 interrupt-controller;
189 clocks = <&cpg CPG_MOD 910>;
190 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
194 gpio3: gpio@e6053000 {
195 compatible = "renesas,gpio-r8a7792",
196 "renesas,rcar-gen2-gpio";
197 reg = <0 0xe6053000 0 0x50>;
198 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
201 gpio-ranges = <&pfc 0 96 28>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
204 clocks = <&cpg CPG_MOD 909>;
205 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
209 gpio4: gpio@e6054000 {
210 compatible = "renesas,gpio-r8a7792",
211 "renesas,rcar-gen2-gpio";
212 reg = <0 0xe6054000 0 0x50>;
213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
216 gpio-ranges = <&pfc 0 128 17>;
217 #interrupt-cells = <2>;
218 interrupt-controller;
219 clocks = <&cpg CPG_MOD 908>;
220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
224 gpio5: gpio@e6055000 {
225 compatible = "renesas,gpio-r8a7792",
226 "renesas,rcar-gen2-gpio";
227 reg = <0 0xe6055000 0 0x50>;
228 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
231 gpio-ranges = <&pfc 0 160 17>;
232 #interrupt-cells = <2>;
233 interrupt-controller;
234 clocks = <&cpg CPG_MOD 907>;
235 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
239 gpio6: gpio@e6055100 {
240 compatible = "renesas,gpio-r8a7792",
241 "renesas,rcar-gen2-gpio";
242 reg = <0 0xe6055100 0 0x50>;
243 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
246 gpio-ranges = <&pfc 0 192 17>;
247 #interrupt-cells = <2>;
248 interrupt-controller;
249 clocks = <&cpg CPG_MOD 905>;
250 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
254 gpio7: gpio@e6055200 {
255 compatible = "renesas,gpio-r8a7792",
256 "renesas,rcar-gen2-gpio";
257 reg = <0 0xe6055200 0 0x50>;
258 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
261 gpio-ranges = <&pfc 0 224 17>;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 clocks = <&cpg CPG_MOD 904>;
265 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
269 gpio8: gpio@e6055300 {
270 compatible = "renesas,gpio-r8a7792",
271 "renesas,rcar-gen2-gpio";
272 reg = <0 0xe6055300 0 0x50>;
273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
276 gpio-ranges = <&pfc 0 256 17>;
277 #interrupt-cells = <2>;
278 interrupt-controller;
279 clocks = <&cpg CPG_MOD 921>;
280 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
284 gpio9: gpio@e6055400 {
285 compatible = "renesas,gpio-r8a7792",
286 "renesas,rcar-gen2-gpio";
287 reg = <0 0xe6055400 0 0x50>;
288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
291 gpio-ranges = <&pfc 0 288 17>;
292 #interrupt-cells = <2>;
293 interrupt-controller;
294 clocks = <&cpg CPG_MOD 919>;
295 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
299 gpio10: gpio@e6055500 {
300 compatible = "renesas,gpio-r8a7792",
301 "renesas,rcar-gen2-gpio";
302 reg = <0 0xe6055500 0 0x50>;
303 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
306 gpio-ranges = <&pfc 0 320 32>;
307 #interrupt-cells = <2>;
308 interrupt-controller;
309 clocks = <&cpg CPG_MOD 914>;
310 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
314 gpio11: gpio@e6055600 {
315 compatible = "renesas,gpio-r8a7792",
316 "renesas,rcar-gen2-gpio";
317 reg = <0 0xe6055600 0 0x50>;
318 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
321 gpio-ranges = <&pfc 0 352 30>;
322 #interrupt-cells = <2>;
323 interrupt-controller;
324 clocks = <&cpg CPG_MOD 913>;
325 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
329 dmac0: dma-controller@e6700000 {
330 compatible = "renesas,dmac-r8a7792",
332 reg = <0 0xe6700000 0 0x20000>;
333 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12", "ch13", "ch14";
354 clocks = <&cpg CPG_MOD 219>;
356 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
362 dmac1: dma-controller@e6720000 {
363 compatible = "renesas,dmac-r8a7792",
365 reg = <0 0xe6720000 0 0x20000>;
366 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "error",
383 "ch0", "ch1", "ch2", "ch3",
384 "ch4", "ch5", "ch6", "ch7",
385 "ch8", "ch9", "ch10", "ch11",
386 "ch12", "ch13", "ch14";
387 clocks = <&cpg CPG_MOD 218>;
389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
395 scif0: serial@e6e60000 {
396 compatible = "renesas,scif-r8a7792",
397 "renesas,rcar-gen2-scif", "renesas,scif";
398 reg = <0 0xe6e60000 0 64>;
399 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&cpg CPG_MOD 721>,
401 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
402 clock-names = "fck", "brg_int", "scif_clk";
403 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
404 <&dmac1 0x29>, <&dmac1 0x2a>;
405 dma-names = "tx", "rx", "tx", "rx";
406 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
411 scif1: serial@e6e68000 {
412 compatible = "renesas,scif-r8a7792",
413 "renesas,rcar-gen2-scif", "renesas,scif";
414 reg = <0 0xe6e68000 0 64>;
415 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cpg CPG_MOD 720>,
417 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
418 clock-names = "fck", "brg_int", "scif_clk";
419 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
420 <&dmac1 0x2d>, <&dmac1 0x2e>;
421 dma-names = "tx", "rx", "tx", "rx";
422 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
427 scif2: serial@e6e58000 {
428 compatible = "renesas,scif-r8a7792",
429 "renesas,rcar-gen2-scif", "renesas,scif";
430 reg = <0 0xe6e58000 0 64>;
431 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cpg CPG_MOD 719>,
433 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
434 clock-names = "fck", "brg_int", "scif_clk";
435 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
436 <&dmac1 0x2b>, <&dmac1 0x2c>;
437 dma-names = "tx", "rx", "tx", "rx";
438 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
443 scif3: serial@e6ea8000 {
444 compatible = "renesas,scif-r8a7792",
445 "renesas,rcar-gen2-scif", "renesas,scif";
446 reg = <0 0xe6ea8000 0 64>;
447 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cpg CPG_MOD 718>,
449 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
450 clock-names = "fck", "brg_int", "scif_clk";
451 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
452 <&dmac1 0x2f>, <&dmac1 0x30>;
453 dma-names = "tx", "rx", "tx", "rx";
454 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
459 hscif0: serial@e62c0000 {
460 compatible = "renesas,hscif-r8a7792",
461 "renesas,rcar-gen2-hscif", "renesas,hscif";
462 reg = <0 0xe62c0000 0 96>;
463 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cpg CPG_MOD 717>,
465 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
466 clock-names = "fck", "brg_int", "scif_clk";
467 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
468 <&dmac1 0x39>, <&dmac1 0x3a>;
469 dma-names = "tx", "rx", "tx", "rx";
470 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
475 hscif1: serial@e62c8000 {
476 compatible = "renesas,hscif-r8a7792",
477 "renesas,rcar-gen2-hscif", "renesas,hscif";
478 reg = <0 0xe62c8000 0 96>;
479 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&cpg CPG_MOD 716>,
481 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
482 clock-names = "fck", "brg_int", "scif_clk";
483 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
484 <&dmac1 0x4d>, <&dmac1 0x4e>;
485 dma-names = "tx", "rx", "tx", "rx";
486 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
491 icram0: sram@e63a0000 {
492 compatible = "mmio-sram";
493 reg = <0 0xe63a0000 0 0x12000>;
496 icram1: sram@e63c0000 {
497 compatible = "mmio-sram";
498 reg = <0 0xe63c0000 0 0x1000>;
499 #address-cells = <1>;
501 ranges = <0 0 0xe63c0000 0x1000>;
504 compatible = "renesas,smp-sram";
510 compatible = "renesas,sdhi-r8a7792";
511 reg = <0 0xee100000 0 0x328>;
512 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
513 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
514 <&dmac1 0xcd>, <&dmac1 0xce>;
515 dma-names = "tx", "rx", "tx", "rx";
516 clocks = <&cpg CPG_MOD 314>;
517 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
522 jpu: jpeg-codec@fe980000 {
523 compatible = "renesas,jpu-r8a7792",
524 "renesas,rcar-gen2-jpu";
525 reg = <0 0xfe980000 0 0x10300>;
526 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 106>;
528 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
532 avb: ethernet@e6800000 {
533 compatible = "renesas,etheravb-r8a7792",
534 "renesas,etheravb-rcar-gen2";
535 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
536 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cpg CPG_MOD 812>;
538 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
540 #address-cells = <1>;
545 /* I2C doesn't need pinmux */
547 compatible = "renesas,i2c-r8a7792",
548 "renesas,rcar-gen2-i2c";
549 reg = <0 0xe6508000 0 0x40>;
550 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cpg CPG_MOD 931>;
552 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
554 i2c-scl-internal-delay-ns = <6>;
555 #address-cells = <1>;
561 compatible = "renesas,i2c-r8a7792",
562 "renesas,rcar-gen2-i2c";
563 reg = <0 0xe6518000 0 0x40>;
564 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cpg CPG_MOD 930>;
566 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
568 i2c-scl-internal-delay-ns = <6>;
569 #address-cells = <1>;
575 compatible = "renesas,i2c-r8a7792",
576 "renesas,rcar-gen2-i2c";
577 reg = <0 0xe6530000 0 0x40>;
578 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cpg CPG_MOD 929>;
580 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
582 i2c-scl-internal-delay-ns = <6>;
583 #address-cells = <1>;
589 compatible = "renesas,i2c-r8a7792",
590 "renesas,rcar-gen2-i2c";
591 reg = <0 0xe6540000 0 0x40>;
592 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cpg CPG_MOD 928>;
594 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
596 i2c-scl-internal-delay-ns = <6>;
597 #address-cells = <1>;
603 compatible = "renesas,i2c-r8a7792",
604 "renesas,rcar-gen2-i2c";
605 reg = <0 0xe6520000 0 0x40>;
606 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cpg CPG_MOD 927>;
608 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
610 i2c-scl-internal-delay-ns = <6>;
611 #address-cells = <1>;
617 compatible = "renesas,i2c-r8a7792",
618 "renesas,rcar-gen2-i2c";
619 reg = <0 0xe6528000 0 0x40>;
620 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cpg CPG_MOD 925>;
622 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
624 i2c-scl-internal-delay-ns = <110>;
625 #address-cells = <1>;
631 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
632 reg = <0 0xe6b10000 0 0x2c>;
633 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cpg CPG_MOD 917>;
635 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
636 <&dmac1 0x17>, <&dmac1 0x18>;
637 dma-names = "tx", "rx", "tx", "rx";
638 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
641 #address-cells = <1>;
646 msiof0: spi@e6e20000 {
647 compatible = "renesas,msiof-r8a7792",
648 "renesas,rcar-gen2-msiof";
649 reg = <0 0xe6e20000 0 0x0064>;
650 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cpg CPG_MOD 000>;
652 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
653 <&dmac1 0x51>, <&dmac1 0x52>;
654 dma-names = "tx", "rx", "tx", "rx";
655 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
657 #address-cells = <1>;
662 msiof1: spi@e6e10000 {
663 compatible = "renesas,msiof-r8a7792",
664 "renesas,rcar-gen2-msiof";
665 reg = <0 0xe6e10000 0 0x0064>;
666 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&cpg CPG_MOD 208>;
668 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
669 <&dmac1 0x55>, <&dmac1 0x56>;
670 dma-names = "tx", "rx", "tx", "rx";
671 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
673 #address-cells = <1>;
678 du: display@feb00000 {
679 compatible = "renesas,du-r8a7792";
680 reg = <0 0xfeb00000 0 0x40000>;
682 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cpg CPG_MOD 724>,
686 clock-names = "du.0", "du.1";
690 #address-cells = <1>;
695 du_out_rgb0: endpoint {
700 du_out_rgb1: endpoint {
707 compatible = "renesas,can-r8a7792",
708 "renesas,rcar-gen2-can";
709 reg = <0 0xe6e80000 0 0x1000>;
710 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cpg CPG_MOD 916>,
712 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
713 clock-names = "clkp1", "clkp2", "can_clk";
714 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
720 compatible = "renesas,can-r8a7792",
721 "renesas,rcar-gen2-can";
722 reg = <0 0xe6e88000 0 0x1000>;
723 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&cpg CPG_MOD 915>,
725 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
726 clock-names = "clkp1", "clkp2", "can_clk";
727 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
732 vin0: video@e6ef0000 {
733 compatible = "renesas,vin-r8a7792",
734 "renesas,rcar-gen2-vin";
735 reg = <0 0xe6ef0000 0 0x1000>;
736 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 811>;
738 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
743 vin1: video@e6ef1000 {
744 compatible = "renesas,vin-r8a7792",
745 "renesas,rcar-gen2-vin";
746 reg = <0 0xe6ef1000 0 0x1000>;
747 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&cpg CPG_MOD 810>;
749 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
754 vin2: video@e6ef2000 {
755 compatible = "renesas,vin-r8a7792",
756 "renesas,rcar-gen2-vin";
757 reg = <0 0xe6ef2000 0 0x1000>;
758 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cpg CPG_MOD 809>;
760 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
765 vin3: video@e6ef3000 {
766 compatible = "renesas,vin-r8a7792",
767 "renesas,rcar-gen2-vin";
768 reg = <0 0xe6ef3000 0 0x1000>;
769 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 808>;
771 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
776 vin4: video@e6ef4000 {
777 compatible = "renesas,vin-r8a7792",
778 "renesas,rcar-gen2-vin";
779 reg = <0 0xe6ef4000 0 0x1000>;
780 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&cpg CPG_MOD 805>;
782 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
787 vin5: video@e6ef5000 {
788 compatible = "renesas,vin-r8a7792",
789 "renesas,rcar-gen2-vin";
790 reg = <0 0xe6ef5000 0 0x1000>;
791 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&cpg CPG_MOD 804>;
793 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
799 compatible = "renesas,vsp1";
800 reg = <0 0xfe928000 0 0x8000>;
801 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 131>;
803 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
808 compatible = "renesas,vsp1";
809 reg = <0 0xfe930000 0 0x8000>;
810 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&cpg CPG_MOD 128>;
812 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
817 compatible = "renesas,vsp1";
818 reg = <0 0xfe938000 0 0x8000>;
819 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 127>;
821 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
825 cpg: clock-controller@e6150000 {
826 compatible = "renesas,r8a7792-cpg-mssr";
827 reg = <0 0xe6150000 0 0x1000>;
828 clocks = <&extal_clk>;
829 clock-names = "extal";
831 #power-domain-cells = <0>;
836 /* External root clock */
838 compatible = "fixed-clock";
840 /* This value must be overridden by the board. */
841 clock-frequency = <0>;
844 /* External SCIF clock */
846 compatible = "fixed-clock";
848 /* This value must be overridden by the board. */
849 clock-frequency = <0>;
852 /* External CAN clock */
854 compatible = "fixed-clock";
856 /* This value must be overridden by the board. */
857 clock-frequency = <0>;